diff --git a/os/common/ports/ARMv7-M-ALT/chcore.h b/os/common/ports/ARMv7-M-ALT/chcore.h
index ca3722270..63c3e5a83 100644
--- a/os/common/ports/ARMv7-M-ALT/chcore.h
+++ b/os/common/ports/ARMv7-M-ALT/chcore.h
@@ -214,10 +214,6 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) && (PORT_ENABLE_GUARD_PAGES == TRUE)
-#error "PORT_ENABLE_GUARD_PAGES requires CH_DBG_ENABLE_STACK_CHECK"
-#endif
-
 #if (PORT_SWITCHED_REGIONS_NUMBER < 0) || (PORT_SWITCHED_REGIONS_NUMBER > 4)
   #error "invalid PORT_SWITCHED_REGIONS_NUMBER value"
 #endif
diff --git a/os/common/ports/ARMv7-M/chcore.c b/os/common/ports/ARMv7-M/chcore.c
index 45bc5875c..615d56bfe 100644
--- a/os/common/ports/ARMv7-M/chcore.c
+++ b/os/common/ports/ARMv7-M/chcore.c
@@ -289,15 +289,13 @@ void port_init(os_instance_t *oip) {
   }
 #endif
 
-#if PORT_USE_SYSCALL == TRUE
+#if (PORT_ENABLE_GUARD_PAGES == TRUE) || (PORT_USE_SYSCALL == TRUE)
   /* MPU is enabled.*/
   mpuEnable(MPU_CTRL_PRIVDEFENA);
 #endif
 }
 
-#if ((CH_DBG_ENABLE_STACK_CHECK == TRUE) &&                                 \
-     (PORT_ENABLE_GUARD_PAGES == TRUE)) ||                                  \
-    defined(__DOXYGEN__)
+#if (PORT_ENABLE_GUARD_PAGES == TRUE) || defined(__DOXYGEN__)
 /**
  * @brief   Setting up MPU region for the current thread.
  */
diff --git a/os/common/ports/ARMv7-M/chcore.h b/os/common/ports/ARMv7-M/chcore.h
index 16338b500..23acf049e 100644
--- a/os/common/ports/ARMv7-M/chcore.h
+++ b/os/common/ports/ARMv7-M/chcore.h
@@ -67,12 +67,12 @@
 /**
  * @brief   Disabled value for BASEPRI register.
  */
-#define CORTEX_BASEPRI_DISABLED         0U
+#define CORTEX_BASEPRI_DISABLED         0
 
 /**
  * @brief   Total priority levels.
  */
-#define CORTEX_PRIORITY_LEVELS          (1U << CORTEX_PRIORITY_BITS)
+#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)
 
 /**
  * @brief   Minimum priority level.
@@ -85,7 +85,13 @@
  * @brief   Maximum priority level.
  * @details The maximum allowed priority level is always zero.
  */
-#define CORTEX_MAXIMUM_PRIORITY         0U
+#define CORTEX_MAXIMUM_PRIORITY         0
+
+/**
+ * @brief   SVCALL handler priority.
+ */
+#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY +          \
+                                         CORTEX_FAST_PRIORITIES)
 
 /**
  * @brief   PendSV priority level.
@@ -98,8 +104,7 @@
 /**
  * @brief   Priority level to priority mask conversion macro.
  */
-#define CORTEX_PRIO_MASK(n)                                                 \
-  ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS))
+#define CORTEX_PRIO_MASK(n)             ((n) << (8 - CORTEX_PRIORITY_BITS))
 /** @} */
 
 /*===========================================================================*/
@@ -149,12 +154,12 @@
  * @details This size depends on the idle thread implementation, usually
  *          the idle thread should take no more space than those reserved
  *          by @p PORT_INT_REQUIRED_STACK.
- * @note    In this port it is set to 16 because the idle thread does have
+ * @note    In this port it is set to 64 because the idle thread does have
  *          a stack frame when compiling without optimizations. You may
  *          reduce this value to zero when compiling with optimizations.
  */
 #if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
-#define PORT_IDLE_THREAD_STACK_SIZE     16
+#define PORT_IDLE_THREAD_STACK_SIZE     64
 #endif
 
 /**
@@ -177,6 +182,14 @@
 #define CORTEX_ENABLE_WFI_IDLE          FALSE
 #endif
 
+/**
+ * @brief   Number of upper priority levels reserved as fast interrupts.
+ * @note    The default reserves priorities 0 and 1 for fast interrupts.
+ */
+#if !defined(CORTEX_FAST_PRIORITIES)
+#define CORTEX_FAST_PRIORITIES          2
+#endif
+
 /**
  * @brief   FPU support in context switch.
  * @details Activating this option activates the FPU support in the kernel.
@@ -209,20 +222,6 @@
 #define CORTEX_SIMPLIFIED_PRIORITY      FALSE
 #endif
 
-/**
- * @brief   SVCALL handler priority.
- * @note    The default SVCALL handler priority is defaulted to
- *          @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
- *          @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
- *          priority level.
- */
-#if !defined(CORTEX_PRIORITY_SVCALL)
-#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1U)
-#elif !PORT_IRQ_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
-/* If it is externally redefined then better perform a validity check on it.*/
-#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
-#endif
-
 /**
  * @brief   NVIC PRIGROUP initialization expression.
  * @details The default assigns all available priority bits as preemption
@@ -240,6 +239,11 @@
   #error "invalid PORT_SWITCHED_REGIONS_NUMBER value"
 #endif
 
+#if (CORTEX_FAST_PRIORITIES < 0) ||                                         \
+    (CORTEX_FAST_PRIORITIES > (CORTEX_PRIORITY_LEVELS / 8))
+#error "invalid CORTEX_FAST_PRIORITIES value specified"
+#endif
+
 /**
  * @name    Port Capabilities and Constants
  * @{
@@ -377,7 +381,12 @@
   /**
    * @brief   Maximum usable priority for normal ISRs.
    */
-  #define CORTEX_MAX_KERNEL_PRIORITY    (CORTEX_PRIORITY_SVCALL + 1U)
+  #define CORTEX_MAX_KERNEL_PRIORITY    (CORTEX_PRIORITY_SVCALL + 1)
+
+  /**
+   * @brief   Minimum usable priority for normal ISRs.
+   */
+  #define CORTEX_MIN_KERNEL_PRIORITY    (CORTEX_PRIORITY_LEVELS - 1)
 
   /**
    * @brief   BASEPRI level within kernel lock.
@@ -386,7 +395,8 @@
     CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
 
 #else
-  #define CORTEX_MAX_KERNEL_PRIORITY    0U
+  #define CORTEX_MAX_KERNEL_PRIORITY    0
+  #define CORTEX_MIN_KERNEL_PRIORITY    (CORTEX_PRIORITY_LEVELS - 1)
 #endif
 
 /* The following code is not processed when the file is included from an
@@ -535,7 +545,7 @@ struct port_context {
  * @brief   Priority level verification macro.
  */
 #define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n)                                \
-  (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
+  (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) <= CORTEX_MIN_KERNEL_PRIORITY))
 
 /**
  * @brief   Optimized thread function declaration macro.