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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16401 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2023-10-23 15:56:00 +00:00
parent b3ba26f1e0
commit 47af8f98cc
3 changed files with 119 additions and 79 deletions
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32
os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c
View File

@ -199,11 +199,11 @@ const stm32_gpdma_channel_t *gpdmaChannelAllocI(uint32_t cmask,
/* Enabling DMA clocks required by the current channels set.*/
if ((STM32_GPDMA1_MASK_ANY & mask) != 0U) {
rccEnableDMA1(true);
rccEnableGPDMA1(true);
}
#if STM32_GPDMA2_NUM_CHANNELS > 0
if ((STM32_GPDMA2_MASK_ANY & mask) != 0U) {
rccEnableDMA2(true);
rccEnableGPDMA2(true);
}
#endif
@ -260,7 +260,7 @@ const stm32_gpdma_channel_t *gpdmaChannelAlloc(uint32_t cmask,
* Trying to release a unallocated channel is an illegal operation
* and is trapped if assertions are enabled.
*
* @param[in] dmachp pointer to a stm32_dma_channel_t structure
* @param[in] dmachp pointer to a @p stm32_dma_channel_t structure
*
* @iclass
*/
@ -285,11 +285,11 @@ void gpdmaChannelFreeI(const stm32_gpdma_channel_t *dmachp) {
/* Shutting down clocks that are no more required, if any.*/
if ((gpdma.allocated_mask & STM32_GPDMA1_MASK_ANY) == 0U) {
rccDisableDMA1();
rccDisableGPDMA1();
}
#if STM32_GPDMA2_NUM_CHANNELS > 0
if ((gpdma.allocated_mask & STM32_GPDMA2_MASK_ANY) == 0U) {
rccDisableDMA2();
rccDisableGPDMA2();
}
#endif
}
@ -300,33 +300,33 @@ void gpdmaChannelFreeI(const stm32_gpdma_channel_t *dmachp) {
* Trying to release a unallocated channel is an illegal operation
* and is trapped if assertions are enabled.
*
* @param[in] dmachp pointer to a stm32_dma_channel_t structure
* @param[in] dmachp pointer to a @p stm32_dma_channel_t structure
*
* @api
*/
void gpdmaChannelFree(const stm32_gpdma_channel_t *dmachp) {
osalSysLock();
dmaStreamFreeI(dmachp);
gpdmaStreamFreeI(dmachp);
osalSysUnlock();
}
/**
* @brief Serves a DMA IRQ.
*
* @param[in] dmachp pointer to a stm32_dma_channel_t structure
* @param[in] dmachp pointer to a @p stm32_gpdma_channel_t structure
*
* @special
*/
void dmaServeInterrupt(const stm32_dma_channel_t *dmachp) {
uint32_t flags;
uint32_t selfindex = (uint32_t)dmachp->selfindex;
void gpdmaServeInterrupt(const stm32_gpdma_channel_t *dmachp) {
uint32_t csr;
uint32_t selfindex = (uint32_t)(dmachp - __stm32_gpdma_channels);
flags = (dmachp->dma->ISR >> dmachp->shift) & STM32_GPDMA_ISR_MASK;
if (flags & dmachp->channel->CCR) {
dmachp->dma->IFCR = flags << dmachp->shift;
if (dma.channels[selfindex].func) {
dma.channels[selfindex].func(dma.channels[selfindex].param, flags);
csr = dmachp->channel->CSR;
dmachp->channel->CFCR = csr;
if (csr & dmachp->channel->CCR) {
if (gpdma.channels[selfindex].func) {
gpdma.channels[selfindex].func(gpdma.channels[selfindex].param, csr);
}
}
}

112
os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h
View File

@ -31,10 +31,47 @@
/* Driver constants. */
/*===========================================================================*/
/**
* @name GPDMA registers helpers
* @{
*/
#define STM32_GPDMA_CLBAR_CLA_POS DMA_CLBAR_LBA_Pos
#define STM32_GPDMA_CLBAR_CLA_MASK (1U << STM32_GPDMA_CLBAR_CLA_POS)
#define STM32_GPDMA_CLBAR_CLA(n) ((n) << STM32_GPDMA_CLBAR_CLA_POS)
#define STM32_GPDMA_CFCR_TOF DMA_CFCR_TOF
#define STM32_GPDMA_CFCR_SUSPF DMA_CFCR_SUSPF
#define STM32_GPDMA_CFCR_USEF DMA_CFCR_USEF
#define STM32_GPDMA_CFCR_ULEF DMA_CFCR_ULEF
#define STM32_GPDMA_CFCR_DTEF DMA_CFCR_DTEF
#define STM32_GPDMA_CFCR_HTF DMA_CFCR_HTF
#define STM32_GPDMA_CFCR_TCF DMA_CFCR_TCF
#define STM32_GPDMA_CSR_FIFOL_POS DMA_CSR_FIFOL_Pos
#define STM32_GPDMA_CSR_FIFOL_MASK (1U << STM32_GPDMA_CSR_FIFOL_POS)
#define STM32_GPDMA_CSR_FIFOL(n) ((n) << STM32_GPDMA_CSR_FIFOL_POS)
#define STM32_GPDMA_CSR_TOF DMA_CSR_TOF
#define STM32_GPDMA_CSR_SUSPF DMA_CSR_SUSPF
#define STM32_GPDMA_CSR_USEF DMA_CSR_USEF
#define STM32_GPDMA_CSR_ULEF DMA_CSR_ULEF
#define STM32_GPDMA_CSR_DTEF DMA_CSR_DTEF
#define STM32_GPDMA_CSR_HTF DMA_CSR_HTF
#define STM32_GPDMA_CSR_TCF DMA_CSR_TCF
#define STM32_GPDMA_CSR_IDLEF DMA_CSR_IDLEF
#define STM32_GPDMA_CSR_ALL (DMA_CSR_TOF | DMA_CSR_SUSPF | \
DMA_CSR_USEF | DMA_CSR_ULEF | \
DMA_CSR_DTEF | DMA_CSR_HTF | \
DMA_CSR_TCF)
/** @< */
/**
* @brief Mask of interrupt flags.
*/
/**
* @brief Maximum number of transfers in a single operation.
*/
#define STM32_GPDMA_MAX_TRANSFER 65535
#define STM32_GPDMA_MAX_TRANSFER 65535
/**
* @brief Checks if a GPDMA priority is within the valid range.
@ -68,6 +105,37 @@
#define STM32_GPDMA_CHANNEL_ID_MSK(dma, ch) \
(1U << STM32_GPDMA_CHANNEL_ID(dma, ch))
/**
* @name GPDMA channels identifiers
* @{
*/
/**
* @brief Returns a pointer to a @p stm32_gpdma_channel_t structure.
*
* @param[in] id the channel numeric identifier
* @return A pointer to the @p stm32_gpdma_channel_t constant
* structure associated to the GPDMA channel.
*/
#define STM32_GPDMA_CHANNEL(id) (&__stm32_gpdma_channels[id])
#define STM32_GPDMA1_CHANNEL0 STM32_GPDMA_CHANNEL(0)
#define STM32_GPDMA1_CHANNEL1 STM32_GPDMA_CHANNEL(1)
#define STM32_GPDMA1_CHANNEL2 STM32_GPDMA_CHANNEL(2)
#define STM32_GPDMA1_CHANNEL3 STM32_GPDMA_CHANNEL(3)
#define STM32_GPDMA1_CHANNEL4 STM32_GPDMA_CHANNEL(4)
#define STM32_GPDMA1_CHANNEL5 STM32_GPDMA_CHANNEL(5)
#define STM32_GPDMA1_CHANNEL6 STM32_GPDMA_CHANNEL(6)
#define STM32_GPDMA1_CHANNEL7 STM32_GPDMA_CHANNEL(7)
#define STM32_GPDMA2_CHANNEL0 STM32_GPDMA_CHANNEL(8)
#define STM32_GPDMA2_CHANNEL1 STM32_GPDMA_CHANNEL(9)
#define STM32_GPDMA2_CHANNEL2 STM32_GPDMA_CHANNEL(10)
#define STM32_GPDMA2_CHANNEL3 STM32_GPDMA_CHANNEL(11)
#define STM32_GPDMA2_CHANNEL4 STM32_GPDMA_CHANNEL(12)
#define STM32_GPDMA2_CHANNEL5 STM32_GPDMA_CHANNEL(13)
#define STM32_GPDMA2_CHANNEL6 STM32_GPDMA_CHANNEL(14)
#define STM32_GPDMA2_CHANNEL7 STM32_GPDMA_CHANNEL(15)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -192,12 +260,12 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
* @param[in] addr value to be written in the CPAR register
*
* @special
*/
#define dmaStreamSetPeripheral(dmastp, addr) { \
#define gpdmaStreamSetPeripheral(dmastp, addr) { \
(dmastp)->channel->CPAR = (uint32_t)(addr); \
}
@ -207,12 +275,12 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
* @param[in] addr value to be written in the CMAR register
*
* @special
*/
#define dmaStreamSetMemory0(dmastp, addr) { \
#define gpdmaStreamSetMemory0(dmastp, addr) { \
(dmastp)->channel->CMAR = (uint32_t)(addr); \
}
@ -222,12 +290,12 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
* @param[in] size value to be written in the CNDTR register
*
* @special
*/
#define dmaStreamSetTransactionSize(dmastp, size) { \
#define gpdmaStreamSetTransactionSize(dmastp, size) { \
(dmastp)->channel->CNDTR = (uint32_t)(size); \
}
@ -237,12 +305,12 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
* @return The number of transfers to be performed.
*
* @special
*/
#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
#define gpdmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
/**
* @brief Programs the channel mode settings.
@ -250,12 +318,12 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
* @param[in] mode value to be written in the CCR register
*
* @special
*/
#define dmaStreamSetMode(dmastp, mode) { \
#define gpdmaStreamSetMode(dmastp, mode) { \
(dmastp)->channel->CCR = (uint32_t)(mode); \
}
@ -265,11 +333,11 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
*
* @special
*/
#define dmaStreamEnable(dmastp) { \
#define gpdmaStreamEnable(dmastp) { \
(dmastp)->channel->CCR |= STM32_GPDMA_CR_EN; \
}
@ -283,11 +351,11 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
*
* @special
*/
#define dmaStreamDisable(dmastp) { \
#define gpdmaStreamDisable(dmastp) { \
(dmastp)->channel->CCR &= ~(STM32_GPDMA_CR_TCIE | STM32_GPDMA_CR_HTIE | \
STM32_GPDMA_CR_TEIE | STM32_GPDMA_CR_EN); \
dmaStreamClearInterrupt(dmastp); \
@ -299,11 +367,11 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
*
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
#define gpdmaStreamClearInterrupt(dmastp) { \
(dmastp)->dma->IFCR = STM32_GPDMA_ISR_MASK << (dmastp)->shift; \
}
@ -314,7 +382,7 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
* @param[in] mode value to be written in the CCR register, this value
* is implicitly ORed with:
* - @p STM32_GPDMA_CR_MINC
@ -326,7 +394,7 @@ typedef struct {
* @param[in] dst destination address
* @param[in] n number of data units to copy
*/
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
#define gpdmaStartMemCopy(dmastp, mode, src, dst, n) { \
dmaStreamSetPeripheral(dmastp, src); \
dmaStreamSetMemory0(dmastp, dst); \
dmaStreamSetTransactionSize(dmastp, n); \
@ -340,9 +408,9 @@ typedef struct {
* @pre The channel must have been allocated using @p dmaStreamAlloc().
* @post After use the channel can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_gpdma_channel_t structure
* @param[in] dmastp pointer to a @p stm32_gpdma_channel_t structure
*/
#define dmaWaitCompletion(dmastp) { \
#define gpdmaWaitCompletion(dmastp) { \
while ((dmastp)->channel->CNDTR > 0U) \
; \
dmaStreamDisable(dmastp); \
@ -354,7 +422,7 @@ typedef struct {
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern const stm32_gpdma_channel_t _stm32_gpdma_channels[STM32_GPDMA_CHANNELS];
extern const stm32_gpdma_channel_t __stm32_gpdma_channels[STM32_GPDMA_CHANNELS];
#endif
#ifdef __cplusplus

54
os/hal/ports/STM32/STM32H5xx/stm32_rcc.h
View File

@ -501,82 +501,54 @@
/** @} */
/**
* @name DMA peripheral specific RCC operations
* @name GPDMA peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DMA1 peripheral clock.
* @brief Enables the GPDMA1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
#define rccEnableGPDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_GPDMA1EN, lp)
/**
* @brief Disables the DMA1 peripheral clock.
* @brief Disables the GPDMA1 peripheral clock.
*
* @api
*/
#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
#define rccDisableGPDMA1() rccDisableGPAHB1(RCC_AHB1ENR_GPDMA1EN)
/**
* @brief Resets the DMA1 peripheral.
* @brief Resets the GPDMA1 peripheral.
*
* @api
*/
#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
#define rccResetGPDMA1() rccResetAHB1(RCC_AHB1RSTR_GPDMA1RST)
/**
* @brief Enables the DMA2 peripheral clock.
* @brief Enables the GPDMA2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
#define rccEnableGPDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_GPDMA2EN, lp)
/**
* @brief Disables the DMA2 peripheral clock.
* @brief Disables the GPDMA2 peripheral clock.
*
* @api
*/
#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
#define rccDisableGPDMA2() rccDisableAHB1(RCC_AHB1ENR_GPDMA2EN)
/**
* @brief Resets the DMA2 peripheral.
* @brief Resets the GPDMA2 peripheral.
*
* @api
*/
#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
/** @} */
/**
* @name DMAMUX peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DMAMUX peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
/**
* @brief Disables the DMAMUX peripheral clock.
*
* @api
*/
#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
/**
* @brief Resets the DMAMUX peripheral.
*
* @api
*/
#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
#define rccResetGPDMA2() rccResetAHB1(RCC_AHB1RSTR_GPDMA2RST)
/** @} */
/**