I2C. Function movement in source file
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@2698 35acf78f-673a-0410-8e92-d51de3d6d3f4
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barthess
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f4bdefbd11
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@ -57,113 +57,6 @@ static i2cflags_t translate_errors(uint16_t sr) {
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}
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/* This function handle all regular interrupt conditions
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*
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*/
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static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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if ((i2cp->id_state == I2C_READY) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// start bit sent
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i2cp->id_state = I2C_MACTIVE;
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i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) |
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i2cp->id_slave_config->rw_bit; // write slave address in DR
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}
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// now "wait" interrupt with ADDR flag
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// TODO: 10 bit address handling here
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// TODO: setup here transmission via DMA like in ADC
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if ((i2cp->id_state == I2C_MACTIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){// address successfully sent
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if(i2cp->id_slave_config->rw_bit == I2C_WRITE){
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i2c_lld_txbyte(i2cp); // send first byte
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i2cp->id_state = I2C_MTRANSMIT; // change state
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}
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else {
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i2c_lld_rxbyte(i2cp); // read first byte
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i2cp->id_state = I2C_MRECEIVE; // change stat
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}
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}
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// transmitting bytes one by one
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if ((i2cp->id_state == I2C_MTRANSMIT) && (i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
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if (i2c_lld_txbyte(i2cp))
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i2cp->id_state = I2C_MWAIT_TF; // last byte written
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}
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//receiving bytes one by one
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if ((i2cp->id_state == I2C_MRECEIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){
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if (i2c_lld_txbyte(i2cp))
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i2cp->id_state = I2C_MWAIT_TF; // last byte read
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}
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// "wait" BTF bit in status register
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if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
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if (i2cp->id_slave_config->restart){ // restart need
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i2cp->id_state = I2C_MACTIVE;
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//i2cp->id_i2c->CR1 |= I2C_CR1_START; // send restart
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i2cp->id_slave_config->id_restart_callback(i2cp, i2cp->id_slave_config); // callback call
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}
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else {
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i2cp->id_state = I2C_READY;
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i2cp->id_i2c->CR1 |= I2C_CR1_STOP; // stop communication
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i2cp->id_slave_config->id_stop_callback(i2cp, i2cp->id_slave_config); // callback call
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}
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}
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}
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/* helper function, not API
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* write bytes in DR register
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* return TRUE if last byte written
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*/
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bool_t i2c_lld_txbyte(I2CDriver *i2cp) {
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// temporal variables
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#define txbuf i2cp->id_slave_config->txbuf
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#define txbufhead i2cp->id_slave_config->txbufhead
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#define txdepth i2cp->id_slave_config->txdepth
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if (txbufhead < txdepth){
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i2cp->id_i2c->DR = txbuf[txbufhead];
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txbufhead++;
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return(FALSE);
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}
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txbufhead = 0;
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#undef txbuf
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#undef txbufhead
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#undef txdepth
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return(TRUE); // last byte written
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}
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/* helper function, not API
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* read bytes from DR register
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* return TRUE if last byte read
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*/
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bool_t i2c_lld_rxbyte(I2CDriver *i2cp) {
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// temporal variables
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#define rxbuf i2cp->id_slave_config->rxbuf
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#define rxbufhead i2cp->id_slave_config->rxbufhead
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#define rxdepth i2cp->id_slave_config->rxdepth
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if (rxbufhead < rxdepth){
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rxbuf[rxbufhead] = i2cp->id_i2c->DR;
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rxbufhead++;
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return(FALSE);
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}
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rxbufhead = 0;
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#undef rxbuf
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#undef rxbufhead
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#undef rxdepth
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return(TRUE); // last byte read
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}
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static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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// TODO:remove this stub
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//simply trap for errors
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@ -172,6 +65,8 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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}
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}
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
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/**
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* @brief I2C1 event interrupt handler.
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@ -310,6 +205,108 @@ void i2c_lld_stop(I2CDriver *i2cp) {
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}
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/* helper function, not API
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* write bytes in DR register
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* return TRUE if last byte written
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*/
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bool_t i2c_lld_txbyte(I2CDriver *i2cp) {
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// temporal variables
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#define txbuf i2cp->id_slave_config->txbuf
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#define txbufhead i2cp->id_slave_config->txbufhead
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#define txdepth i2cp->id_slave_config->txdepth
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if (txbufhead < txdepth){
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i2cp->id_i2c->DR = txbuf[txbufhead];
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txbufhead++;
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return(FALSE);
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}
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txbufhead = 0;
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#undef txbuf
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#undef txbufhead
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#undef txdepth
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return(TRUE); // last byte written
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}
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/* helper function, not API
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* read bytes from DR register
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* return TRUE if last byte read
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*/
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bool_t i2c_lld_rxbyte(I2CDriver *i2cp) {
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// temporal variables
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#define rxbuf i2cp->id_slave_config->rxbuf
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#define rxbufhead i2cp->id_slave_config->rxbufhead
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#define rxdepth i2cp->id_slave_config->rxdepth
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if (rxbufhead < rxdepth){
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rxbuf[rxbufhead] = i2cp->id_i2c->DR;
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rxbufhead++;
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return(FALSE);
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}
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rxbufhead = 0;
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#undef rxbuf
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#undef rxbufhead
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#undef rxdepth
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return(TRUE); // last byte read
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}
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/* This function handle all regular interrupt conditions
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*
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*/
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static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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if ((i2cp->id_state == I2C_READY) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// start bit sent
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i2cp->id_state = I2C_MACTIVE;
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i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) |
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i2cp->id_slave_config->rw_bit; // write slave address in DR
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}
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// now "wait" interrupt with ADDR flag
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// TODO: 10 bit address handling here
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// TODO: setup here transmission via DMA like in ADC
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if ((i2cp->id_state == I2C_MACTIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){// address successfully sent
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if(i2cp->id_slave_config->rw_bit == I2C_WRITE){
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i2c_lld_txbyte(i2cp); // send first byte
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i2cp->id_state = I2C_MTRANSMIT; // change state
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}
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else {
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i2c_lld_rxbyte(i2cp); // read first byte
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i2cp->id_state = I2C_MRECEIVE; // change stat
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}
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}
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// transmitting bytes one by one
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if ((i2cp->id_state == I2C_MTRANSMIT) && (i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
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if (i2c_lld_txbyte(i2cp))
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i2cp->id_state = I2C_MWAIT_TF; // last byte written
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}
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//receiving bytes one by one
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if ((i2cp->id_state == I2C_MRECEIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){
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if (i2c_lld_txbyte(i2cp))
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i2cp->id_state = I2C_MWAIT_TF; // last byte read
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}
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// "wait" BTF bit in status register
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if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
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if (i2cp->id_slave_config->restart){ // restart need
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i2cp->id_state = I2C_MACTIVE;
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//i2cp->id_i2c->CR1 |= I2C_CR1_START; // send restart
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i2cp->id_slave_config->id_restart_callback(i2cp, i2cp->id_slave_config); // callback call
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}
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else {
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i2cp->id_state = I2C_READY;
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i2cp->id_i2c->CR1 |= I2C_CR1_STOP; // stop communication
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i2cp->id_slave_config->id_stop_callback(i2cp, i2cp->id_slave_config); // callback call
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}
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}
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}
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void i2c_lld_master_transmitI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
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//TODO: check txbytes <= sizeof(i2cscfg->txbuf) here, or in hylevel API
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