diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c index 791be5750..6fd212d86 100644 --- a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c +++ b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c @@ -562,9 +562,10 @@ void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) { (void)clk; #if STM32_SDC_SDMMC_PWRSAV -#else sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | SDMMC_CLKDIV_HS | SDMMC_CLKCR_PWRSAV; +#else + sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) | SDMMC_CLKDIV_HS; #endif #endif } @@ -583,7 +584,7 @@ void sdc_lld_stop_clk(SDCDriver *sdcp) { } /** - * @brief Switches the bus to 4 bits mode. + * @brief Switches the bus to 1, 4 or 8 bits mode. * * @param[in] sdcp pointer to the @p SDCDriver object * @param[in] mode bus mode @@ -750,7 +751,7 @@ bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes, uint8_t cmd, uint32_t arg) { uint32_t resp[1]; - if(sdc_lld_prepare_read_bytes(sdcp, buf, bytes)) + if (sdc_lld_prepare_read_bytes(sdcp, buf, bytes)) goto error; if (sdc_lld_send_cmd_short_crc(sdcp, cmd, arg, resp) diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index f497dd143..8a54f2a21 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -769,7 +769,7 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 2 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 6 +#define STM32_OTG1_ENDPOINTS 5 #define STM32_HAS_OTG2 TRUE #define STM32_OTG2_ENDPOINTS 7 @@ -1464,7 +1464,7 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 4 +#define STM32_OTG1_ENDPOINTS 3 #define STM32_HAS_OTG2 FALSE #define STM32_HAS_USB FALSE @@ -1759,7 +1759,7 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 4 +#define STM32_OTG1_ENDPOINTS 3 #define STM32_HAS_OTG2 FALSE #define STM32_HAS_USB FALSE @@ -2665,7 +2665,7 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 4 +#define STM32_OTG1_ENDPOINTS 3 #define STM32_HAS_OTG2 FALSE #define STM32_HAS_USB FALSE diff --git a/os/hal/src/hal_sdc.c b/os/hal/src/hal_sdc.c index 70a85b10f..2ae594dbb 100644 --- a/os/hal/src/hal_sdc.c +++ b/os/hal/src/hal_sdc.c @@ -120,7 +120,7 @@ static bool mode_detect(SDCDriver *sdcp) { } else { sdcp->cardmode = SDC_MODE_CARDTYPE_SDV11; - + /* Reset error flag illegal command.*/ sdc_lld_send_cmd_none(sdcp, MMCSD_CMD_GO_IDLE_STATE, 0); } @@ -464,7 +464,7 @@ static bool mmc_set_bus_width(SDCDriver *sdcp) { uint32_t resp[1]; uint32_t cmdarg = mmc_cmd6_construct(MMC_SWITCH_WRITE_BYTE, 183, 0, 0); - switch(sdcp->config->bus_width){ + switch (sdcp->config->bus_width) { case SDC_MODE_1BIT: /* Nothing to do. Bus is already in 1bit mode.*/ return HAL_SUCCESS; @@ -807,7 +807,7 @@ bool sdcRead(SDCDriver *sdcp, uint32_t startblk, uint8_t *buf, uint32_t n) { osalDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0U)); osalDbgAssert(sdcp->state == BLK_READY, "invalid state"); - if ((startblk + n - 1U) > sdcp->capacity){ + if ((startblk + n - 1U) > sdcp->capacity) { sdcp->errors |= SDC_OVERFLOW_ERROR; return HAL_FAILED; } @@ -845,7 +845,7 @@ bool sdcWrite(SDCDriver *sdcp, uint32_t startblk, osalDbgCheck((sdcp != NULL) && (buf != NULL) && (n > 0U)); osalDbgAssert(sdcp->state == BLK_READY, "invalid state"); - if ((startblk + n - 1U) > sdcp->capacity){ + if ((startblk + n - 1U) > sdcp->capacity) { sdcp->errors |= SDC_OVERFLOW_ERROR; return HAL_FAILED; }