git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@634 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
140c2d06cd
commit
48d08ca947
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@ -90,12 +90,13 @@ void hwinit1(void) {
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* NVIC/SCB initialization.
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*/
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SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4).
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SCB_SHPR(2) = 0xF0 << 16; // PendSV at lowest priority.
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NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL);
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NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK);
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NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV);
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/*
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* SysTick initialization.
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*/
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SCB_SHPR(2) |= 0x40 << 24; // SysTick at priority 4:0.
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ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
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ST_CVR = 0;
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ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS;
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@ -103,7 +104,7 @@ void hwinit1(void) {
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/*
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* Other subsystems initialization.
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*/
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InitSerial(0x80, 0x80, 0x80);
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InitSerial(0xC0, 0xC0, 0xC0);
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/*
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* ChibiOS/RT initialization.
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@ -84,7 +84,7 @@ WARN_LOGFILE =
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#---------------------------------------------------------------------------
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# configuration options related to the input files
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#---------------------------------------------------------------------------
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INPUT = ../src/include ../src/templates ../src ../docs/ch.txt ../src/lib ../ports/ARM7
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INPUT = ../src/include ../src/templates ../src ../docs/ch.txt ../src/lib ../ports/ARM7 ../ports/ARMCM3
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INPUT_ENCODING = UTF-8
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FILE_PATTERNS = *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py *.ddf
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RECURSIVE = YES
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64
docs/ch.txt
64
docs/ch.txt
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@ -77,7 +77,7 @@
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* state unless differently specified.<br>
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* Examples: @p chThdCreateStatic(), @p chSemSignalI(), @p chIQGetTimeout().
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*
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* @section interrupts Interrupt Classes
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* @section interrupt_classes Interrupt Classes
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* In ChibiOS/RT there are three logical interrupt classes:
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* - <b>Regular Interrupts</b>. Maskable interrupt sources that cannot
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* preempt the kernel code and are thus able to invoke operating system APIs
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@ -280,68 +280,6 @@
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*/
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/** @} */
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/**
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* @defgroup ARMCM3 ARM Cortex-M3
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* @{
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* <p>
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* The ARM Cortex-M3 port is organized as follow:
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* </p>
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* <ul>
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* <li>The @p main() function is invoked in thread-privileged mode.</li>
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* <li>Each thread has a private process stack, the system has a single main
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* stack where all the interrupts and exceptions are processed.</li>
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* <li>Only the 4 MSb of the priority level are used, the 4 LSb are assumed
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* to be zero.</li>
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* <li>The threads are started in thread-privileged mode with BASEPRI level
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* 0x00 (disabled).</li>
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* <li>The kernel raises its BASEPRI level to 0x10 in order to protect the
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* system mutex zones. Note that exceptions with level 0x00 can preempt
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* the kernel, such exception handlers cannot invoke kernel APIs directly.
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* It is possible to modify the priority levels by editing the
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* <b>./ports/ARMCM3/chcore.h</b> file.</li>
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* <li>Interrupt nesting and the other advanced NVIC features are supported.</li>
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* <li>The SVC instruction and vector, with parameter #0, is internally used
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* for commanded context switching.<br>
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* It is possible to share the SVC handler at the cost of slower context
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* switching.</li>
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* <li>The PendSV vector is internally used for preemption context switching.</li>
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* </ul>
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* @ingroup Ports
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*/
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/** @} */
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/**
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* @defgroup ARMCM3CONF Configuration Options
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* @{
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* <p>
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* The ARMCM3 port allows some architecture-specific configurations settings
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* that can be specified externally, as example on the compiler command line:
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* <ul>
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* <li>@p INT_REQUIRED_STACK, this value represent the amount of stack space used
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* by an interrupt handler between the @p extctx and @p intctx
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* structures.<br>
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* In the current implementation this value is guaranteed to be zero so
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* there is no need to modify this value unless changes are done at the
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* interrupts handling code.</li>
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* <li>@p BASEPRI_USER, this is the @p BASEPRI value for the user threads. The
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* default value is @p 0 (disabled).<br>
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* Usually there is no need to change this value, please refer to the
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* Cortex-M3 technical reference manual for a detailed description.</li>
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* <li>@p BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock code.
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* The default value is 0x10.<br>
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* Code running at higher priority levels must not invoke any OS API.<br>
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* Usually there is no need to change this value, please refer to the
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* Cortex-M3 technical reference manual for a detailed description.</li>
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* <li>@p ENABLE_WFI_IDLE, if set to @p 1 enables the use of the @p wfi
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* instruction from within the idle loop. This is defaulted to 0 because
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* it can create problems with some debuggers. Setting this option to 1
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* reduces the system power requirements.</li>
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* </ul>
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* </p>
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* @ingroup ARMCM3
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*/
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/** @} */
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/**
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* @defgroup STM32F103 STM32F103 Support
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* @{
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@ -28,14 +28,18 @@
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* Prints a message on the system console.
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* @param msg pointer to the message
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*/
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/** @cond never */
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__attribute__((weak))
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/** @endcond */
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void port_puts(char *msg) {
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}
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/**
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* Halts the system.
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*/
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/** @cond never */
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__attribute__((weak))
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/** @endcond */
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void port_halt(void) {
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port_disable();
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@ -105,7 +105,7 @@
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/** @} */
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/**
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* @defgroup ARM7CONF Configuration Options
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* @defgroup ARM7_CONF Configuration Options
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* @{
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* @brief ARM7 specific configuration options.
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* @details The ARM7 port allows some architecture-specific configurations
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@ -133,7 +133,8 @@
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* @brief ARM7 specific port code, structures and macros.
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*
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* @ingroup ARM7
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* @file ports/ARM7/chcore.h Port related structures and macros.
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* @file ports/ARM7/chtypes.h Port types.
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* @file ports/ARM7/chcore.h Port related structures and macros.
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* @file ports/ARM7/chcore.c Port related code.
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*/
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/** @} */
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@ -32,7 +32,9 @@
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* it in your application code.
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* @param msg pointer to the message string
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*/
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/** @cond never */
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__attribute__((weak))
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/** @endcond */
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void port_puts(char *msg) {
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}
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@ -41,7 +43,9 @@ void port_puts(char *msg) {
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* @note The function is declared as a weak symbol, it is possible to redefine
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* it in your application code.
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*/
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/** @cond never */
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__attribute__((weak))
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/** @endcond */
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void port_halt(void) {
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port_disable();
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@ -53,7 +57,9 @@ void port_halt(void) {
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* Start a thread by invoking its work function.
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* If the work function returns @p chThdExit() is automatically invoked.
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*/
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/** @cond never */
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__attribute__((naked, weak))
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/** @endcond */
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void threadstart(void) {
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asm volatile ("blx r1 \n\t" \
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@ -79,7 +85,9 @@ CH_IRQ_HANDLER void SysTickVector(void) {
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/**
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* The SVC vector is used for commanded context switch.
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*/
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/** @cond never */
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__attribute__((naked))
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/** @endcond */
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void SVCallVector(Thread *otp, Thread *ntp) {
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/* { r0 = otp, r1 = ntp } */
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/* get the BASEPRI in r3 */
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@ -146,7 +154,9 @@ void SVCallVector(Thread *otp, Thread *ntp) {
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/**
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* Preemption invoked context switch.
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*/
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/** @cond never */
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__attribute__((naked))
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/** @endcond */
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void PendSVVector(void) {
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Thread *otp;
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register struct intctx *sp_thd asm("r12");
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@ -28,16 +28,51 @@
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/*
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* Port-related configuration parameters.
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*/
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#ifndef BASEPRI_USER
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#define BASEPRI_USER 0 /* User level BASEPRI, 0 = disabled. */
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#endif
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#ifndef BASEPRI_KERNEL
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#define BASEPRI_KERNEL 0x10 /* BASEPRI level within kernel lock. */
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#endif
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/** Enables the use of the WFI ins. */
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#ifndef ENABLE_WFI_IDLE
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#define ENABLE_WFI_IDLE 0 /* Enables the use of the WFI ins. */
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#define ENABLE_WFI_IDLE 0
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#endif
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/** BASEPRI user level, 0 = disabled. */
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#ifndef BASEPRI_USER
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#define BASEPRI_USER 0
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#endif
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/**
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* BASEPRI level within kernel lock.
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* Priority levels higher than this one (lower values) are unaffected by
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* the OS activity and can be classified as fast interrupt sources, see
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* @ref interrupt_classes.
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*/
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#ifndef BASEPRI_KERNEL
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#define BASEPRI_KERNEL 0x40
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#endif
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/**
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* SVCALL handler priority.
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* @note This priority must always be one level above the @p BASEPRI_KERNEL
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* value.
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* @note It is recommended to leave this priority level for this handler alone.
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*/
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#ifndef PRIORITY_SVCALL
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#define PRIORITY_SVCALL (BASEPRI_KERNEL - 0x10)
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#endif
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/** SYSTICK handler priority. */
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#ifndef PRIORITY_SYSTICK
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#define PRIORITY_SYSTICK 0x80
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#endif
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/**
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* PENDSV handler priority.
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* @note It is recommended to leave this priority level for this handler alone.
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* @note This is a reserved handler and its priority must always be the
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* lowest priority in the system in order to be always executed last
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* in the interrupt servicing chain.
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*/
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#ifndef PRIORITY_PENDSV
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#define PRIORITY_PENDSV 0xF0
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#endif
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/**
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@ -37,6 +37,8 @@
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.thumb_func
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.global ResetHandler
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ResetHandler:
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/* Interrupts globally masked. */
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cpsid i
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/*
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* Stack pointers initialization.
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*/
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@ -47,9 +49,7 @@ ResetHandler:
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msr PSP, r0
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// ldr r1, =__process_stack_size__
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// sub r0, r0, r1
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/*
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* Early initialization.
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*/
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/* Early initialization. */
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bl hwinit0
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/*
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* Data initialization.
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@ -76,22 +76,13 @@ bloop:
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itt lo
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strlo r0, [r1], #4
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blo bloop
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/*
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* Switches to the Process Stack and disables the interrupts globally.
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*/
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/* Switches to the Process Stack. */
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movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
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msr CONTROL, r0
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isb
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movs r0, #0x10
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msr BASEPRI, r0
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cpsie i
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/*
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* Late initialization.
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*/
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/* Late initialization. */
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bl hwinit1
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/*
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* main(0, NULL).
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*/
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/* main(0, NULL). */
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movs r0, #0
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mov r1, r0
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bl main
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@ -20,9 +20,27 @@
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#include <ch.h>
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#include <nvic.h>
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/**
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* Sets the priority of an interrupt handler and enables it.
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* @param n the interrupt number
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* @param prio the interrupt priority
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* @note The parameters are not tested for correctness.
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*/
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void NVICEnableVector(uint32_t n, uint32_t prio) {
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int sh = (n & 3) << 3;
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unsigned sh = (n & 3) << 3;
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NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
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NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
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}
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/**
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* Changes the priority of a system handler.
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* @param handler the system handler number
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* @param prio the system handler priority
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* @note The parameters are not tested for correctness.
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*/
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void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
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unsigned sh = (handler & 3) * 8;
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SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & ~(0xFF << sh)) | (prio << sh);
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}
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|
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@ -20,6 +20,22 @@
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#ifndef _NVIC_H_
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#define _NVIC_H_
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/*
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* System vector constants for @p NVICSetSystemHandlerPriority().
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*/
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#define HANDLER_MEM_MANAGE 0
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#define HANDLER_BUS_FAULT 1
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#define HANDLER_USAGE_FAULT 2
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#define HANDLER_RESERVED_3 3
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#define HANDLER_RESERVED_4 4
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#define HANDLER_RESERVED_5 5
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#define HANDLER_RESERVED_6 6
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#define HANDLER_SVCALL 7
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#define HANDLER_DEBUG_MONITOR 8
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#define HANDLER_RESERVED_9 9
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#define HANDLER_PENDSV 10
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#define HANDLER_SYSTICK 11
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typedef volatile unsigned char IOREG8;
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typedef volatile unsigned int IOREG32;
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@ -132,6 +148,7 @@ typedef struct {
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extern "C" {
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#endif
|
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void NVICEnableVector(uint32_t n, uint32_t prio);
|
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void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
|
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#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
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|
|
@ -0,0 +1,108 @@
|
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/**
|
||||
* @defgroup ARMCM3 ARM Cortex-M3
|
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* @{
|
||||
* @details The ARM Cortex-M3 architecture is quite complex for a
|
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* microcontroller and some explanations are required about the port choices.
|
||||
*
|
||||
* @section ARMCM3_STATES Mapping of the System States in the ARM Cortex-M3 port
|
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
|
||||
* Cortex-M3 port:
|
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* - <b>Initialization</b>. This state is represented by the startup code and
|
||||
* the initialization code before @p chSysInit() is executed. It has not a
|
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* special hardware state associated.
|
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* - <b>Normal</b>. This is the state the system has after executing
|
||||
* @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
|
||||
* set at @p BASEPRI_USER level, interrupts are not masked. The processor
|
||||
* is running in thread-privileged mode.
|
||||
* - <b>Suspended</b>. In this state the interrupt sources are not globally
|
||||
* masked but the BASEPRI register is set to @p BASEPRI_KERNEL thus masking
|
||||
* any interrupt source with lower or equal priority. The processor
|
||||
* is running in thread-privileged mode.
|
||||
* - <b>Disabled</b>. Interrupt sources are globally masked. The processor
|
||||
* is running in thread-privileged mode.
|
||||
* - <b>Sleep</b>. This state is entered with the execution of the specific
|
||||
* instruction @p <b>wfi</b>.
|
||||
* - <b>S-Locked</b>. In this state the interrupt sources are not globally
|
||||
* masked but the BASEPRI register is set to @p BASEPRI_KERNEL thus masking
|
||||
* any interrupt source with lower or equal priority. The processor
|
||||
* is running in thread-privileged mode.
|
||||
* - <b>I-Locked</b>. In this state the interrupt sources are not globally
|
||||
* masked but the BASEPRI register is set to @p BASEPRI_KERNEL thus masking
|
||||
* any interrupt source with lower or equal priority. The processor
|
||||
* is running in exception-privileged mode.
|
||||
* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
|
||||
* not globally masked but only interrupts with higher priority can preempt
|
||||
* the current handler. The processor is running in exception-privileged mode.
|
||||
* - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
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||||
* but it is not possible to switch to the I-Locked state because fast
|
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* interrupts can preempt the kernel critical zone.
|
||||
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
|
||||
* asynchronous NMI vector and several synchronous fault vectors that can
|
||||
* be considered to be in this category.
|
||||
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
|
||||
* the maskable interrupt sources. The ARM state is whatever the processor
|
||||
* was running when @p chSysHalt() was invoked.
|
||||
*
|
||||
* @section ARMCM3_NOTES The ARM Cortex-M3 port notes
|
||||
* The ARM Cortex-M3 port is organized as follow:
|
||||
* - The @p main() function is invoked in thread-privileged mode.
|
||||
* - Each thread has a private process stack, the system has a single main
|
||||
* stack where all the interrupts and exceptions are processed.
|
||||
* - Only the 4 MSb of the priority level are used, the 4 LSb are assumed
|
||||
* to be zero.
|
||||
* - The threads are started in thread-privileged mode with BASEPRI level
|
||||
* 0x00 (disabled).
|
||||
* - The kernel raises its BASEPRI level to @p BASEPRI_KERNEL in order to
|
||||
* protect the kernel data structures.
|
||||
* - Interrupt nesting and the other advanced NVIC features are supported.
|
||||
* - The SVC instruction and vector, with parameter #0, is internally used
|
||||
* for commanded context switching.<br>
|
||||
* It is possible to share the SVC handler at the cost of slower context
|
||||
* switching.
|
||||
* - The PendSV vector is internally used for preemption context switching.
|
||||
*
|
||||
* @ingroup Ports
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARMCM3_CONF Configuration Options
|
||||
* @{
|
||||
* @brief ARM Cortex-M3 Configuration Options.
|
||||
* The ARMCM3 port allows some architecture-specific configurations settings
|
||||
* that can be specified externally, as example on the compiler command line:
|
||||
* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
|
||||
* by an interrupt handler between the @p extctx and @p intctx
|
||||
* structures.<br>
|
||||
* In the current implementation this value is guaranteed to be zero so
|
||||
* there is no need to modify this value unless changes are done at the
|
||||
* interrupts handling code.
|
||||
* - @p BASEPRI_USER, this is the @p BASEPRI value for the user threads. The
|
||||
* default value is @p 0 (disabled).<br>
|
||||
* Usually there is no need to change this value, please refer to the
|
||||
* Cortex-M3 technical reference manual for a detailed description.
|
||||
* - @p BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock code.
|
||||
* The default value is 0x10.<br>
|
||||
* Code running at higher priority levels must not invoke any OS API.<br>
|
||||
* Usually there is no need to change this value, please refer to the
|
||||
* Cortex-M3 technical reference manual for a detailed description.
|
||||
* - @p ENABLE_WFI_IDLE, if set to @p 1 enables the use of the @p <b>wfi</b>
|
||||
* instruction from within the idle loop. This is defaulted to 0 because
|
||||
* it can create problems with some debuggers. Setting this option to 1
|
||||
* reduces the system power requirements.
|
||||
*
|
||||
* @ingroup ARMCM3
|
||||
*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup ARMCM3_CORE ARM Cortex-M3 Core Implementation
|
||||
* @{
|
||||
* @brief ARM Cortex-M3 specific port code, structures and macros.
|
||||
*
|
||||
* @ingroup ARMCM3
|
||||
* @file ports/ARMCM3/chtypes.h Port types.
|
||||
* @file ports/ARMCM3/chcore.h Port related structures and macros.
|
||||
* @file ports/ARMCM3/chcore.c Port related code.
|
||||
*/
|
||||
/** @} */
|
||||
|
|
@ -85,8 +85,9 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process,
|
|||
CH_IRQ_PROLOGUE() and CH_IRQ_EPILOGUE() in order to make very clear that
|
||||
those are not functions but inlined code. Also introduced a new macro
|
||||
CH_IRQ_HANDLER that should be used when declaring an interrupt handler.
|
||||
- Improved ARM7 and Cortex-M3 support.
|
||||
- Introduced the concept of interrupt classes, see the documentation.
|
||||
- Introduced the concept of system state, see the documentation.
|
||||
- Introduced the concept of system states, see the documentation.
|
||||
- Huge improvements to the ports documentation.
|
||||
|
||||
*** 1.0.0rc2 ***
|
||||
|
|
|
|||
Loading…
Reference in New Issue