Updated the ADXL355 demo to work with the SDP-K1
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16112 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Rocco Marco Guglielmi
parent
4689cabc31
commit
4a9310c615
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@ -47,4 +47,5 @@
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</storageModule>
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<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
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<storageModule moduleId="refreshScope"/>
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<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
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</cproject>
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@ -27,7 +27,7 @@
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<link>
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<name>board</name>
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<type>2</type>
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<locationURI>CHIBIOS/os/hal/boards/ST_NUCLEO64_F401RE</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/ADI_EVAL_SDP_CK1Z</locationURI>
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</link>
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<link>
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<name>os</name>
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@ -71,7 +71,7 @@ endif
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# FPU-related options.
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ifeq ($(USE_FPU_OPT),)
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USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
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USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16
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endif
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#
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@ -101,7 +101,7 @@ include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.m
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# HAL-OSAL files (optional).
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk
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include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F401RE/board.mk
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include $(CHIBIOS)/os/hal/boards/ADI_EVAL_SDP_CK1Z/board.mk
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include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
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# RTOS files (optional).
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include $(CHIBIOS)/os/rt/rt.mk
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@ -113,8 +113,8 @@ include $(CHIBIOS)/tools/mk/autobuild.mk
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# Other files (optional).
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include $(CHIBIOS)/os/hal/lib/streams/streams.mk
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# Define linker script file here.
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LDSCRIPT= $(STARTUPLD)/STM32F401xE.ld
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# Define linker script file here
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LDSCRIPT= $(STARTUPLD)/STM32F469xI.ld
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# C sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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@ -32,7 +32,8 @@
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*/
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#define STM32F4xx_MCUCONF
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#define STM32F401_MCUCONF
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#define STM32F469_MCUCONF
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#define STM32F479_MCUCONF
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/*
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* HAL driver system settings.
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@ -43,27 +44,35 @@
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_CLOCK48_REQUIRED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSI
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#define STM32_PLLM_VALUE 16
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#define STM32_PLLN_VALUE 336
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#define STM32_PLLP_VALUE 4
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 8
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#define STM32_PLLN_VALUE 360
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 7
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIR_VALUE 4
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#define STM32_PLLSAIP_VALUE 4
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#define STM32_PLLSAIQ_VALUE 4
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV4
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCPRE_VALUE 8
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
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#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
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#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
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#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
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#define STM32_CK48MSEL STM32_CK48MSEL_PLLALT
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/*
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* IRQ system settings.
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@ -91,20 +100,60 @@
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_TIM6_PRIORITY 7
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#define STM32_IRQ_TIM7_PRIORITY 7
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#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
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#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
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#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
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#define STM32_IRQ_TIM8_CC_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 12
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#define STM32_IRQ_USART2_PRIORITY 12
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#define STM32_IRQ_USART3_PRIORITY 12
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#define STM32_IRQ_UART4_PRIORITY 12
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#define STM32_IRQ_UART5_PRIORITY 12
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#define STM32_IRQ_USART6_PRIORITY 12
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#define STM32_IRQ_UART7_PRIORITY 12
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#define STM32_IRQ_UART8_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_USE_ADC2 FALSE
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#define STM32_ADC_USE_ADC3 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC2_DMA_PRIORITY 2
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 6
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_CAN1 FALSE
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#define STM32_CAN_USE_CAN2 FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY 11
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#define STM32_CAN_CAN2_IRQ_PRIORITY 11
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 FALSE
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#define STM32_DAC_USE_DAC1_CH2 FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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/*
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* GPT driver system settings.
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@ -114,9 +163,15 @@
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 FALSE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM8 FALSE
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#define STM32_GPT_USE_TIM9 FALSE
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#define STM32_GPT_USE_TIM10 FALSE
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#define STM32_GPT_USE_TIM11 FALSE
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#define STM32_GPT_USE_TIM12 FALSE
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#define STM32_GPT_USE_TIM13 FALSE
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#define STM32_GPT_USE_TIM14 FALSE
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/*
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* I2C driver system settings.
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@ -162,9 +217,24 @@
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_USE_TIM10 FALSE
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#define STM32_ICU_USE_TIM11 FALSE
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#define STM32_ICU_USE_TIM12 FALSE
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#define STM32_ICU_USE_TIM13 FALSE
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#define STM32_ICU_USE_TIM14 FALSE
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/*
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* MAC driver system settings.
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*/
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#define STM32_MAC_TRANSMIT_BUFFERS 2
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#define STM32_MAC_RECEIVE_BUFFERS 4
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#define STM32_MAC_BUFFERS_SIZE 1522
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#define STM32_MAC_PHY_TIMEOUT 100
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#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
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#define STM32_MAC_ETH1_IRQ_PRIORITY 13
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#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
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/*
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* PWM driver system settings.
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@ -174,15 +244,41 @@
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM5 FALSE
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#define STM32_PWM_USE_TIM8 FALSE
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#define STM32_PWM_USE_TIM9 FALSE
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#define STM32_PWM_USE_TIM10 FALSE
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#define STM32_PWM_USE_TIM11 FALSE
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#define STM32_PWM_USE_TIM12 FALSE
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#define STM32_PWM_USE_TIM13 FALSE
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#define STM32_PWM_USE_TIM14 FALSE
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/*
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* RTC driver system settings.
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*/
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#define STM32_RTC_PRESA_VALUE 32
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#define STM32_RTC_PRESS_VALUE 1024
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#define STM32_RTC_CR_INIT 0
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#define STM32_RTC_TAMPCR_INIT 0
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/*
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* SDC driver system settings.
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*/
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#define STM32_SDC_SDIO_DMA_PRIORITY 3
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#define STM32_SDC_SDIO_IRQ_PRIORITY 9
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#define STM32_SDC_WRITE_TIMEOUT_MS 1000
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#define STM32_SDC_READ_TIMEOUT_MS 1000
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#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
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#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
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#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 TRUE
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_SERIAL_USE_USART3 FALSE
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#define STM32_SERIAL_USE_UART4 FALSE
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#define STM32_SERIAL_USE_UART5 TRUE
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#define STM32_SERIAL_USE_USART6 FALSE
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/*
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@ -191,18 +287,33 @@
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#define STM32_SPI_USE_SPI1 TRUE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_USE_SPI4 FALSE
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#define STM32_SPI_USE_SPI5 FALSE
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#define STM32_SPI_USE_SPI6 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#define STM32_SPI_SPI5_DMA_PRIORITY 1
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#define STM32_SPI_SPI6_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_SPI4_IRQ_PRIORITY 10
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#define STM32_SPI_SPI5_IRQ_PRIORITY 10
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#define STM32_SPI_SPI6_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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@ -216,24 +327,47 @@
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USE_UART7 FALSE
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#define STM32_UART_USE_UART8 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_UART7_DMA_PRIORITY 0
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#define STM32_UART_UART8_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_OTG1 FALSE
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#define STM32_USB_USE_OTG2 FALSE
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#define STM32_USB_OTG1_IRQ_PRIORITY 14
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#define STM32_USB_OTG2_IRQ_PRIORITY 14
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#define STM32_USB_OTG1_RX_FIFO_SIZE 512
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#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
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#define STM32_USB_HOST_WAKEUP_DURATION 2
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/*
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@ -26,8 +26,8 @@
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/*
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* SPI TX and RX buffers.
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*/
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static uint8_t txbuf[32];
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static uint8_t rxbuf[32];
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static uint8_t txbuf[ADXL355_COMM_BUFF_SIZE];
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static uint8_t rxbuf[ADXL355_COMM_BUFF_SIZE];
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/* ADXL355 Driver: This object represent an ADXL355 instance */
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static ADXL355Driver ADXL355D1;
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@ -45,7 +45,7 @@ static const SPIConfig spicfg = {
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.data_cb = NULL,
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.error_cb = NULL,
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.ssline = LINE_ARD_D10,
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.cr1 = SPI_CR1_BR_1 | SPI_CR1_BR_0,
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.cr1 = SPI_CR1_BR_2,
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.cr2 = 0U
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};
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@ -65,7 +65,22 @@ static ADXL355Config adxl355cfg = {
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/* Generic code. */
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/*===========================================================================*/
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static BaseSequentialStream* chp = (BaseSequentialStream*)&SD2;
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static BaseSequentialStream* chp = (BaseSequentialStream*) &SD5;
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static THD_WORKING_AREA(waThreadBlinker, 128);
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static THD_FUNCTION(ThreadBlinker, arg) {
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(void)arg;
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chRegSetThreadName("blinker");
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while (true) {
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||||
palSetLine(LINE_LED_RED);
|
||||
chThdSleepMilliseconds(200);
|
||||
palClearLine(LINE_LED_RED);
|
||||
chThdSleepMilliseconds(200);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Application entry point.
|
||||
|
|
@ -82,13 +97,17 @@ int main(void) {
|
|||
halInit();
|
||||
chSysInit();
|
||||
|
||||
sdStart(&SD2, NULL);
|
||||
sdStart(&SD5, NULL);
|
||||
|
||||
palSetLineMode(LINE_ARD_D10, PAL_MODE_OUTPUT_PUSHPULL);
|
||||
palSetLineMode(LINE_ARD_D11, PAL_MODE_ALTERNATE(5) | PAL_STM32_OSPEED_HIGHEST);
|
||||
palSetLineMode(LINE_ARD_D12, PAL_MODE_ALTERNATE(5) | PAL_STM32_OSPEED_HIGHEST);
|
||||
palSetLineMode(LINE_ARD_D13, PAL_MODE_ALTERNATE(5) | PAL_STM32_OSPEED_HIGHEST);
|
||||
|
||||
/* Creating LED thread.*/
|
||||
chThdCreateStatic(waThreadBlinker, sizeof(waThreadBlinker), NORMALPRIO + 1,
|
||||
ThreadBlinker, NULL);
|
||||
|
||||
/* ADXL355 Object Initialization.*/
|
||||
adxl355ObjectInit(&ADXL355D1, txbuf, rxbuf);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
** TARGET **
|
||||
|
||||
The demo runs on an STM32 Nucleo64-F401RE board. It has been tested
|
||||
The demo runs on an ADI EVAL-SDP-CK1Z board. It has been tested
|
||||
connecting an external the EVAL-ADXL355.
|
||||
|
||||
** The Demo **
|
||||
|
|
@ -15,10 +15,10 @@ to acquire data from ADXL355 using ChibiOS/EX.
|
|||
** Board Setup **
|
||||
|
||||
With reference to the ADI UG-1030 (EVAL-ADXL354/EVAL-ADXL355 User Guide) and
|
||||
to the ST UM1724 (STM32 Nucleo64 board User Manual) the following connection
|
||||
to the Schematic of the SDP-K1) the following connection
|
||||
are need:
|
||||
---------------------------------------------
|
||||
| EVAL-ADXL355 | STM32 Nucleo64 |
|
||||
| EVAL-ADXL355 | SDP-K1 |
|
||||
|---------------------------------------------|
|
||||
| | |
|
||||
| P1.1 | ARD_IOREF |
|
||||
|
|
@ -27,8 +27,8 @@ are need:
|
|||
| | |
|
||||
| P2.2 | ARD_D10 |
|
||||
| P2.4 | ARD_D13 |
|
||||
| P2.5 | ARD_D11 |
|
||||
| P2.6 | ARD_D12 |
|
||||
| P2.5 | ARD_D12 |
|
||||
| P2.6 | ARD_D11 |
|
||||
---------------------------------------------
|
||||
** Build Procedure **
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue