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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15563 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2022-03-28 08:50:54 +00:00
parent 5641232c9e
commit 4adf9f490c
4 changed files with 6 additions and 6 deletions
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4
os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.h
View File

@ -288,9 +288,9 @@
/**
* @brief Device bus mode to be used.
* #note if @p MX25_SWITCH_WIDTH is @p FALSE then this is the bus mode
* @note if @p MX25_SWITCH_WIDTH is @p FALSE then this is the bus mode
* that the device is expected to be using.
* #note if @p MX25_SWITCH_WIDTH is @p TRUE then this is the bus mode
* @note if @p MX25_SWITCH_WIDTH is @p TRUE then this is the bus mode
* that the device will be switched in.
* @note This option is only valid in WSPI bus mode.
*/

4
os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.h
View File

@ -124,9 +124,9 @@
/**
* @brief Device bus mode to be used.
* #note if @p N25Q_SWITCH_WIDTH is @p FALSE then this is the bus mode
* @note if @p N25Q_SWITCH_WIDTH is @p FALSE then this is the bus mode
* that the device is expected to be using.
* #note if @p N25Q_SWITCH_WIDTH is @p TRUE then this is the bus mode
* @note if @p N25Q_SWITCH_WIDTH is @p TRUE then this is the bus mode
* that the device will be switched in.
* @note This option is only valid in WSPI bus mode.
*/

2
testhal/STM32/multi/WSPI-MFS/cfg/stm32h735ig_discovery/portab.c
View File

@ -39,7 +39,7 @@ const WSPIConfig WSPIcfg1 = {
.error_cb = NULL,
.dcr1 = STM32_DCR1_DLYBYP_MODE |
STM32_DCR1_MTYP(1U) | /* Macronix mode. */
STM32_DCR1_DEVSIZE(26U) | /* 64MB device. */
STM32_DCR1_DEVSIZE(25U) | /* 64MB device. */
STM32_DCR1_CSHT(1U), /* NCS 2 cycles delay. */
.dcr2 = 0U,
.dcr3 = 0U,

2
testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/portab.c
View File

@ -38,7 +38,7 @@ const WSPIConfig WSPIcfg1 = {
.end_cb = NULL,
.error_cb = NULL,
.dcr1 = STM32_DCR1_MTYP(1U) | /* Macronix mode. */
STM32_DCR1_DEVSIZE(26U) | /* 64MB device. */
STM32_DCR1_DEVSIZE(25U) | /* 64MB device. */
STM32_DCR1_CSHT(1U), /* NCS 2 cycles delay. */
.dcr2 = 0U,
.dcr3 = 0U,