+
+#include "ch.h"
+#include "hal.h"
+#include "ch_test.h"
+
+#include "chprintf.h"
+#include "shell.h"
+
+#include "lwipthread.h"
+#include "web/web.h"
+
+#include "ff.h"
+
+#include "usbcfg.h"
+
+/*===========================================================================*/
+/* Card insertion monitor. */
+/*===========================================================================*/
+
+#define POLLING_INTERVAL 10
+#define POLLING_DELAY 10
+
+/**
+ * @brief Card monitor timer.
+ */
+static virtual_timer_t tmr;
+
+/**
+ * @brief Debounce counter.
+ */
+static unsigned cnt;
+
+/**
+ * @brief Card event sources.
+ */
+static event_source_t inserted_event, removed_event;
+
+/**
+ * @brief Insertion monitor timer callback function.
+ *
+ * @param[in] p pointer to the @p BaseBlockDevice object
+ *
+ * @notapi
+ */
+static void tmrfunc(void *p) {
+ BaseBlockDevice *bbdp = p;
+
+ chSysLockFromISR();
+ if (cnt > 0) {
+ if (blkIsInserted(bbdp)) {
+ if (--cnt == 0) {
+ chEvtBroadcastI(&inserted_event);
+ }
+ }
+ else
+ cnt = POLLING_INTERVAL;
+ }
+ else {
+ if (!blkIsInserted(bbdp)) {
+ cnt = POLLING_INTERVAL;
+ chEvtBroadcastI(&removed_event);
+ }
+ }
+ chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, bbdp);
+ chSysUnlockFromISR();
+}
+
+/**
+ * @brief Polling monitor start.
+ *
+ * @param[in] p pointer to an object implementing @p BaseBlockDevice
+ *
+ * @notapi
+ */
+static void tmr_init(void *p) {
+
+ chEvtObjectInit(&inserted_event);
+ chEvtObjectInit(&removed_event);
+ chSysLock();
+ cnt = POLLING_INTERVAL;
+ chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, p);
+ chSysUnlock();
+}
+
+/*===========================================================================*/
+/* FatFs related. */
+/*===========================================================================*/
+
+/**
+ * @brief FS object.
+ */
+static FATFS SDC_FS;
+
+/* FS mounted and ready.*/
+static bool fs_ready = FALSE;
+
+/* Generic large buffer.*/
+static uint8_t fbuff[1024];
+
+static FRESULT scan_files(BaseSequentialStream *chp, char *path) {
+ FRESULT res;
+ FILINFO fno;
+ DIR dir;
+ int i;
+ char *fn;
+
+#if _USE_LFN
+ fno.lfname = 0;
+ fno.lfsize = 0;
+#endif
+ res = f_opendir(&dir, path);
+ if (res == FR_OK) {
+ i = strlen(path);
+ for (;;) {
+ res = f_readdir(&dir, &fno);
+ if (res != FR_OK || fno.fname[0] == 0)
+ break;
+ if (fno.fname[0] == '.')
+ continue;
+ fn = fno.fname;
+ if (fno.fattrib & AM_DIR) {
+ path[i++] = '/';
+ strcpy(&path[i], fn);
+ res = scan_files(chp, path);
+ if (res != FR_OK)
+ break;
+ path[--i] = 0;
+ }
+ else {
+ chprintf(chp, "%s/%s\r\n", path, fn);
+ }
+ }
+ }
+ return res;
+}
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
+
+static void cmd_tree(BaseSequentialStream *chp, int argc, char *argv[]) {
+ FRESULT err;
+ uint32_t clusters;
+ FATFS *fsp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: tree\r\n");
+ return;
+ }
+ if (!fs_ready) {
+ chprintf(chp, "File System not mounted\r\n");
+ return;
+ }
+ err = f_getfree("/", &clusters, &fsp);
+ if (err != FR_OK) {
+ chprintf(chp, "FS: f_getfree() failed\r\n");
+ return;
+ }
+ chprintf(chp,
+ "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n",
+ clusters, (uint32_t)SDC_FS.csize,
+ clusters * (uint32_t)SDC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE);
+ fbuff[0] = 0;
+ scan_files(chp, (char *)fbuff);
+}
+
+static const ShellCommand commands[] = {
+ {"tree", cmd_tree},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+ (BaseSequentialStream *)&SDU1,
+ commands
+};
+
+/*===========================================================================*/
+/* Main and generic code. */
+/*===========================================================================*/
+
+static thread_t *shelltp = NULL;
+
+/*
+ * Card insertion event.
+ */
+static void InsertHandler(eventid_t id) {
+ FRESULT err;
+
+ (void)id;
+ /*
+ * On insertion SDC initialization and FS mount.
+ */
+ if (sdcConnect(&SDCD1))
+ return;
+
+ err = f_mount(&SDC_FS, "/", 1);
+ if (err != FR_OK) {
+ sdcDisconnect(&SDCD1);
+ return;
+ }
+ fs_ready = TRUE;
+}
+
+/*
+ * Card removal event.
+ */
+static void RemoveHandler(eventid_t id) {
+
+ (void)id;
+ sdcDisconnect(&SDCD1);
+ fs_ready = FALSE;
+}
+
+/*
+ * Shell exit event.
+ */
+static void ShellHandler(eventid_t id) {
+
+ (void)id;
+ if (chThdTerminatedX(shelltp)) {
+ chThdWait(shelltp); /* Returning memory to heap. */
+ shelltp = NULL;
+ }
+}
+
+/*
+ * Green LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ palTogglePad(GPIOC, GPIOC_LED);
+ chThdSleepMilliseconds(fs_ready ? 125 : 500);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ static const evhandler_t evhndl[] = {
+ InsertHandler,
+ RemoveHandler,
+ ShellHandler
+ };
+ event_listener_t el0, el1, el2;
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ * - lwIP subsystem initialization using the default configuration.
+ */
+ halInit();
+ chSysInit();
+ lwipInit(NULL);
+
+ /*
+ * Initializes a serial-over-USB CDC driver.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ * Note, a delay is inserted in order to not have to disconnect the cable
+ * after a reset.
+ */
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(1500);
+ usbStart(serusbcfg.usbp, &usbcfg);
+ usbConnectBus(serusbcfg.usbp);
+
+ /*
+ * Shell manager initialization.
+ */
+ shellInit();
+
+ /*
+ * Activates the serial driver 6 and SDC driver 1 using default
+ * configuration.
+ */
+ sdStart(&SD6, NULL);
+ sdcStart(&SDCD1, NULL);
+
+ /*
+ * Activates the card insertion monitor.
+ */
+ tmr_init(&SDCD1);
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Creates the HTTP thread (it changes priority internally).
+ */
+ chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
+ http_server, NULL);
+
+ /*
+ * Normal main() thread activity, handling SD card events and shell
+ * start/exit.
+ */
+ chEvtRegister(&inserted_event, &el0, 0);
+ chEvtRegister(&removed_event, &el1, 1);
+ chEvtRegister(&shell_terminated, &el2, 2);
+ while (true) {
+ if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) {
+ shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE,
+ "shell", NORMALPRIO + 1,
+ shellThread, (void *)&shell_cfg1);
+ }
+ chEvtDispatch(evhndl, chEvtWaitOneTimeout(ALL_EVENTS, MS2ST(500)));
+ }
+}
diff --git a/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/mcuconf.h b/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/mcuconf.h
new file mode 100644
index 000000000..f95d3d6af
--- /dev/null
+++ b/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/mcuconf.h
@@ -0,0 +1,342 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 12
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+#define STM32_GPT_TIM12_IRQ_PRIORITY 7
+#define STM32_GPT_TIM14_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_USE_SPI3 FALSE
+#define STM32_I2S_SPI2_IRQ_PRIORITY 10
+#define STM32_I2S_SPI3_IRQ_PRIORITY 10
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI3_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY 3
+#define STM32_SDC_SDIO_IRQ_PRIORITY 9
+#define STM32_SDC_WRITE_TIMEOUT_MS 1000
+#define STM32_SDC_READ_TIMEOUT_MS 1000
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 TRUE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 TRUE
+#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+#endif /* MCUCONF_H */
diff --git a/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/readme.txt b/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/readme.txt
new file mode 100644
index 000000000..25d6c13f6
--- /dev/null
+++ b/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/readme.txt
@@ -0,0 +1,28 @@
+*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M3 STM32F107. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an Olimex STM32-P107 board.
+
+** The Demo **
+
+The demo currently just flashes a LED using a thread and serves HTTP requests
+at address 192.168.1.20 on port 80.
+The button activates che ChibiOS/RT test suite, output on SD3.
+
+** Build Procedure **
+
+The demo has been tested by using the free Codesourcery GCC-based toolchain
+and YAGARTO.
+Just modify the TRGT line in the makefile in order to use different GCC ports.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/web/web.c b/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/web/web.c
new file mode 100644
index 000000000..736589b3c
--- /dev/null
+++ b/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/web/web.c
@@ -0,0 +1,121 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file is a modified version of the lwIP web server demo. The original
+ * author is unknown because the file didn't contain any license information.
+ */
+
+/**
+ * @file web.c
+ * @brief HTTP server wrapper thread code.
+ * @addtogroup WEB_THREAD
+ * @{
+ */
+
+#include "ch.h"
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/api.h"
+
+#include "web.h"
+
+#if LWIP_NETCONN
+
+static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
+static const char http_index_html[] = "Congrats!Welcome to our lwIP HTTP server!
This is a small test page.";
+
+static void http_server_serve(struct netconn *conn) {
+ struct netbuf *inbuf;
+ char *buf;
+ u16_t buflen;
+ err_t err;
+
+ /* Read the data from the port, blocking if nothing yet there.
+ We assume the request (the part we care about) is in one netbuf */
+ err = netconn_recv(conn, &inbuf);
+
+ if (err == ERR_OK) {
+ netbuf_data(inbuf, (void **)&buf, &buflen);
+
+ /* Is this an HTTP GET command? (only check the first 5 chars, since
+ there are other formats for GET, and we're keeping it very simple )*/
+ if (buflen>=5 &&
+ buf[0]=='G' &&
+ buf[1]=='E' &&
+ buf[2]=='T' &&
+ buf[3]==' ' &&
+ buf[4]=='/' ) {
+
+ /* Send the HTML header
+ * subtract 1 from the size, since we dont send the \0 in the string
+ * NETCONN_NOCOPY: our data is const static, so no need to copy it
+ */
+ netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
+
+ /* Send our HTML page */
+ netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
+ }
+ }
+ /* Close the connection (server closes in HTTP) */
+ netconn_close(conn);
+
+ /* Delete the buffer (netconn_recv gives us ownership,
+ so we have to make sure to deallocate the buffer) */
+ netbuf_delete(inbuf);
+}
+
+/**
+ * Stack area for the http thread.
+ */
+THD_WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
+
+/**
+ * HTTP server thread.
+ */
+THD_FUNCTION(http_server, p) {
+ struct netconn *conn, *newconn;
+ err_t err;
+
+ (void)p;
+ chRegSetThreadName("http");
+
+ /* Create a new TCP connection handle */
+ conn = netconn_new(NETCONN_TCP);
+ LWIP_ERROR("http_server: invalid conn", (conn != NULL), chThdExit(MSG_RESET););
+
+ /* Bind to port 80 (HTTP) with default IP address */
+ netconn_bind(conn, NULL, WEB_THREAD_PORT);
+
+ /* Put the connection into LISTEN state */
+ netconn_listen(conn);
+
+ /* Goes to the final priority after initialization.*/
+ chThdSetPriority(WEB_THREAD_PRIORITY);
+
+ while (true) {
+ err = netconn_accept(conn, &newconn);
+ if (err != ERR_OK)
+ continue;
+ http_server_serve(newconn);
+ netconn_delete(newconn);
+ }
+}
+
+#endif /* LWIP_NETCONN */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/web/web.h b/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/web/web.h
new file mode 100644
index 000000000..e1d48379a
--- /dev/null
+++ b/demos/STM32/RT-STM32F107-OLIMEX_P107-LWIP/web/web.h
@@ -0,0 +1,51 @@
+/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file web.h
+ * @brief HTTP server wrapper thread macros and structures.
+ * @addtogroup WEB_THREAD
+ * @{
+ */
+
+#ifndef WEB_H
+#define WEB_H
+
+#ifndef WEB_THREAD_STACK_SIZE
+#define WEB_THREAD_STACK_SIZE 1024
+#endif
+
+#ifndef WEB_THREAD_PORT
+#define WEB_THREAD_PORT 80
+#endif
+
+#ifndef WEB_THREAD_PRIORITY
+#define WEB_THREAD_PRIORITY (LOWPRIO + 2)
+#endif
+
+extern THD_WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ THD_FUNCTION(http_server, p);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* WEB_H */
+
+/** @} */