git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6601 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
2f7a9a8a03
commit
4b2705efbf
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@ -66,7 +66,7 @@
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/* If the device type is not externally defined, for example from the Makefile,
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then a file named board.h is included. This file must contain a device
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definition compatible with the vendor include file.*/
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#if !defined(STM32F0XX_LD) && !defined(STM32F0XX_MD)
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#if !defined(STM32F0030) && !defined(STM32F0XX_LD) && !defined(STM32F0XX_MD)
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#include "board.h"
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#endif
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f0xx.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 31-July-2013
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* @version V1.2.1
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* @date 22-November-2013
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F0xx devices.
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@ -65,22 +65,26 @@
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application
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*/
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#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD)
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/* #define STM32F0XX_LD*/ /*!< STM32F0xx Low-density devices are STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes */
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/* #define STM32F0XX_MD*/ /*!< STM32F0xx Medium-density devices are STM32F051xx and STM32F061xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes */
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#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD) && !defined (STM32F030)
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/* #define STM32F0XX_LD */ /*!< STM32F0xx Low-density devices are STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes */
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/* #define STM32F0XX_MD */ /*!< STM32F0xx Medium-density devices are STM32F051xx and STM32F061xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes */
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#define STM32F030 /*!< STM32F030 devices are STM32F030xx value line microcontrollers */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#ifdef STM32F0XX_MD
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#ifndef STM32F0XX
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/* Old STM32F0XX definition, maintained for legacy purpose */
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#define STM32F0XX STM32F0XX_MD
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#endif /* STM32F0XX */
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#endif /* STM32F0XX_MD */
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/* Old STM32F0XX definition, maintained for legacy purpose */
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#if defined(STM32F0XX)
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#define STM32F0XX_MD
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#endif /* STM32F0XX */
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#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD)
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/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
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#if defined (STM32F030X8) || defined (STM32F030X6)
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#define STM32F030
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#endif /* STM32F030X8 or STM32F030X6 */
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#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD) && !defined (STM32F030)
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#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
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#endif
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@ -143,10 +147,10 @@
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#endif /* LSE_VALUE */
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/**
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* @brief STM32F0xx Standard Peripheral Library version number V1.1.1
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* @brief STM32F0xx Standard Peripheral Library version number V1.2.1
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*/
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#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
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#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
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#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
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#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
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@ -180,9 +184,8 @@ typedef enum IRQn
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SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
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#ifdef STM32F0XX_MD
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/****** STM32F0XX_MD specific Interrupt Numbers *****************************************************/
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#if defined (STM32F0XX_MD)
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/****** STM32F0XX_MD specific Interrupt Numbers ****************************************************/
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WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
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RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
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@ -191,7 +194,7 @@ typedef enum IRQn
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EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
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EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
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EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
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TS_IRQn = 8, /*!< TS Interrupt */
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TS_IRQn = 8, /*!< Touch sense controller Interrupt */
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DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
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DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
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DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
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@ -235,7 +238,33 @@ typedef enum IRQn
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TIM17_IRQn = 22, /*!< TIM17 Interrupt */
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I2C1_IRQn = 23, /*!< I2C1 Interrupt */
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SPI1_IRQn = 25, /*!< SPI1 Interrupt */
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USART1_IRQn = 27 /*!< USART1 Interrupt */
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#elif defined (STM32F030)
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/****** STM32F030 specific Interrupt Numbers ********************************************************/
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WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
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FLASH_IRQn = 3, /*!< FLASH Interrupt */
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RCC_IRQn = 4, /*!< RCC Interrupt */
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EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
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EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
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EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
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DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
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DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
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DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
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ADC1_IRQn = 12, /*!< ADC1 Interrupt */
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TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
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TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
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TIM3_IRQn = 16, /*!< TIM3 Interrupt */
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TIM14_IRQn = 19, /*!< TIM14 Interrupt */
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TIM15_IRQn = 20, /*!< TIM15 Interrupt */
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TIM16_IRQn = 21, /*!< TIM16 Interrupt */
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TIM17_IRQn = 22, /*!< TIM17 Interrupt */
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I2C1_IRQn = 23, /*!< I2C1 Interrupt */
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I2C2_IRQn = 24, /*!< I2C2 Interrupt */
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SPI1_IRQn = 25, /*!< SPI1 Interrupt */
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SPI2_IRQn = 26, /*!< SPI2 Interrupt */
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USART1_IRQn = 27, /*!< USART1 Interrupt */
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USART2_IRQn = 28 /*!< USART2 Interrupt */
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#endif /* STM32F0XX_MD */
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} IRQn_Type;
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@ -2032,17 +2061,17 @@ typedef struct
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#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
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#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
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#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (only for STM32F0XX_LD devices)*/
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#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
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#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (only for STM32F0XX_LD devices) */
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#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (only for STM32F0XX_LD and STM32FO30X6 devices) */
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/*!<****************** Bit definition for RCC_CIR register ********************/
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#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
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@ -2587,9 +2616,9 @@ typedef struct
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#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
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#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
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#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
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#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0XX_LD devices) */
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#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F0XX_LD devices) */
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#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F0XX_LD devices) */
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#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0XX_LD and STM32FO30X6 devices) */
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#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F0XX_LD and STM32FO30X6 devices) */
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#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F0XX_LD and STM32FO30X6 devices) */
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/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
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#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file system_stm32f0xx.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 31-July-2013
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* @version V1.2.1
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* @date 22-November-2013
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
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******************************************************************************
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* @attention
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@ -45,7 +45,7 @@
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#define STM32_HSE_BYPASS
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/*
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* MCU type as defined in the ST header file stm32f0xx.h.
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* MCU type as defined in the ST header.
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*/
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#define STM32F0XX_MD
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@ -10,6 +10,7 @@
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<board_name>ST STM32F0-Discovery</board_name>
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<board_id>ST_STM32F0_DISCOVERY</board_id>
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<board_functions></board_functions>
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<subtype>STM32F0XX_MD</subtype>
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<clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
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LSEBypass="false" LSEDrive="3 High Drive (default)" />
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<ports>
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@ -35,21 +35,29 @@
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
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#define AHB_LPEN_MASK AHB_EN_MASK
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#elif defined(STM32F0XX_LD) || defined(STM32F0XX_MD)
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#elif defined(STM32F030) || defined(STM32F0XX_MD)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F0XX_LD)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F2XX)
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#elif defined(STM32F30X) || defined(STM32F37X)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F4XX)
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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@ -57,6 +65,7 @@
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#else
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#error "missing or unsupported platform for GPIOv2 PAL driver"
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#endif
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@ -120,10 +129,18 @@ void _pal_lld_init(const PALConfig *config) {
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/*
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* Initial GPIO setup.
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*/
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#if STM32_HAS_GPIOA
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initgpio(GPIOA, &config->PAData);
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#endif
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#if STM32_HAS_GPIOB
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initgpio(GPIOB, &config->PBData);
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#endif
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#if STM32_HAS_GPIOC
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initgpio(GPIOC, &config->PCData);
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#endif
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#if STM32_HAS_GPIOD
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initgpio(GPIOD, &config->PDData);
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#endif
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#if STM32_HAS_GPIOE
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initgpio(GPIOE, &config->PEData);
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#endif
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@ -215,31 +215,39 @@ typedef struct {
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* or whole ports can be reprogrammed at later time.
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*/
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typedef struct {
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#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
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/** @brief Port A setup data.*/
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stm32_gpio_setup_t PAData;
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#endif
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#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
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/** @brief Port B setup data.*/
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stm32_gpio_setup_t PBData;
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#endif
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#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
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/** @brief Port C setup data.*/
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stm32_gpio_setup_t PCData;
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#endif
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#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
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/** @brief Port D setup data.*/
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stm32_gpio_setup_t PDData;
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#if STM32_HAS_GPIOE
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#endif
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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/** @brief Port E setup data.*/
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stm32_gpio_setup_t PEData;
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#endif
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#if STM32_HAS_GPIOF
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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/** @brief Port F setup data.*/
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stm32_gpio_setup_t PFData;
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#endif
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#if STM32_HAS_GPIOG
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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/** @brief Port G setup data.*/
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stm32_gpio_setup_t PGData;
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#endif
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#if STM32_HAS_GPIOH
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#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
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/** @brief Port H setup data.*/
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stm32_gpio_setup_t PHData;
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#endif
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#if STM32_HAS_GPIOI
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#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
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/** @brief Port I setup data.*/
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stm32_gpio_setup_t PIData;
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#endif
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@ -26,8 +26,9 @@
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* - STM32_HSE_BYPASS (optionally).
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* .
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* One of the following macros must also be defined:
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* - STM32F0XX_LD for Low Density Entry Level devices.
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* - STM32F0XX_MD for Medium Density Entry Level devices.
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* - STM32F030 for Value Line devices.
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* - STM32F0XX_LD for Low Density devices.
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* - STM32F0XX_MD for Medium Density devices.
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* .
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*
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* @addtogroup HAL
|
||||
|
|
@ -44,10 +45,24 @@
|
|||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @name Platform identification macros
|
||||
* @{
|
||||
*/
|
||||
#define PLATFORM_NAME "STM32F05x Entry Level"
|
||||
#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
|
||||
#define PLATFORM_NAME "STM32F051xx/F061xx Entry Level Medium Density devices"
|
||||
#define STM32F0XX
|
||||
|
||||
#elif defined(STM32F0XX_LD)
|
||||
#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Low Density devices"
|
||||
#define STM32F0XX
|
||||
|
||||
#elif defined(STM32F030)
|
||||
#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Value Line devices"
|
||||
#define STM32F0XX
|
||||
|
||||
#else
|
||||
#error "STM32F0xx device not specified"
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@
|
|||
* @name STM32F0xx capabilities
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
|
|
@ -164,6 +166,259 @@
|
|||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
#elif defined(STM32F0XX_LD)
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 FALSE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC FALSE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 28
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD FALSE
|
||||
#define STM32_HAS_GPIOE FALSE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS FALSE
|
||||
#define STM32_RTC_IS_CALENDAR TRUE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
|
||||
#define STM32_HAS_SPI2 FALSE
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM14 TRUE
|
||||
#define STM32_TIM14_IS_32BITS FALSE
|
||||
#define STM32_TIM14_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
|
||||
#define STM32_HAS_USART2 FALSE
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
#else /* STM32F030 */
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 FALSE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC FALSE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 28
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE FALSE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS FALSE
|
||||
#define STM32_RTC_IS_CALENDAR TRUE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM14 TRUE
|
||||
#define STM32_TIM14_IS_32BITS FALSE
|
||||
#define STM32_TIM14_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_TIM15_IS_32BITS FALSE
|
||||
#define STM32_TIM15_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM2 FALSE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
#endif /* STM32F030 */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* _STM32_REGISTRY_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue