From 4b7aa7e476a66a465b8791ac1b114a6dbaae8f31 Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Thu, 26 May 2016 11:08:28 +0000 Subject: [PATCH] Fixed Bug #746 git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_16.1.x@9530 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F4xx/hal_lld.h | 16 +++++++------- os/hal/ports/STM32/STM32F7xx/hal_lld.h | 30 +++++++++++++------------- readme.txt | 2 ++ 3 files changed, 25 insertions(+), 23 deletions(-) diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index 4383e4855..79b80bc04 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -633,32 +633,32 @@ #endif /** - * @brief MC01 clock source value. - * @note The default value outputs HSI clock on MC01 pin. + * @brief MCO1 clock source value. + * @note The default value outputs HSI clock on MCO1 pin. */ #if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) #define STM32_MCO1SEL STM32_MCO1SEL_HSI #endif /** - * @brief MC01 prescaler value. - * @note The default value outputs HSI clock on MC01 pin. + * @brief MCO1 prescaler value. + * @note The default value outputs HSI clock on MCO1 pin. */ #if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #endif /** - * @brief MC02 clock source value. - * @note The default value outputs SYSCLK / 5 on MC02 pin. + * @brief MCO2 clock source value. + * @note The default value outputs SYSCLK / 5 on MCO2 pin. */ #if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #endif /** - * @brief MC02 prescaler value. - * @note The default value outputs SYSCLK / 5 on MC02 pin. + * @brief MCO2 prescaler value. + * @note The default value outputs SYSCLK / 5 on MCO2 pin. */ #if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index b850f51d4..cb6ff3a2a 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -194,11 +194,11 @@ * @name RCC_PLLCFGR register bits definitions * @{ */ -#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ -#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ -#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ -#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ -#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ +#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ +#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ +#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ +#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ +#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ #define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ @@ -224,14 +224,14 @@ #define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ #define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ -#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ +#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ #define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ #define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ #define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ #define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ #define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ -#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ +#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ #define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ #define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ #define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ @@ -582,32 +582,32 @@ #endif /** - * @brief MC01 clock source value. - * @note The default value outputs HSI clock on MC01 pin. + * @brief MCO1 clock source value. + * @note The default value outputs HSI clock on MCO1 pin. */ #if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) #define STM32_MCO1SEL STM32_MCO1SEL_HSI #endif /** - * @brief MC01 prescaler value. - * @note The default value outputs HSI clock on MC01 pin. + * @brief MCO1 prescaler value. + * @note The default value outputs HSI clock on MCO1 pin. */ #if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #endif /** - * @brief MC02 clock source value. - * @note The default value outputs SYSCLK / 4 on MC02 pin. + * @brief MCO2 clock source value. + * @note The default value outputs SYSCLK / 4 on MCO2 pin. */ #if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #endif /** - * @brief MC02 prescaler value. - * @note The default value outputs SYSCLK / 4 on MC02 pin. + * @brief MCO2 prescaler value. + * @note The default value outputs SYSCLK / 4 on MCO2 pin. */ #if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 diff --git a/readme.txt b/readme.txt index 2611efb00..6d30d1b01 100644 --- a/readme.txt +++ b/readme.txt @@ -73,6 +73,8 @@ ***************************************************************************** *** 16.1.5 *** +- HAL: Fixed wrong comments and indent in STM32F4xx and STM32F7xx + hal_lld.h (bug #746). - HAL: Removed wrong SAI masks in STM32F4xx hal_lld.h (bug #745). - HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744). - HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).