git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1820 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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77ae91f021
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4bc04c7835
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@ -600,8 +600,10 @@ INPUT = ../docs/src \
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../os/ports/GCC/ARM7 \
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../os/ports/GCC/ARM7/crt0.s \
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../os/ports/GCC/ARM7/chcoreasm.s \
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../os/ports/GCC/ARMCMx \
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../os/ports/GCC/ARMCMx/crt0.s \
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../os/ports/GCC/ARMCMx/STM32F10x \
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../os/ports/GCC/ARMCM3 \
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../os/ports/GCC/ARMCM3/crt0.s \
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../os/ports/GCC/ARMCM3\STM32F103 \
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../os/ports/GCC/PPC \
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../os/ports/GCC/PPC/crt0.s \
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@ -158,7 +158,6 @@
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* - @p _bss_end BSS end location +1.
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* .
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* @ingroup ARMCM3
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* @file ARMCM3/crt0.s Startup code.
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*/
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/**
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@ -19,7 +19,7 @@
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/**
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* @file ARMCMx/chcore.c
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* @brief ARM Cortex-Mx architecture port code.
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* @brief ARM Cortex-Mx port code.
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*
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* @addtogroup ARMCMx_CORE
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* @{
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@ -165,14 +165,21 @@ void _port_switch_from_irq(void) {
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__attribute__((naked))
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#endif
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void port_switch(Thread *ntp, Thread *otp) {
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register struct intctx *sp_thd asm ("sp");
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register struct intctx *r13 asm ("r13");
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PUSH_CONTEXT(sp_thd);
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/* Stack overflow check, if enabled.*/
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#if CH_DBG_ENABLE_STACK_CHECK
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if ((void *)(r13 - 1) < (void *)(otp + 1))
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asm volatile ("movs r0, #0 \n\t"
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"b chDbgPanic");
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#endif /* CH_DBG_ENABLE_STACK_CHECK */
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otp->p_ctx.r13 = sp_thd;
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sp_thd = ntp->p_ctx.r13;
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PUSH_CONTEXT(r13);
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POP_CONTEXT(sp_thd);
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otp->p_ctx.r13 = r13;
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r13 = ntp->p_ctx.r13;
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POP_CONTEXT(r13);
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}
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/**
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@ -182,9 +189,9 @@ void port_switch(Thread *ntp, Thread *otp) {
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*/
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void _port_thread_start(void) {
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asm volatile ("cpsie i \n\t" \
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"mov r0, r5 \n\t" \
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"blx r4 \n\t" \
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asm volatile ("cpsie i \n\t" \
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"mov r0, r5 \n\t" \
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"blx r4 \n\t" \
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"bl chThdExit");
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}
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@ -19,7 +19,7 @@
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/**
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* @file ARMCMx/chcore.h
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* @brief ARM Cortex-Mx architecture port macros and structures.
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* @brief ARM Cortex-Mx port macros and structures.
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*
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* @addtogroup ARMCMx_CORE
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* @{
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@ -49,14 +49,16 @@
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/* Inclusion of the Cortex-Mx implementation specific parameters.*/
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#include "cmparams.h"
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/* Cortex model check, only M0 and M3 right now.*/
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/* Cortex model check, only M0 and M3 supported right now.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3)
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#elif (CORTEX_MODEL == CORTEX_M1) || (CORTEX_MODEL == CORTEX_M4)
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#warning "untested Cortex-M model"
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#else
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#error "unknown or unsupported Cortex-M model"
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#endif
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/*===========================================================================*/
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/* Port derived parameters. */
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/* Port statically derived parameters. */
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/*===========================================================================*/
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/**
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@ -114,8 +116,8 @@
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/**
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* @brief SYSTICK handler priority.
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* @note The default is calculated as the priority level in the middle
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* of the priority range.
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* @note The default priority is calculated as the priority level in
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* the middle of the numeric priorities range.
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*/
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#ifndef CORTEX_PRIORITY_SYSTICK
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#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
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@ -126,13 +128,67 @@
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#endif
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#endif
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/**
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* @brief Priority masking support.
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* @details The ARMv7-M architecture is capable to mask only interrupt
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* priorities below or equal to a certain specified priority
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* mask. If this option is enabled all the priorities above
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* @p CORTEX_BASEPRI_KERNEL (lower numeric values) are not
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* affected by the kernel locks and can operate with minimum
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* latency.<br>
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* This option makes the kernel code a bit larger and slower, if
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* your application does not need fast interrups it is recommended
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* to keep this option disabled.
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*/
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#if CORTEX_SUPPORTS_BASEPRI || defined(__DOXYGEN__)
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#if !defined(CORTEX_USE_BASEPRI) || defined(__DOXYGEN__)
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#define CORTEX_USE_BASEPRI FALSE
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#endif /* !defined(CORTEX_USE_BASEPRI) */
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#else /* !CORTEX_SUPPORTS_BASEPRI */
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#if defined(CORTEX_USE_BASEPRI) && CORTEX_USE_BASEPRI
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#error "BASEPRI priority masking register not supported in this architecture"
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#endif
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#define CORTEX_USE_BASEPRI FALSE
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#endif /* !CORTEX_SUPPORTS_BASEPRI */
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#if CORTEX_USE_BASEPRI || defined(__DOXYGEN__)
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/**
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* @brief BASEPRI user level.
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* @note This constant is defined only if the @p CORTEX_USE_BASEPRI port
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* option is enabled.
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*/
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#ifndef CORTEX_BASEPRI_USER
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#define CORTEX_BASEPRI_USER CORTEX_PRIORITY_MASK(0)
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#endif
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/**
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* @brief BASEPRI level within kernel lock.
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* @details Priority levels higher than this one (lower numeric values) are
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* unaffected by kernel locks and can be classified as fast
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* interrupt sources, see @ref interrupt_classes.
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* @note This constant is defined only if the @p CORTEX_USE_BASEPRI port
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* option is enabled.
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* @note The default setting reserves just the highest priority level
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* (@p CORTEX_MAXIMUM_PRIORITY) for fast interrupts, you may redefine
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* this setting in order to reserve more levels.
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*/
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#ifndef CORTEX_BASEPRI_KERNEL
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#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAXIMUM_PRIORITY+1)
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#endif
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#endif /* CORTEX_USE_BASEPRI */
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/*===========================================================================*/
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/* Port exported info. */
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/*===========================================================================*/
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/**
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* @brief Macro defining a generic ARM architecture.
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*/
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#define CH_ARCHITECTURE_ARM
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#if defined(__DOXYGEN__)
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/**
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* @brief Macro defining the ARM architecture.
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* @brief Macro defining the specific ARM architecture.
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*/
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#define CH_ARCHITECTURE_ARM_vxm
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@ -147,7 +203,7 @@
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#define CH_CORE_VARIANT_NAME "Cortex-Mx"
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#elif CORTEX_MODEL == CORTEX_M4
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#define CH_ARCHITECTURE_ARM_v7M
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#define CH_ARCHITECTURE_NAME "ARMv7-M"
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#define CH_ARCHITECTURE_NAME "ARMv7-ME"
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#define CH_CORE_VARIANT_NAME "Cortex-M4"
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#elif CORTEX_MODEL == CORTEX_M3
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#define CH_ARCHITECTURE_ARM_v7M
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@ -364,17 +420,29 @@ struct context {
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* @brief Kernel-lock action.
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* @details Usually this function just disables interrupts but may perform
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* more actions.
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* @note In this port it disables all the interrupt sources.
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*/
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#if CORTEX_USE_BASEPRI
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#define port_lock() { \
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register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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}
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#else /* !CORTEX_USE_BASEPRI */
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#define port_lock() asm volatile ("cpsid i")
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#endif /* !CORTEX_USE_BASEPRI */
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/**
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* @brief Kernel-unlock action.
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* @details Usually this function just disables interrupts but may perform
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* more actions.
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* @note In this port it enables all the interrupt sources.
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*/
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#if CORTEX_USE_BASEPRI
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#define port_unlock() { \
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register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
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asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
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}
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#else /* !CORTEX_USE_BASEPRI */
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#define port_unlock() asm volatile ("cpsie i")
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#endif /* !CORTEX_USE_BASEPRI */
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/**
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* @brief Kernel-lock action from an interrupt handler.
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@ -390,29 +458,40 @@ struct context {
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* @details This function is invoked after invoking I-class APIs from interrupt
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* handlers. The implementation is architecture dependent, in its
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* simplest form it is void.
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* @note Same as @p port_unlock() in this port.
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* @note Same as @p port_lock() in this port.
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*/
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#define port_unlock_from_isr() port_unlock()
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/**
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* @brief Disables all the interrupt sources.
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* @note Of course non maskable interrupt sources are not included.
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* @note In this port it disables all the interrupt sources.
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*/
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#define port_disable() asm volatile ("cpsid i")
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/**
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* @brief Disables the interrupt sources below kernel-level priority.
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* @note Interrupt sources above kernel level remains enabled.
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* @note In this port it disables all the interrupt sources.
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*/
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#if CORTEX_USE_BASEPRI
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#define port_suspend() { \
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register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
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asm volatile ("msr BASEPRI, %0 \n\t" \
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"cpsie i" : : "r" (tmp)); \
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}
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#else /* !CORTEX_USE_BASEPRI */
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#define port_suspend() asm volatile ("cpsid i")
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#endif /* !CORTEX_USE_BASEPRI */
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/**
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* @brief Enables all the interrupt sources.
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* @note In this port it enables all the interrupt sources.
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*/
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#if CORTEX_USE_BASEPRI
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#define port_enable() { \
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register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
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asm volatile ("msr BASEPRI, %0 \n\t" \
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"cpsie i" : : "r" (tmp)); \
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}
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#else /* !CORTEX_USE_BASEPRI */
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#define port_enable() asm volatile ("cpsie i")
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#endif /* !CORTEX_USE_BASEPRI */
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/**
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* @brief Enters an architecture-dependent IRQ-waiting mode.
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@ -18,8 +18,9 @@
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*/
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/**
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* @file ARMCMx/chtypes.h
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* @brief ARM Cortex-M3 architecture port system types.
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* @file ARMCMx/chtypes.h
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* @brief ARM Cortex-Mx port system types.
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*
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* @addtogroup ARMCMx_CORE
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* @{
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*/
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@ -32,9 +33,7 @@
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#define __need_ptrdiff_t
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#include <stddef.h>
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#if !defined(_STDINT_H) && !defined(__STDINT_H_)
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#include <stdint.h>
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#endif
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typedef int32_t bool_t; /**< Fast boolean type. */
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typedef uint8_t tmode_t; /**< Thread flags. */
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@ -73,7 +73,7 @@ ResetHandler:
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ldr r3, =_edata
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dloop:
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cmp r2, r3
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#if CORTEX_MODEL == CORTEX_M0
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
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bge enddloop
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ldr r0, [r1]
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str r0, [r2]
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@ -96,7 +96,7 @@ enddloop:
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ldr r2, =_bss_end
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bloop:
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cmp r1, r2
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#if CORTEX_MODEL == CORTEX_M0
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
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bge endbloop
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str r0, [r1]
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adds r1, r1, #4
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|
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@ -18,8 +18,9 @@
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*/
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/**
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* @file ARMCMx/nvic.c
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* @brief Cortex-Mx NVIC support code.
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* @file ARMCMx/nvic.c
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* @brief Cortex-Mx NVIC support code.
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*
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* @addtogroup ARMCMx_NVIC
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* @{
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*/
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@ -31,7 +32,7 @@
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* @brief Sets the priority of an interrupt handler and enables it.
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*
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* @param n the interrupt number
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* @param prio the interrupt priority
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* @param prio the interrupt priority mask
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*
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* @note The parameters are not tested for correctness.
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*/
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@ -61,13 +62,14 @@ void NVICDisableVector(uint32_t n) {
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* @brief Changes the priority of a system handler.
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*
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* @param handler the system handler number
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* @param prio the system handler priority
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* @param prio the system handler priority mask
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* @note The parameters are not tested for correctness.
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*/
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void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) {
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unsigned sh = (handler & 3) * 8;
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SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & ~(0xFF << sh)) | (prio << sh);
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SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) &
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~(0xFF << sh)) | (prio << sh);
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}
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/** @} */
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|
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@ -18,8 +18,9 @@
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*/
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/**
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* @file ARMCMx/nvic.h
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* @brief Cortex-Mx NVIC support macros and structures.
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* @file ARMCMx/nvic.h
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* @brief Cortex-Mx NVIC support macros and structures.
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*
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* @addtogroup ARMCMx_NVIC
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* @{
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*/
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@ -30,21 +31,21 @@
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/*
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* System vector constants for @p NVICSetSystemHandlerPriority().
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*/
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#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id.*/
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#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id.*/
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#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id.*/
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#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */
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#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */
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#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */
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#define HANDLER_RESERVED_3 3
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#define HANDLER_RESERVED_4 4
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#define HANDLER_RESERVED_5 5
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#define HANDLER_RESERVED_6 6
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#define HANDLER_SVCALL 7 /**< SVCALL vector id.*/
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#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id.*/
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#define HANDLER_SVCALL 7 /**< SVCALL vector id. */
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#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */
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#define HANDLER_RESERVED_9 9
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#define HANDLER_PENDSV 10 /**< PENDSV vector id.*/
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#define HANDLER_SYSTICK 11 /**< SYS TCK vector id.*/
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#define HANDLER_PENDSV 10 /**< PENDSV vector id. */
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#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */
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typedef volatile unsigned char IOREG8; /**< 8 bits I/O register type.*/
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typedef volatile unsigned int IOREG32; /**< 32 bits I/O register type.*/
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typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */
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typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
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/**
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* @brief NVIC ITCR register.
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|
|
|
@ -19,17 +19,65 @@
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|
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/**
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* @defgroup ARMCMx ARM Cortex-Mx
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* @details This port supports the ARM Cortex-Mx architectures, specifically
|
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* the Cortex-M0 and the Cortex-M3.
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* @details This port supports the ARMv6-M and ARMv7-M architectures (all the
|
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* Cortex-Mx cores).
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*
|
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* @section ARMCMx_STATES Mapping of the System States in the ARM Cortex-Mx port
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
|
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* Cortex-Mx port:
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* This port supports two IRQ handling modes:
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* - <b>IRQ disabling</b>. This is the simplest and most efficient way to
|
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* implement kernel locks, this is done by globally disabling interrupts.
|
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* This mode is available to both the ARMv6-M and ARMv7-M architectures.
|
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* - <b>IRQ priority masking</b>. In this mode kernel locks are implemented by
|
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* raising the priority mask to the @p CORTEX_BASEPRI_KERNEL level. Using
|
||||
* priority masking it is possible to reserve one or more priority levels
|
||||
* for use as fast interrupt handlers. This mode is slightly less efficient
|
||||
* because the lock/unlock code requires two instructions instead of just
|
||||
* one and is available to the ARMv7-M architecture only (Cortex-M3 and
|
||||
* Cortex-M4). The advantage in this mode is the availability of very low
|
||||
* latency priority levels unaffected by the RTOS activity.
|
||||
* .
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||||
* The mapping of the @ref system_states changes depending on the chosen IRQ
|
||||
* handling mode.
|
||||
*
|
||||
* @subsection ARMCMx_STATES_A System logical states in IRQ disabling mode
|
||||
* - <b>Init</b>. This state is represented by the startup code and the
|
||||
* initialization code before @p chSysInit() is executed. It has not a
|
||||
* special hardware state associated.
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||||
* - <b>Normal</b>. This is the state the system has after executing
|
||||
* @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
|
||||
* @p chSysInit(). In this state interrupts are enabled. The processor
|
||||
* is running in thread-privileged mode.
|
||||
* - <b>Suspended</b>. In this state the interrupt sources are globally
|
||||
* disabled. The processor is running in thread-privileged mode. In this
|
||||
* mode this state is not different from the <b>Disabled</b> state.
|
||||
* - <b>Disabled</b>. In this state the interrupt sources are globally
|
||||
* disabled. The processor is running in thread-privileged mode. In this
|
||||
* mode this state is not different from the <b>Suspended</b> state.
|
||||
* - <b>Sleep</b>. This state is entered with the execution of the specific
|
||||
* instruction @p <b>wfi</b>.
|
||||
* - <b>S-Locked</b>. In this state the interrupt sources are globally
|
||||
* disabled. The processor is running in thread-privileged mode.
|
||||
* - <b>I-Locked</b>. In this state the interrupt sources are globally
|
||||
* disabled. The processor is running in exception-privileged mode.
|
||||
* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
|
||||
* not globally masked but only interrupts with higher priority can preempt
|
||||
* the current handler. The processor is running in exception-privileged
|
||||
* mode.
|
||||
* - <b>Serving Fast Interrupt</b>. This state is not implemented in this mode.
|
||||
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
|
||||
* asynchronous NMI vector and several synchronous fault vectors that can
|
||||
* be considered belonging to this category.
|
||||
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
|
||||
* the maskable interrupt sources. The ARM state is whatever the processor
|
||||
* was running when @p chSysHalt() was invoked.
|
||||
*
|
||||
* @subsection ARMCMx_STATES_B System logical states in IRQ priority masking mode
|
||||
* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
|
||||
* Cortex-M3 port:
|
||||
* - <b>Init</b>. This state is represented by the startup code and the
|
||||
* initialization code before @p chSysInit() is executed. It has not a
|
||||
* special hardware state associated.
|
||||
* - <b>Normal</b>. This is the state the system has after executing
|
||||
* @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
|
||||
* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
|
||||
* processor is running in thread-privileged mode.
|
||||
* - <b>Suspended</b>. In this state the interrupt sources are not globally
|
||||
|
@ -50,13 +98,14 @@
|
|||
* is running in exception-privileged mode.
|
||||
* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
|
||||
* not globally masked but only interrupts with higher priority can preempt
|
||||
* the current handler. The processor is running in exception-privileged mode.
|
||||
* the current handler. The processor is running in exception-privileged
|
||||
* mode.
|
||||
* - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
|
||||
* but it is not possible to switch to the I-Locked state because fast
|
||||
* interrupts can preempt the kernel critical zone.
|
||||
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
|
||||
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
|
||||
* asynchronous NMI vector and several synchronous fault vectors that can
|
||||
* be considered to be in this category.
|
||||
* be considered belonging to this category.
|
||||
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
|
||||
* the maskable interrupt sources. The ARM state is whatever the processor
|
||||
* was running when @p chSysHalt() was invoked.
|
||||
|
@ -66,18 +115,8 @@
|
|||
* - The @p main() function is invoked in thread-privileged mode.
|
||||
* - Each thread has a private process stack, the system has a single main
|
||||
* stack where all the interrupts and exceptions are processed.
|
||||
* - Only the 4 MSb of the priority level are used, the 4 LSb are assumed
|
||||
* to be zero.
|
||||
* - The threads are started in thread-privileged mode with BASEPRI level
|
||||
* 0x00 (disabled).
|
||||
* - The kernel raises its BASEPRI level to @p CORTEX_BASEPRI_KERNEL in order
|
||||
* to protect the kernel data structures.
|
||||
* - Interrupt nesting and the other advanced NVIC features are supported.
|
||||
* - The SVC instruction and vector, with parameter #0, is internally used
|
||||
* for commanded context switching.<br>
|
||||
* It is possible to share the SVC handler at the cost of slower context
|
||||
* switching.
|
||||
* - The PendSV vector is internally used for preemption context switching.
|
||||
* - The threads are started in thread-privileged mode.
|
||||
* - Interrupt nesting and the other advanced core/NVIC features are supported.
|
||||
* .
|
||||
* @ingroup ports
|
||||
*/
|
||||
|
@ -85,7 +124,7 @@
|
|||
/**
|
||||
* @defgroup ARMCMx_CONF Configuration Options
|
||||
* @brief ARM Cortex-Mx Configuration Options.
|
||||
* @details The ARMCMx port allows some architecture-specific configurations
|
||||
* @details The ARMCM3 port allows some architecture-specific configurations
|
||||
* settings that can be specified externally, as example on the compiler
|
||||
* command line:
|
||||
* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
|
||||
|
@ -97,18 +136,18 @@
|
|||
* - @p CORTEX_BASEPRI_USER, this is the @p BASEPRI value for the user threads.
|
||||
* The default value is @p 0 (disabled).<br>
|
||||
* Usually there is no need to change this value, please refer to the
|
||||
* Cortex-Mx technical reference manual for a detailed description.
|
||||
* Cortex-M3 technical reference manual for a detailed description.
|
||||
* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
|
||||
* code.<br>
|
||||
* Code running at higher priority levels must not invoke any OS API.<br>
|
||||
* Usually there is no need to change this value, please refer to the
|
||||
* Cortex-Mx technical reference manual for a detailed description.
|
||||
* - @p ENABLE_WFI_IDLE, if set to @p 1 enables the use of the @p <b>wfi</b>
|
||||
* instruction from within the idle loop. This is defaulted to 0 because
|
||||
* it can create problems with some debuggers. Setting this option to 1
|
||||
* reduces the system power requirements.
|
||||
* Cortex-M3 technical reference manual for a detailed description.
|
||||
* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p 1 enables the use of the
|
||||
* @p <b>wfi</b> instruction from within the idle loop. This is defaulted to
|
||||
* 0 because it can create problems with some debuggers. Setting this option
|
||||
* to 1 reduces the system power requirements.
|
||||
* .
|
||||
* @ingroup ARMCMx
|
||||
* @ingroup ARMCM3
|
||||
*/
|
||||
|
||||
/**
|
||||
|
@ -159,7 +198,6 @@
|
|||
* - @p _bss_end BSS end location +1.
|
||||
* .
|
||||
* @ingroup ARMCMx
|
||||
* @file ARMCMx/crt0.s Startup code.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
Loading…
Reference in New Issue