diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h index 30097f65c..8cacd9a2a 100644 --- a/demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h +++ b/demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h @@ -65,13 +65,13 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK -#define STM32_PLLSAI1N_VALUE 80 +#define STM32_PLLSAI1N_VALUE 72 #define STM32_PLLSAI1P_VALUE 7 #define STM32_PLLSAI1Q_VALUE 6 -#define STM32_PLLSAI1R_VALUE 4 -#define STM32_PLLSAI2N_VALUE 80 +#define STM32_PLLSAI1R_VALUE 6 +#define STM32_PLLSAI2N_VALUE 72 #define STM32_PLLSAI2P_VALUE 7 -#define STM32_PLLSAI2R_VALUE 4 +#define STM32_PLLSAI2R_VALUE 6 #define STM32_USART1SEL STM32_USART1SEL_SYSCLK #define STM32_USART2SEL STM32_USART2SEL_SYSCLK #define STM32_USART3SEL STM32_USART3SEL_SYSCLK @@ -85,12 +85,45 @@ #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF #define STM32_SAI2SEL STM32_SAI2SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLL +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1 #define STM32_RTCSEL STM32_RTCSEL_LSI +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE FALSE +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + /* * SERIAL driver system settings. */ diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h index 399112cd8..ad0f62836 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h @@ -31,9 +31,16 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @brief DMA capability. + * @details if @p TRUE then the DMA is able of burst transfers, FIFOs, + * scatter gather and other advanced features. + */ +#define STM32_DMA_ADVANCED FALSE + /** * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. + * @details This is the total number of streams among all the DMA units. */ #define STM32_DMA_STREAMS (STM32_DMA1_NUM_CHANNELS + \ STM32_DMA2_NUM_CHANNELS) diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h index 7f7b5a1dc..d2053ad0e 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h @@ -29,9 +29,16 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @brief DMA capability. + * @details if @p TRUE then the DMA is able of burst transfers, FIFOs, + * scatter gather and other advanced features. + */ +#define STM32_DMA_ADVANCED TRUE + /** * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. + * @details This is the total number of streams among all the DMA units. */ #define STM32_DMA_STREAMS 16U @@ -635,9 +642,11 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @param[in] dmastp pointer to a stm32_dma_stream_t structure */ #define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->stream->NDTR > 0U) \ + (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE); \ + while ((dmastp)->stream->CR & STM32_DMA_CR_EN) \ ; \ - dmaStreamDisable(dmastp); \ + dmaStreamClearInterrupt(dmastp); \ } /** @} */ diff --git a/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c b/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c index cdc4934e9..53062b6a6 100644 --- a/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c +++ b/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c @@ -234,7 +234,7 @@ static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n, /*while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF) dmaStreamClearInterrupt(sdcp->dma);*/ #else - /* Waits for transfer completion at DMA level, the the stream is + /* Waits for transfer completion at DMA level, then the stream is disabled and cleared.*/ dmaWaitCompletion(sdcp->dma); diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c b/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c index 768258303..386e23b4c 100644 --- a/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c +++ b/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c @@ -248,12 +248,9 @@ static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n, return HAL_FAILED; } - /* Wait until DMA channel enabled to be sure that all data transferred.*/ - while (sdcp->dma->stream->CR & STM32_DMA_CR_EN) - ; - - /* DMA event flags must be manually cleared.*/ - dmaStreamClearInterrupt(sdcp->dma); + /* Waits for transfer completion at DMA level, then the stream is + disabled and cleared.*/ + dmaWaitCompletion(sdcp->dma); sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS; sdcp->sdmmc->DCTRL = 0; @@ -309,7 +306,6 @@ static void sdc_lld_error_cleanup(SDCDriver *sdcp, uint32_t *resp) { uint32_t sta = sdcp->sdmmc->STA; - dmaStreamClearInterrupt(sdcp->dma); dmaStreamDisable(sdcp->dma); sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS; sdcp->sdmmc->MASK = 0; @@ -389,7 +385,7 @@ void sdc_lld_start(SDCDriver *sdcp) { STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC; -#if 1 +#if STM32_DMA_ADVANCED sdcp->dmamode |= STM32_DMA_CR_PFCTRL | STM32_DMA_CR_PBURST_INCR4 | STM32_DMA_CR_MBURST_INCR4; @@ -401,7 +397,7 @@ void sdc_lld_start(SDCDriver *sdcp) { b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDMMC1_IRQ_PRIORITY, NULL, NULL); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdmmc->FIFO); -#if 1 +#if STM32_DMA_ADVANCED dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); #endif nvicEnableVector(STM32_SDMMC1_NUMBER, STM32_SDC_SDMMC1_IRQ_PRIORITY); diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h b/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h index eb0ce6b18..fc4511344 100644 --- a/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h +++ b/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h @@ -65,13 +65,13 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK -#define STM32_PLLSAI1N_VALUE 80 +#define STM32_PLLSAI1N_VALUE 72 #define STM32_PLLSAI1P_VALUE 7 #define STM32_PLLSAI1Q_VALUE 6 -#define STM32_PLLSAI1R_VALUE 4 -#define STM32_PLLSAI2N_VALUE 80 +#define STM32_PLLSAI1R_VALUE 6 +#define STM32_PLLSAI2N_VALUE 72 #define STM32_PLLSAI2P_VALUE 7 -#define STM32_PLLSAI2R_VALUE 4 +#define STM32_PLLSAI2R_VALUE 6 #define STM32_USART1SEL STM32_USART1SEL_SYSCLK #define STM32_USART2SEL STM32_USART2SEL_SYSCLK #define STM32_USART3SEL STM32_USART3SEL_SYSCLK @@ -85,7 +85,7 @@ #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF #define STM32_SAI2SEL STM32_SAI2SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLL +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1 @@ -132,6 +132,18 @@ #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM8_IRQ_PRIORITY 7 +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + /* * SERIAL driver system settings. */