git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_17.6.x@10957 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-11-05 11:11:39 +00:00
parent 173ae41522
commit 4cfd7100f9
3 changed files with 10 additions and 6 deletions

View File

@ -730,9 +730,10 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
/* Only enable TC interrupt if there's a callback attached to it.
Also we need to clear TC flag which could be set before. */
if (uartp->config->txend2_cb != NULL) {
/* Only enable TC interrupt if there's a callback attached to it or
if called from uartSendFullTimeout(). Also we need to clear TC flag
which could be set before.*/
if ((uartp->config->txend2_cb != NULL) || (uartp->early == false)) {
uartp->usart->SR = ~USART_SR_TC;
uartp->usart->CR1 |= USART_CR1_TCIE;
}

View File

@ -953,9 +953,10 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
/* Only enable TC interrupt if there's a callback attached to it.
Also we need to clear TC flag which could be set before. */
if (uartp->config->txend2_cb != NULL) {
/* Only enable TC interrupt if there's a callback attached to it or
if called from uartSendFullTimeout(). Also we need to clear TC flag
which could be set before.*/
if ((uartp->config->txend2_cb != NULL) || (uartp->early == false)) {
uartp->usart->ICR = USART_ICR_TCCF;
uartp->usart->CR1 |= USART_CR1_TCIE;
}

View File

@ -89,6 +89,8 @@
*****************************************************************************
*** 17.6.3 ***
- HAL: Fixed function uartSendFullTimeout() failing on STM32 USARTv1 and
v2 drivers (bug #901).
- HAL: Fixed broken I2C fallback driver (bug #900).
- LIB: Fixed heap buffer alignment not enforced (bug #899).
- LIB: Fixed call protocol violation in chCoreAlloc() (bug #896).