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STM32F7xx clock tree and initialization done. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8144 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2015-08-02 10:33:23 +00:00
parent 0aee8c6229
commit 4d7be5bf04
7 changed files with 79 additions and 47 deletions
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2
demos/STM32/RT-STM32F746G-DISCOVERY/.project
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@ -79,7 +79,7 @@
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F476G_DISCOVERY</locationURI>
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F746G_DISCOVERY</locationURI>
</link>
<link>
<name>os</name>

2
demos/STM32/RT-STM32F746G-DISCOVERY/Makefile
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@ -92,7 +92,7 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_STM32F476G_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk

71
demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h
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@ -37,32 +37,57 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 432
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSE
#define STM32_RTCPRE_VALUE 25
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
#define STM32_UART4SEL STM32_UART4SEL_PCLK1
#define STM32_UART5SEL STM32_UART5SEL_PCLK1
#define STM32_USART6SEL STM32_USART6SEL_PCLK2
#define STM32_UART7SEL STM32_UART7SEL_PCLK1
#define STM32_UART8SEL STM32_UART8SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
/*
* ADC driver system settings.

6
os/hal/boards/ST_STM32F746G_DISCOVERY/board.h
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@ -33,13 +33,15 @@
* NOTE: LSE not fitted.
*/
#if !defined(STM32_LSECLK)
#define STM32_LSECLK 0U
#define STM32_LSECLK 32768U
#endif
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 8000000U
#define STM32_HSECLK 25000000U
#endif
#define STM32_HSE_BYPASS
/*
* Board voltages.
* Required for performance limits calculation.

4
os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk
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@ -1,5 +1,5 @@
# List of all the board related files.
BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F476G_DISCOVERY/board.c
BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F746G_DISCOVERY/board.c
# Required include directories
BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F476G_DISCOVERY
BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F746G_DISCOVERY

29
os/hal/ports/STM32/STM32F7xx/hal_lld.c
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@ -16,7 +16,7 @@
/**
* @file STM32F7xx/hal_lld.c
* @brief STM32F7xx/STM32F2xx HAL subsystem low level driver source.
* @brief STM32F7xx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
@ -34,7 +34,7 @@
/**
* @brief CMSIS system core clock variable.
* @note It is declared in system_STM32F7xx.h.
* @note It is declared in system_stm32f7xx.h.
*/
uint32_t SystemCoreClock = STM32_SYSCLK;
@ -150,11 +150,7 @@ void stm32_clock_init(void) {
RCC->APB1ENR = RCC_APB1ENR_PWREN;
/* PWR initialization.*/
#if defined(STM32F7xx) || defined(__DOXYGEN__)
PWR->CR1 = STM32_VOS;
#else
PWR->CR1 = 0;
#endif
/* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
@ -201,7 +197,6 @@ void stm32_clock_init(void) {
RCC->CR |= RCC_CR_PLLON;
/* Synchronization with voltage regulator stabilization.*/
#if defined(STM32F7xx)
while ((PWR->CSR1 & PWR_CSR1_VOSRDY) == 0)
; /* Waits until power regulator is stable. */
@ -215,7 +210,6 @@ void stm32_clock_init(void) {
while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY))
;
#endif /* STM32_OVERDRIVE_REQUIRED */
#endif /* defined(STM32F7xx) */
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLRDY))
@ -234,8 +228,10 @@ void stm32_clock_init(void) {
#if STM32_ACTIVATE_PLLSAI
/* PLLSAI activation.*/
RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ;
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIQ | STM32_PLLSAIP |
STM32_PLLSAIN;
RCC->DCKCFGR1 = /*STM32_TIMPRE | */STM32_SAI2SEL | STM32_SAI1SEL |
STM32_PLLSAIDIVR;
RCC->CR |= RCC_CR_PLLSAION;
/* Waiting for PLL lock.*/
@ -244,8 +240,17 @@ void stm32_clock_init(void) {
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->CFGR = STM32_MCO2SEL | STM32_MCO2PRE | STM32_MCO1PRE | STM32_I2SSRC |
STM32_MCO1SEL | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
/* Peripheral clock sources.*/
RCC->DCKCFGR2 = STM32_SDMMCSEL | STM32_CK48MSEL | STM32_CECSEL |
STM32_LPTIM1SEL | STM32_I2C4SEL | STM32_I2C4SEL |
STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_UART8SEL | STM32_UART7SEL | STM32_USART6SEL |
STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
STM32_USART2SEL | STM32_USART1SEL;
/* Flash setup.*/
FLASH->ACR = FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS;

12
os/hal/ports/STM32/STM32F7xx/hal_lld.h
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@ -175,9 +175,9 @@
* @name PWR_CR register bits definitions
* @{
*/
#define STM32_VOS_SCALE3 (PWR_CR_VOS_0)
#define STM32_VOS_SCALE2 (PWR_CR_VOS_1)
#define STM32_VOS_SCALE1 (PWR_CR_VOS_1 | PWR_CR_VOS_0)
#define STM32_VOS_SCALE3 (PWR_CR1_VOS_0)
#define STM32_VOS_SCALE2 (PWR_CR1_VOS_1)
#define STM32_VOS_SCALE1 (PWR_CR1_VOS_1 | PWR_CR1_VOS_0)
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
@ -605,7 +605,7 @@
/**
* @brief MC02 clock source value.
* @note The default value outputs SYSCLK / 8 on MC02 pin.
* @note The default value outputs SYSCLK / 4 on MC02 pin.
*/
#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
@ -613,10 +613,10 @@
/**
* @brief MC02 prescaler value.
* @note The default value outputs SYSCLK / 8 on MC02 pin.
* @note The default value outputs SYSCLK / 4 on MC02 pin.
*/
#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
#define STM32_MCO2PRE STM32_MCO2PRE_DIV8
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#endif
/**