Feature request #28 merged. Updated mcuconf.h files.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5915 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -245,6 +245,8 @@
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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@ -252,15 +254,23 @@
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_UART4_IRQ_PRIORITY 12
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#define STM32_UART_UART5_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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@ -245,6 +245,8 @@
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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@ -252,15 +254,23 @@
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_UART4_IRQ_PRIORITY 12
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#define STM32_UART_UART5_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_UART4_IRQ_PRIORITY 12
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#define STM32_UART_UART5_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_UART4_IRQ_PRIORITY 12
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#define STM32_UART_UART5_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_UART4_IRQ_PRIORITY 12
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#define STM32_UART_UART5_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART6_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_UART4_DMA_PRIORITY 0
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#define STM32_UART_UART5_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USE_UART4 FALSE
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#define STM32_UART_USE_UART5 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 TRUE
|
#define STM32_UART_USE_USART1 TRUE
|
||||||
#define STM32_UART_USE_USART2 TRUE
|
#define STM32_UART_USE_USART2 TRUE
|
||||||
#define STM32_UART_USE_USART3 TRUE
|
#define STM32_UART_USE_USART3 TRUE
|
||||||
|
#define STM32_UART_USE_UART4 TRUE
|
||||||
|
#define STM32_UART_USE_UART5 TRUE
|
||||||
#define STM32_UART_USE_USART6 TRUE
|
#define STM32_UART_USE_USART6 TRUE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
|
@ -245,6 +245,8 @@
|
||||||
#define STM32_UART_USE_USART1 FALSE
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
#define STM32_UART_USE_USART2 FALSE
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
#define STM32_UART_USE_USART3 FALSE
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USE_UART4 FALSE
|
||||||
|
#define STM32_UART_USE_UART5 FALSE
|
||||||
#define STM32_UART_USE_USART6 FALSE
|
#define STM32_UART_USE_USART6 FALSE
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
|
@ -252,15 +254,23 @@
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||||
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||||
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||||
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||||
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue