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ChibiOS
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Fixed bug #1207. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15218 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-12-08 09:57:13 +00:00
parent 2a0e158bab
commit 4dac93cf65
15 changed files with 22 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
os/hal/boards/ST_NUCLEO144_L4R5ZI/board.h
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@ -42,7 +42,7 @@
* NOTE: HSE not fitted.
*/
#if !defined(STM32_LSECLK)
#define STM32_LSECLK 0U
#define STM32_LSECLK 32768U
#endif
#define STM32_LSEDRV (3U << 3U)

2
readme.txt
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@ -101,6 +101,8 @@
ARMv7-M and ARMv8-M-ML.
- NEW: On STM32WBxx added a check on STM32_LSI_ENABLE required by IWDG.
- NEW: Added SPIv2 support also to STM32WB and STM32WL.
- FIX: Fixed PWR_CR2_USV not set in STM32L4+ mcuconf.h file (bug #1207)
(backported to 21.11.1).
- FIX: Fixed USB not enabled on STM32F103x6 (bug #1206)
(backported to 20.3.5)(backported to 21.11.1).
- FIX: Fixed RT test suite build fails when CH_CFG_USE_TIMESTAMP is FALSE

2
testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h
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@ -46,7 +46,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
testhal/STM32/multi/SDMMC/cfg/stm32l4r9ai_discovery/mcuconf.h
View File

@ -46,7 +46,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
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@ -46,7 +46,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

14
testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)
@ -73,8 +73,8 @@
#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
@ -93,16 +93,16 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 48
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 4
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 48
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 4
#define STM32_PLLSAI2Q_VALUE 6
#define STM32_PLLSAI2R_VALUE 6
#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16

2
testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
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@ -48,7 +48,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)
#define STM32_PWR_PUCRA (0U)

2
tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
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@ -57,7 +57,7 @@
#define STM32_CLOCK_DYNAMIC ${doc.STM32_CLOCK_DYNAMIC!"FALSE"}
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
#define STM32_PWR_BOOST ${doc.STM32_PWR_BOOST!"TRUE"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV | PWR_CR2_USV)"}
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}
#define STM32_PWR_PUCRA ${doc.STM32_PWR_PUCRA!"(0U)"}