More L1-related fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8174 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
a9b125afb4
commit
4e935e11dd
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@ -305,11 +305,7 @@ OSAL_IRQ_HANDLER(Vector98) {
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*
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*
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* @isr
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* @isr
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*/
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*/
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#if defined(STM32L1XX_MDP) || defined(__DOXYGEN__)
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OSAL_IRQ_HANDLER(Vector114) {
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#else
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OSAL_IRQ_HANDLER(Vector120) {
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OSAL_IRQ_HANDLER(Vector120) {
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#endif
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uint32_t pr;
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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@ -31,9 +31,6 @@
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* STM32L152xD, STM32L152xDX, STM32L152xE.
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* STM32L152xD, STM32L152xDX, STM32L152xE.
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* - STM32L162xC, STM32L162xCA, STM32L162xD, STM32L162xDX,
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* - STM32L162xC, STM32L162xCA, STM32L162xD, STM32L162xDX,
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* STM32L162xE.
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* STM32L162xE.
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* - STM32L1XX_MD for Ultra Low Power Medium-density devices.
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* - STM32L1XX_MDP for Ultra Low Power Medium-density Plus devices.
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* - STM32L1XX_HD for Ultra Low Power High-density devices.
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* .
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* .
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*
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*
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* @addtogroup HAL
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* @addtogroup HAL
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@ -260,6 +260,31 @@
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* @api
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* @api
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*/
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*/
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#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
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#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
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/**
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* @brief Enables the DMA2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
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/**
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* @brief Disables the DMA2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
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/**
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* @brief Resets the DMA2 peripheral.
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*
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* @api
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*/
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#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
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/** @} */
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/** @} */
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/**
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/**
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@ -25,23 +25,29 @@
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#ifndef _STM32_REGISTRY_H_
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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#if defined(STM32L100xB) || defined(STM32L151xB) || \
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#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
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defined(STM32L152xB) || defined(__DOXYGEN__)
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#define STM32L1XX_PROD_CAT 1
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#define STM32L1XX_MD
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#elif defined(STM32L100xBA) || defined(STM32L100xC) || \
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#elif defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)
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defined(STM32L151xBA) || defined(STM32L151xC) || \
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#define STM32L1XX_PROD_CAT 2
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defined(STM32L151xCA) || defined(STM32L152xBA) || \
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defined(STM32L152xC) || defined(STM32L152xCA) || \
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defined(STM32L162xC) || defined(STM32L162xCA)
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#define STM32L1XX_MDP
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#elif defined(STM32L151xD) || defined(STM32L151xDX) || \
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#elif defined(STM32L100xC) || defined(STM32L151xC) || \
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defined(STM32L151xE) || defined(STM32L152xD) || \
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defined(STM32L151xCA) || defined(STM32L152xC) || \
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defined(STM32L152xDX) || defined(STM32L152xE) || \
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defined(STM32L152xCA) || defined(STM32L162xC) || \
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defined(STM32L162xD) || defined(STM32L162xDX) || \
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defined(STM32L162xCA)
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#define STM32L1XX_PROD_CAT 3
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#elif defined(STM32L151xD) || defined(STM32L152xD) || \
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defined(STM32L162xD)
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#define STM32L1XX_PROD_CAT 4
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#elif defined(STM32L151xE) || defined (STM32L152xE) || \
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defined(STM32L162xE)
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defined(STM32L162xE)
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#define STM32L1XX_HD
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#define STM32L1XX_PROD_CAT 5
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#elif defined(STM32L151xDX) || defined (STM32L152xDX) || \
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defined(STM32L162xDX)
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#define STM32L1XX_PROD_CAT 6
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#else
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#else
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#error "STM32L1xx device not specified"
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#error "STM32L1xx device not specified"
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@ -55,8 +61,6 @@
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* @name STM32L1xx capabilities
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* @name STM32L1xx capabilities
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* @{
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* @{
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*/
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*/
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#if defined(STM32L1XX_MD) || defined(STM32L1XX_MDP) || defined(__DOXYGEN__)
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/* ADC attributes.*/
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC2 FALSE
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@ -78,11 +82,6 @@
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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/* DMA attributes.*/
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_ADVANCED_DMA FALSE
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@ -103,16 +102,37 @@
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#define STM32_DMA1_CH6_NUMBER 16
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#define STM32_DMA1_CH6_NUMBER 16
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#define STM32_DMA1_CH7_NUMBER 17
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#define STM32_DMA1_CH7_NUMBER 17
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#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
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defined(__DOXYGEN__)
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#define STM32_DMA2_NUM_CHANNELS 0
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#define STM32_DMA2_NUM_CHANNELS 0
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#else
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#define STM32_DMA2_NUM_CHANNELS 5
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#define STM32_DMA2_CH1_HANDLER Vector108
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#define STM32_DMA2_CH2_HANDLER Vector10C
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#define STM32_DMA2_CH3_HANDLER Vector110
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#define STM32_DMA2_CH4_HANDLER Vector114
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#define STM32_DMA2_CH5_HANDLER Vector118
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#define STM32_DMA2_CH1_NUMBER 50
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#define STM32_DMA2_CH2_NUMBER 51
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#define STM32_DMA2_CH3_NUMBER 52
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#define STM32_DMA2_CH4_NUMBER 53
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#define STM32_DMA2_CH5_NUMBER 54
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#endif
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/* ETH attributes.*/
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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/* EXTI attributes.*/
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#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
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defined(__DOXYGEN__)
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#define STM32_EXTI_NUM_LINES 23
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#define STM32_EXTI_NUM_LINES 23
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#else
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#define STM32_EXTI_NUM_LINES 24
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#endif
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#define STM32_EXTI_IMR_MASK 0x00000000U
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#define STM32_EXTI_IMR_MASK 0x00000000U
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/* GPIO attributes.*/
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#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
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(STM32L1XX_PROD_CAT == 3) || defined(__DOXYGEN__)
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOC TRUE
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@ -130,6 +150,27 @@
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | \
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RCC_AHBENR_GPIOEEN | \
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RCC_AHBENR_GPIOHEN)
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RCC_AHBENR_GPIOHEN)
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#else
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
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RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | \
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | \
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RCC_AHBENR_GPIOFEN | \
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RCC_AHBENR_GPIOGEN | \
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RCC_AHBENR_GPIOHEN)
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#endif
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/* I2C attributes.*/
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C1 TRUE
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/* RTC attributes.*/
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_RTC TRUE
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#if defined(STM32L1XX_MDP)
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#if (STM32L1XX_PROD_CAT == 1) || defined(__DOXYGEN__)
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#else
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#define STM32_RTC_HAS_SUBSECONDS FALSE
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#define STM32_RTC_HAS_SUBSECONDS FALSE
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#else
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#endif
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#endif
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
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defined(__DOXYGEN__)
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI3 FALSE
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#else
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#endif
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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#define STM32_HAS_SPI6 FALSE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_TIM4_CHANNELS 4
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#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
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defined(__DOXYGEN__)
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#define STM32_HAS_TIM5 FALSE
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#else
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#endif
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_TIM6_CHANNELS 0
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#define STM32_TIM11_CHANNELS 2
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#define STM32_TIM11_CHANNELS 2
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#define STM32_HAS_TIM1 FALSE
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#define STM32_HAS_TIM1 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) || \
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(STM32L1XX_PROD_CAT == 3) || defined(__DOXYGEN__)
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_UART5 FALSE
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#else
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#define STM32_HAS_UART4 TRUE
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_HAS_UART5 TRUE
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#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#endif
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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#define STM32_HAS_UART8 FALSE
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#define STM32_HAS_CRC TRUE
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE FALSE
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#define STM32_CRC_PROGRAMMABLE FALSE
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#else /* STM32L1XX_HD */
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 0
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA1_CH1_HANDLER Vector6C
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#define STM32_DMA1_CH2_HANDLER Vector70
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#define STM32_DMA1_CH3_HANDLER Vector74
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#define STM32_DMA1_CH4_HANDLER Vector78
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#define STM32_DMA1_CH5_HANDLER Vector7C
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#define STM32_DMA1_CH6_HANDLER Vector80
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#define STM32_DMA1_CH7_HANDLER Vector84
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#define STM32_DMA1_CH1_NUMBER 11
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||||||
#define STM32_DMA1_CH2_NUMBER 12
|
|
||||||
#define STM32_DMA1_CH3_NUMBER 13
|
|
||||||
#define STM32_DMA1_CH4_NUMBER 14
|
|
||||||
#define STM32_DMA1_CH5_NUMBER 15
|
|
||||||
#define STM32_DMA1_CH6_NUMBER 16
|
|
||||||
#define STM32_DMA1_CH7_NUMBER 17
|
|
||||||
|
|
||||||
#define STM32_DMA2_NUM_CHANNELS 5
|
|
||||||
#define STM32_DMA2_CH1_HANDLER Vector108
|
|
||||||
#define STM32_DMA2_CH2_HANDLER Vector10C
|
|
||||||
#define STM32_DMA2_CH3_HANDLER Vector110
|
|
||||||
#define STM32_DMA2_CH4_HANDLER Vector114
|
|
||||||
#define STM32_DMA2_CH5_HANDLER Vector118
|
|
||||||
#define STM32_DMA2_CH1_NUMBER 50
|
|
||||||
#define STM32_DMA2_CH2_NUMBER 51
|
|
||||||
#define STM32_DMA2_CH3_NUMBER 52
|
|
||||||
#define STM32_DMA2_CH4_NUMBER 53
|
|
||||||
#define STM32_DMA2_CH5_NUMBER 54
|
|
||||||
|
|
||||||
/* ETH attributes.*/
|
|
||||||
#define STM32_HAS_ETH FALSE
|
|
||||||
|
|
||||||
/* EXTI attributes.*/
|
|
||||||
#define STM32_EXTI_NUM_LINES 24
|
|
||||||
#define STM32_EXTI_IMR_MASK 0x00000000U
|
|
||||||
|
|
||||||
/* GPIO attributes.*/
|
|
||||||
#define STM32_HAS_GPIOA TRUE
|
|
||||||
#define STM32_HAS_GPIOB TRUE
|
|
||||||
#define STM32_HAS_GPIOC TRUE
|
|
||||||
#define STM32_HAS_GPIOD TRUE
|
|
||||||
#define STM32_HAS_GPIOE TRUE
|
|
||||||
#define STM32_HAS_GPIOF TRUE
|
|
||||||
#define STM32_HAS_GPIOG TRUE
|
|
||||||
#define STM32_HAS_GPIOH TRUE
|
|
||||||
#define STM32_HAS_GPIOI FALSE
|
|
||||||
#define STM32_HAS_GPIOJ FALSE
|
|
||||||
#define STM32_HAS_GPIOK FALSE
|
|
||||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
||||||
RCC_AHBENR_GPIOBEN | \
|
|
||||||
RCC_AHBENR_GPIOCEN | \
|
|
||||||
RCC_AHBENR_GPIODEN | \
|
|
||||||
RCC_AHBENR_GPIOEEN | \
|
|
||||||
RCC_AHBENR_GPIOFEN | \
|
|
||||||
RCC_AHBENR_GPIOGEN | \
|
|
||||||
RCC_AHBENR_GPIOHEN)
|
|
||||||
|
|
||||||
/* I2C attributes.*/
|
|
||||||
#define STM32_HAS_I2C1 TRUE
|
|
||||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
||||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
||||||
|
|
||||||
#define STM32_HAS_I2C2 TRUE
|
|
||||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
||||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
||||||
|
|
||||||
#define STM32_HAS_I2C3 FALSE
|
|
||||||
|
|
||||||
/* RTC attributes.*/
|
|
||||||
#define STM32_HAS_RTC TRUE
|
|
||||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
||||||
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
||||||
#define STM32_RTC_NUM_ALARMS 2
|
|
||||||
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
||||||
|
|
||||||
/* SDIO attributes.*/
|
|
||||||
#define STM32_HAS_SDIO TRUE
|
|
||||||
|
|
||||||
/* SPI attributes.*/
|
|
||||||
#define STM32_HAS_SPI1 TRUE
|
|
||||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
||||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
||||||
|
|
||||||
#define STM32_HAS_SPI2 TRUE
|
|
||||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
||||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
||||||
|
|
||||||
#define STM32_HAS_SPI3 TRUE
|
|
||||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
|
||||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
|
||||||
|
|
||||||
#define STM32_HAS_SPI4 FALSE
|
|
||||||
#define STM32_HAS_SPI5 FALSE
|
|
||||||
#define STM32_HAS_SPI6 FALSE
|
|
||||||
|
|
||||||
/* TIM attributes.*/
|
|
||||||
#define STM32_TIM_MAX_CHANNELS 4
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM2 TRUE
|
|
||||||
#define STM32_TIM2_IS_32BITS FALSE
|
|
||||||
#define STM32_TIM2_CHANNELS 4
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM3 TRUE
|
|
||||||
#define STM32_TIM3_IS_32BITS FALSE
|
|
||||||
#define STM32_TIM3_CHANNELS 4
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM4 TRUE
|
|
||||||
#define STM32_TIM4_IS_32BITS FALSE
|
|
||||||
#define STM32_TIM4_CHANNELS 4
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM5 TRUE
|
|
||||||
#define STM32_TIM5_IS_32BITS TRUE
|
|
||||||
#define STM32_TIM5_CHANNELS 4
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM6 TRUE
|
|
||||||
#define STM32_TIM6_IS_32BITS FALSE
|
|
||||||
#define STM32_TIM6_CHANNELS 0
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM7 TRUE
|
|
||||||
#define STM32_TIM7_IS_32BITS FALSE
|
|
||||||
#define STM32_TIM7_CHANNELS 0
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM9 TRUE
|
|
||||||
#define STM32_TIM9_IS_32BITS FALSE
|
|
||||||
#define STM32_TIM9_CHANNELS 2
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM10 TRUE
|
|
||||||
#define STM32_TIM10_IS_32BITS FALSE
|
|
||||||
#define STM32_TIM10_CHANNELS 2
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM11 TRUE
|
|
||||||
#define STM32_TIM11_IS_32BITS FALSE
|
|
||||||
#define STM32_TIM11_CHANNELS 2
|
|
||||||
|
|
||||||
#define STM32_HAS_TIM1 FALSE
|
|
||||||
#define STM32_HAS_TIM8 FALSE
|
|
||||||
#define STM32_HAS_TIM12 FALSE
|
|
||||||
#define STM32_HAS_TIM13 FALSE
|
|
||||||
#define STM32_HAS_TIM14 FALSE
|
|
||||||
#define STM32_HAS_TIM15 FALSE
|
|
||||||
#define STM32_HAS_TIM16 FALSE
|
|
||||||
#define STM32_HAS_TIM17 FALSE
|
|
||||||
#define STM32_HAS_TIM18 FALSE
|
|
||||||
#define STM32_HAS_TIM19 FALSE
|
|
||||||
#define STM32_HAS_TIM20 FALSE
|
|
||||||
#define STM32_HAS_TIM21 FALSE
|
|
||||||
#define STM32_HAS_TIM22 FALSE
|
|
||||||
|
|
||||||
/* USART attributes.*/
|
|
||||||
#define STM32_HAS_USART1 TRUE
|
|
||||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
||||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
||||||
|
|
||||||
#define STM32_HAS_USART2 TRUE
|
|
||||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
||||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
||||||
|
|
||||||
#define STM32_HAS_USART3 TRUE
|
|
||||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
||||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
||||||
|
|
||||||
#define STM32_HAS_UART4 TRUE
|
|
||||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
|
||||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
|
||||||
|
|
||||||
#define STM32_HAS_UART5 TRUE
|
|
||||||
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
|
||||||
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
|
||||||
|
|
||||||
#define STM32_HAS_USART6 FALSE
|
|
||||||
|
|
||||||
/* USB attributes.*/
|
|
||||||
#define STM32_HAS_USB TRUE
|
|
||||||
#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
|
|
||||||
#define STM32_USB_PMA_SIZE 512
|
|
||||||
#define STM32_USB_HAS_BCDR FALSE
|
|
||||||
#define STM32_HAS_OTG1 FALSE
|
|
||||||
#define STM32_HAS_OTG2 FALSE
|
|
||||||
|
|
||||||
/* LTDC attributes.*/
|
|
||||||
#define STM32_HAS_LTDC FALSE
|
|
||||||
|
|
||||||
/* DMA2D attributes.*/
|
|
||||||
#define STM32_HAS_DMA2D FALSE
|
|
||||||
|
|
||||||
/* FSMC attributes.*/
|
|
||||||
#define STM32_HAS_FSMC FALSE
|
|
||||||
|
|
||||||
/* CRC attributes.*/
|
|
||||||
#define STM32_HAS_CRC TRUE
|
|
||||||
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
||||||
|
|
||||||
#endif /* STM32L1XX_HD */
|
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
#endif /* _STM32_REGISTRY_H_ */
|
#endif /* _STM32_REGISTRY_H_ */
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue