diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index e65e5c570..968c00fd9 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -28,6 +28,10 @@
 /* Driver local definitions.                                                 */
 /*===========================================================================*/
 
+#define RCC_AHB1RSTR_DONOTTOUCH_Pos             (31U)
+#define RCC_AHB1RSTR_DONOTTOUCH_Msk             (0x1UL << RCC_AHB1RSTR_DONOTTOUCH_Pos)
+#define RCC_AHB1RSTR_DONOTTOUCH                 RCC_AHB1RSTR_DONOTTOUCH_Msk
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -149,8 +153,11 @@ void hal_lld_init(void) {
   /* Reset of all peripherals. AHB3 is not reset entirely because FMC could
      have been initialized in the board initialization file (board.c).
      Note, GPIOs are not reset because initialized before this point in
-     board files.*/
-  __rccResetAHB1(~0);
+     board files.
+     Note that there is an undocumented bit in AHB1, presumably the cache
+     reset, which must not be touched because the cache is write-back and
+     latest writes could be lost.*/
+  __rccResetAHB1(~RCC_AHB1RSTR_DONOTTOUCH);
   __rccResetAHB2(~0);
   __rccResetAHB3(~(RCC_AHB3RSTR_FMCRST |
 #if defined(STM32_QSPI_NO_RESET)
diff --git a/readme.txt b/readme.txt
index 7e9afbd51..c1a5502a9 100644
--- a/readme.txt
+++ b/readme.txt
@@ -110,6 +110,8 @@
        instead of a simple size.
 - NEW: RT and NIL upgraded to support the enhanced OSLIB.
 - NEW: Memory areas/pointers checker functions added to OSLIB.
+- FIX: Fixed unwanted reset of cache on STM32H7xx (bug #1258)
+       (backported to 20.3.5)(backported to 21.11.4).
 - FIX: Fixed invalid HSIDIV in STM32Ggxx clocks initialization (bug #1257)
        (backported to 21.11.4).
 - FIX: Fixed incorrect RTC initialization on STM32G4/L4/L4+ (bug #1256)