andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

More style fixes. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12802 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-05-18 10:42:02 +00:00
parent 4bca2e749d
commit 4f7cf535be
40 changed files with 82 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
os/hal/osal/os-less/AVR/osal.h
View File

@ -64,7 +64,6 @@
#define MSG_WAIT (msg_t)-10 #define MSG_WAIT (msg_t)-10
/** @} */ /** @} */
/** /**
* @name Special time constants * @name Special time constants
* @{ * @{
@ -587,7 +586,7 @@ static inline syssts_t osalSysGetStatusAndLockX(void) {
sts = SREG; sts = SREG;
asm volatile ("cli" : : : "memory"); asm volatile ("cli" : : : "memory");
return sts; return sts;
} }

2
os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.h
View File

@ -225,7 +225,7 @@ typedef void (*stm32_bdmaisr_t)(void *p, uint32_t flags);
* @brief STM32 BDMA stream descriptor structure. * @brief STM32 BDMA stream descriptor structure.
*/ */
typedef struct { typedef struct {
BDMA_TypeDef *bdma ; /**< @brief Associated BDMA. */ BDMA_TypeDef *bdma; /**< @brief Associated BDMA. */
BDMA_Channel_TypeDef *channel; /**< @brief Associated BDMA channel.*/ BDMA_Channel_TypeDef *channel; /**< @brief Associated BDMA channel.*/
uint8_t shift; /**< @brief Bit offset in ISR and uint8_t shift; /**< @brief Bit offset in ISR and
IFCR registers. */ IFCR registers. */

22
os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c
View File

@ -83,7 +83,7 @@ static void can_lld_set_filters(CANDriver* canp,
const CANFilter *cfp) { const CANFilter *cfp) {
#if STM32_CAN_USE_CAN2 #if STM32_CAN_USE_CAN2
if(canp == &CAND2) { if (canp == &CAND2) {
/* Set handle to CAN1, because CAN1 manages the filters of CAN2.*/ /* Set handle to CAN1, because CAN1 manages the filters of CAN2.*/
canp = &CAND1; canp = &CAND1;
} }
@ -91,7 +91,7 @@ static void can_lld_set_filters(CANDriver* canp,
/* Temporarily enabling CAN clock.*/ /* Temporarily enabling CAN clock.*/
#if STM32_CAN_USE_CAN1 #if STM32_CAN_USE_CAN1
if(canp == &CAND1) { if (canp == &CAND1) {
rccEnableCAN1(true); rccEnableCAN1(true);
/* Filters initialization.*/ /* Filters initialization.*/
canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT; canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT;
@ -100,7 +100,7 @@ static void can_lld_set_filters(CANDriver* canp,
#endif #endif
#if STM32_CAN_USE_CAN3 #if STM32_CAN_USE_CAN3
if(canp == &CAND3) { if (canp == &CAND3) {
rccEnableCAN3(true); rccEnableCAN3(true);
/* Filters initialization.*/ /* Filters initialization.*/
canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT; canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT;
@ -117,7 +117,7 @@ static void can_lld_set_filters(CANDriver* canp,
canp->can->FFA1R = 0; canp->can->FFA1R = 0;
#if STM32_CAN_USE_CAN1 #if STM32_CAN_USE_CAN1
if(canp == &CAND1) { if (canp == &CAND1) {
for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) { for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) {
canp->can->sFilterRegister[i].FR1 = 0; canp->can->sFilterRegister[i].FR1 = 0;
canp->can->sFilterRegister[i].FR2 = 0; canp->can->sFilterRegister[i].FR2 = 0;
@ -126,7 +126,7 @@ static void can_lld_set_filters(CANDriver* canp,
#endif #endif
#if STM32_CAN_USE_CAN3 #if STM32_CAN_USE_CAN3
if(canp == &CAND3) { if (canp == &CAND3) {
for (i = 0; i < STM32_CAN3_MAX_FILTERS; i++) { for (i = 0; i < STM32_CAN3_MAX_FILTERS; i++) {
canp->can->sFilterRegister[i].FR1 = 0; canp->can->sFilterRegister[i].FR1 = 0;
canp->can->sFilterRegister[i].FR2 = 0; canp->can->sFilterRegister[i].FR2 = 0;
@ -155,7 +155,7 @@ static void can_lld_set_filters(CANDriver* canp,
canp->can->sFilterRegister[0].FR1 = 0; canp->can->sFilterRegister[0].FR1 = 0;
canp->can->sFilterRegister[0].FR2 = 0; canp->can->sFilterRegister[0].FR2 = 0;
#if STM32_CAN_USE_CAN2 #if STM32_CAN_USE_CAN2
if(canp == &CAND1) { if (canp == &CAND1) {
canp->can->sFilterRegister[can2sb].FR1 = 0; canp->can->sFilterRegister[can2sb].FR1 = 0;
canp->can->sFilterRegister[can2sb].FR2 = 0; canp->can->sFilterRegister[can2sb].FR2 = 0;
} }
@ -165,7 +165,7 @@ static void can_lld_set_filters(CANDriver* canp,
canp->can->FS1R = 1; canp->can->FS1R = 1;
canp->can->FA1R = 1; canp->can->FA1R = 1;
#if STM32_CAN_USE_CAN2 #if STM32_CAN_USE_CAN2
if(canp == &CAND1) { if (canp == &CAND1) {
canp->can->FS1R |= 1 << can2sb; canp->can->FS1R |= 1 << can2sb;
canp->can->FA1R |= 1 << can2sb; canp->can->FA1R |= 1 << can2sb;
} }
@ -176,12 +176,12 @@ static void can_lld_set_filters(CANDriver* canp,
/* Clock disabled, it will be enabled again in can_lld_start().*/ /* Clock disabled, it will be enabled again in can_lld_start().*/
/* Temporarily enabling CAN clock.*/ /* Temporarily enabling CAN clock.*/
#if STM32_CAN_USE_CAN1 #if STM32_CAN_USE_CAN1
if(canp == &CAND1) { if (canp == &CAND1) {
rccDisableCAN1(); rccDisableCAN1();
} }
#endif #endif
#if STM32_CAN_USE_CAN3 #if STM32_CAN_USE_CAN3
if(canp == &CAND3) { if (canp == &CAND3) {
rccDisableCAN3(); rccDisableCAN3();
} }
#endif #endif
@ -1000,12 +1000,12 @@ void canSTM32SetFilters(CANDriver *canp, uint32_t can2sb,
#endif #endif
#if STM32_CAN_USE_CAN1 #if STM32_CAN_USE_CAN1
if(canp == &CAND1) { if (canp == &CAND1) {
can_lld_set_filters(canp, can2sb, num, cfp); can_lld_set_filters(canp, can2sb, num, cfp);
} }
#endif #endif
#if STM32_CAN_USE_CAN3 #if STM32_CAN_USE_CAN3
if(canp == &CAND3) { if (canp == &CAND3) {
can_lld_set_filters(canp, can2sb, num, cfp); can_lld_set_filters(canp, can2sb, num, cfp);
} }
#endif #endif

5
os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
View File

@ -147,7 +147,7 @@
#define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2 #define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2
#endif #endif
/** @} */ /** @} */
/*===========================================================================*/ /*===========================================================================*/
/* Derived constants and error checks. */ /* Derived constants and error checks. */
/*===========================================================================*/ /*===========================================================================*/
@ -347,7 +347,7 @@ typedef enum {
/** /**
* @brief Samples alignment and size mode. * @brief Samples alignment and size mode.
*/ */
typedef enum { typedef enum {
DAC_DHRM_12BIT_RIGHT = 0, DAC_DHRM_12BIT_RIGHT = 0,
DAC_DHRM_12BIT_LEFT = 1, DAC_DHRM_12BIT_LEFT = 1,
DAC_DHRM_8BIT_RIGHT = 2, DAC_DHRM_8BIT_RIGHT = 2,
@ -371,7 +371,6 @@ typedef enum {
/* Associated DMA.*/ \ /* Associated DMA.*/ \
const stm32_dma_stream_t *dma const stm32_dma_stream_t *dma
/** /**
* @brief Low level fields of the DAC configuration structure. * @brief Low level fields of the DAC configuration structure.
*/ */

2
os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h
View File

@ -286,7 +286,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @brief STM32 DMA stream descriptor structure. * @brief STM32 DMA stream descriptor structure.
*/ */
typedef struct { typedef struct {
DMA_TypeDef *dma ; /**< @brief Associated DMA. */ DMA_TypeDef *dma; /**< @brief Associated DMA. */
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
uint32_t cmask; /**< @brief Mask of streams sharing uint32_t cmask; /**< @brief Mask of streams sharing
the same ISR. */ the same ISR. */

1
os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c
View File

@ -49,7 +49,6 @@
*/ */
#define STM32_DMA2_STREAMS_MASK 0x0000FF00U #define STM32_DMA2_STREAMS_MASK 0x0000FF00U
#if STM32_DMA_SUPPORTS_DMAMUX == TRUE #if STM32_DMA_SUPPORTS_DMAMUX == TRUE
#define DMA1_CH0_VARIANT DMAMUX1_Channel0 #define DMA1_CH0_VARIANT DMAMUX1_Channel0

2
os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c
View File

@ -252,7 +252,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
done by the DMA.*/ done by the DMA.*/
switch (I2C_EV_MASK & (event | (regSR2 << 16))) { switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
case I2C_EV5_MASTER_MODE_SELECT: case I2C_EV5_MASTER_MODE_SELECT:
if ((i2cp->addr >> 8) > 0) { if ((i2cp->addr >> 8) > 0) {
/* 10-bit address: 1 1 1 1 0 X X R/W */ /* 10-bit address: 1 1 1 1 0 X X R/W */
dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr); dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr);
} else { } else {

20
os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c
View File

@ -50,7 +50,7 @@
#if 0 #if 0
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -113,7 +113,7 @@ I2CDriver I2CD4;
static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) { static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -133,7 +133,7 @@ static inline void i2c_lld_start_rx_dma(I2CDriver *i2cp) {
static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) { static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -153,7 +153,7 @@ static inline void i2c_lld_start_tx_dma(I2CDriver *i2cp) {
static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) { static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -173,7 +173,7 @@ static inline void i2c_lld_stop_rx_dma(I2CDriver *i2cp) {
static inline void i2c_lld_stop_tx_dma(I2CDriver *i2cp) { static inline void i2c_lld_stop_tx_dma(I2CDriver *i2cp) {
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -797,7 +797,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_DMA == TRUE #if STM32_I2C_USE_DMA == TRUE
/* Common DMA modes.*/ /* Common DMA modes.*/
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -928,7 +928,7 @@ void i2c_lld_start(I2CDriver *i2cp) {
#if STM32_I2C_USE_DMA == TRUE #if STM32_I2C_USE_DMA == TRUE
/* I2C registers pointed by the DMA.*/ /* I2C registers pointed by the DMA.*/
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -977,7 +977,7 @@ void i2c_lld_stop(I2CDriver *i2cp) {
i2c_lld_abort_operation(i2cp); i2c_lld_abort_operation(i2cp);
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -1062,7 +1062,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
#if STM32_I2C_USE_DMA == TRUE #if STM32_I2C_USE_DMA == TRUE
/* RX DMA setup.*/ /* RX DMA setup.*/
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {
@ -1185,7 +1185,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
#if STM32_I2C_USE_DMA == TRUE #if STM32_I2C_USE_DMA == TRUE
/* TX and RX DMA setup.*/ /* TX and RX DMA setup.*/
#if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_DMA_REQUIRED) && defined(STM32_I2C_BDMA_REQUIRED)
if(i2cp->is_bdma) if (i2cp->is_bdma)
#endif #endif
#if defined(STM32_I2C_BDMA_REQUIRED) #if defined(STM32_I2C_BDMA_REQUIRED)
{ {

2
os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c
View File

@ -320,7 +320,7 @@ void mac_lld_start(MACDriver *macp) {
rccEnableETH(true); rccEnableETH(true);
#if defined(STM32_MAC_DMABMR_SR) #if defined(STM32_MAC_DMABMR_SR)
ETH->DMABMR |= ETH_DMABMR_SR; ETH->DMABMR |= ETH_DMABMR_SR;
while(ETH->DMABMR & ETH_DMABMR_SR) while (ETH->DMABMR & ETH_DMABMR_SR)
; ;
#endif #endif

2
os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c
View File

@ -260,7 +260,7 @@ static void otg_fifo_read_to_buffer(volatile uint32_t *fifop,
size_t i = 0; size_t i = 0;
while (i < n) { while (i < n) {
if ((i & 3) == 0){ if ((i & 3) == 0) {
w = *fifop; w = *fifop;
} }
if (i < max) { if (i < max) {

2
os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
View File

@ -556,7 +556,7 @@ struct USBDriver {
* @notapi * @notapi
*/ */
#define usb_lld_wakeup_host(usbp) \ #define usb_lld_wakeup_host(usbp) \
do{ \ do { \
(usbp)->otg->DCTL |= DCTL_RWUSIG; \ (usbp)->otg->DCTL |= DCTL_RWUSIG; \
osalThreadSleepMilliseconds(STM32_USB_HOST_WAKEUP_DURATION); \ osalThreadSleepMilliseconds(STM32_USB_HOST_WAKEUP_DURATION); \
(usbp)->otg->DCTL &= ~DCTL_RWUSIG; \ (usbp)->otg->DCTL &= ~DCTL_RWUSIG; \

2
os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c
View File

@ -130,7 +130,7 @@ static void rtc_decode(uint32_t tv_sec,
RTCDateTime *timespec) { RTCDateTime *timespec) {
struct tm tim; struct tm tim;
struct tm *t; struct tm *t;
const time_t time = tv_sec; /* Copy with implicit type conversion.*/ const time_t time = tv_sec; /* Copy with implicit type conversion.*/
/* If the conversion is successful the function returns a pointer /* If the conversion is successful the function returns a pointer
to the object the result was written into.*/ to the object the result was written into.*/

2
os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
View File

@ -647,7 +647,7 @@ bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
uint8_t cmd, uint32_t arg) { uint8_t cmd, uint32_t arg) {
uint32_t resp[1]; uint32_t resp[1];
if(sdc_lld_prepare_read_bytes(sdcp, buf, bytes)) if (sdc_lld_prepare_read_bytes(sdcp, buf, bytes))
goto error; goto error;
if (sdc_lld_send_cmd_short_crc(sdcp, cmd, arg, resp) if (sdc_lld_send_cmd_short_crc(sdcp, cmd, arg, resp)

16
os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
View File

@ -606,7 +606,7 @@ void spi_lld_start(SPIDriver *spip) {
/* DMA setup.*/ /* DMA setup.*/
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma) if (spip->is_bdma)
#endif #endif
#if defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_BDMA_REQUIRED)
{ {
@ -628,7 +628,7 @@ void spi_lld_start(SPIDriver *spip) {
/* Configuration-specific DMA setup.*/ /* Configuration-specific DMA setup.*/
dsize = (spip->config->cfg1 & SPI_CFG1_DSIZE_Msk) + 1U; dsize = (spip->config->cfg1 & SPI_CFG1_DSIZE_Msk) + 1U;
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma) if (spip->is_bdma)
#endif #endif
#if defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_BDMA_REQUIRED)
{ {
@ -733,7 +733,7 @@ void spi_lld_stop(SPIDriver *spip) {
spip->spi->CFG2 = 0U; spip->spi->CFG2 = 0U;
spip->spi->IER = 0U; spip->spi->IER = 0U;
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma) if (spip->is_bdma)
#endif #endif
#if defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_BDMA_REQUIRED)
{ {
@ -821,7 +821,7 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size"); osalDbgAssert(n < 65536, "unsupported DMA transfer size");
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma) if (spip->is_bdma)
#endif #endif
#if defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_BDMA_REQUIRED)
{ {
@ -879,7 +879,7 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
osalDbgAssert(n < 65536, "unsupported DMA transfer size"); osalDbgAssert(n < 65536, "unsupported DMA transfer size");
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma) if (spip->is_bdma)
#endif #endif
#if defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_BDMA_REQUIRED)
{ {
@ -934,7 +934,7 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size"); osalDbgAssert(n < 65536, "unsupported DMA transfer size");
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma) if (spip->is_bdma)
#endif #endif
#if defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_BDMA_REQUIRED)
{ {
@ -989,7 +989,7 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size"); osalDbgAssert(n < 65536, "unsupported DMA transfer size");
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma) if (spip->is_bdma)
#endif #endif
#if defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_BDMA_REQUIRED)
{ {
@ -1041,7 +1041,7 @@ void spi_lld_abort(SPIDriver *spip) {
/* Stopping DMAs.*/ /* Stopping DMAs.*/
#if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
if(spip->is_bdma) if (spip->is_bdma)
#endif #endif
#if defined(STM32_SPI_BDMA_REQUIRED) #if defined(STM32_SPI_BDMA_REQUIRED)
{ {

4
os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
View File

@ -184,7 +184,7 @@ static uartflags_t translate_errors(uint16_t sr) {
*/ */
static void uart_enter_rx_idle_loop(UARTDriver *uartp) { static void uart_enter_rx_idle_loop(UARTDriver *uartp) {
uint32_t mode; uint32_t mode;
/* RX DMA channel preparation, if the char callback is defined then the /* RX DMA channel preparation, if the char callback is defined then the
TCIE interrupt is enabled too.*/ TCIE interrupt is enabled too.*/
if (uartp->config->rxchar_cb == NULL) if (uartp->config->rxchar_cb == NULL)
@ -208,7 +208,7 @@ static void usart_stop(UARTDriver *uartp) {
/* Stops RX and TX DMA channels.*/ /* Stops RX and TX DMA channels.*/
dmaStreamDisable(uartp->dmarx); dmaStreamDisable(uartp->dmarx);
dmaStreamDisable(uartp->dmatx); dmaStreamDisable(uartp->dmatx);
/* Stops USART operations.*/ /* Stops USART operations.*/
uartp->usart->CR1 = 0; uartp->usart->CR1 = 0;
uartp->usart->CR2 = 0; uartp->usart->CR2 = 0;

2
os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h
View File

@ -273,7 +273,7 @@
#error "USART3 not present in the selected device" #error "USART3 not present in the selected device"
#endif #endif
#if STM32_UART_USE_UART4 #if STM32_UART_USE_UART4
#if !STM32_HAS_UART4 #if !STM32_HAS_UART4
#error "UART4 not present in the selected device" #error "UART4 not present in the selected device"
#endif #endif

4
os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
View File

@ -235,8 +235,8 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
/* Baud rate setting.*/ /* Baud rate setting.*/
#if STM32_SERIAL_USE_LPUART1 #if STM32_SERIAL_USE_LPUART1
if ( sdp == &LPSD1 ) { if (sdp == &LPSD1) {
fck = (uint32_t)(((uint64_t)sdp->clock * 256 ) / config->speed); fck = (uint32_t)(((uint64_t)sdp->clock * 256) / config->speed);
} }
else else
#endif #endif

6
os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
View File

@ -214,7 +214,7 @@ static uartflags_t translate_errors(uint32_t isr) {
*/ */
static void uart_enter_rx_idle_loop(UARTDriver *uartp) { static void uart_enter_rx_idle_loop(UARTDriver *uartp) {
uint32_t mode; uint32_t mode;
/* RX DMA channel preparation, if the char callback is defined then the /* RX DMA channel preparation, if the char callback is defined then the
TCIE interrupt is enabled too.*/ TCIE interrupt is enabled too.*/
if (uartp->config->rxchar_cb == NULL) if (uartp->config->rxchar_cb == NULL)
@ -238,7 +238,7 @@ static void usart_stop(UARTDriver *uartp) {
/* Stops RX and TX DMA channels.*/ /* Stops RX and TX DMA channels.*/
dmaStreamDisable(uartp->dmarx); dmaStreamDisable(uartp->dmarx);
dmaStreamDisable(uartp->dmatx); dmaStreamDisable(uartp->dmatx);
/* Stops USART operations.*/ /* Stops USART operations.*/
uartp->usart->CR1 = 0; uartp->usart->CR1 = 0;
uartp->usart->CR2 = 0; uartp->usart->CR2 = 0;
@ -357,7 +357,7 @@ static void serve_usart_irq(UARTDriver *uartp) {
uint32_t isr; uint32_t isr;
USART_TypeDef *u = uartp->usart; USART_TypeDef *u = uartp->usart;
uint32_t cr1 = u->CR1; uint32_t cr1 = u->CR1;
/* Reading and clearing status.*/ /* Reading and clearing status.*/
isr = u->ISR; isr = u->ISR;
u->ICR = isr; u->ICR = isr;

2
os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.h
View File

@ -465,7 +465,7 @@ struct USBDriver {
* @notapi * @notapi
*/ */
#define usb_lld_wakeup_host(usbp) \ #define usb_lld_wakeup_host(usbp) \
do{ \ do { \
STM32_USB->CNTR |= USB_CNTR_RESUME; \ STM32_USB->CNTR |= USB_CNTR_RESUME; \
osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION); \ osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION); \
STM32_USB->CNTR &= ~USB_CNTR_RESUME; \ STM32_USB->CNTR &= ~USB_CNTR_RESUME; \

2
os/hal/ports/STM32/STM32F0xx/hal_lld.c
View File

@ -60,7 +60,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;

6
os/hal/ports/STM32/STM32F1xx/hal_efl_lld.c
View File

@ -67,7 +67,6 @@ static const flash_descriptor_t efl_lld_descriptor = {
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
static inline void stm32_flash_lock(EFlashDriver *eflp) { static inline void stm32_flash_lock(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_LOCK; eflp->flash->CR |= FLASH_CR_LOCK;
@ -305,8 +304,7 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
break; break;
} }
/* Check for flash error.*/ /* Check for flash error.*/
if(address[0] != line.hw[0]) if (address[0] != line.hw[0]) {
{
err = FLASH_ERROR_PROGRAM; err = FLASH_ERROR_PROGRAM;
break; break;
} }
@ -400,7 +398,7 @@ flash_error_t efl_lld_start_erase_sector(void *instance,
* *
* @api * @api
*/ */
flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time){ flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time) {
EFlashDriver *devp = (EFlashDriver *)instance; EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err; flash_error_t err;

2
os/hal/ports/STM32/STM32F1xx/hal_lld.c
View File

@ -58,7 +58,7 @@ static void hal_lld_backup_domain_init(void) {
#if HAL_USE_RTC #if HAL_USE_RTC
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;

8
os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h
View File

@ -404,10 +404,10 @@
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
(((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \ (((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
(STM32_MCOSEL == STM32_MCOSEL_PLL2) || \ (STM32_MCOSEL == STM32_MCOSEL_PLL2) || \
(STM32_MCOSEL == STM32_MCOSEL_PLL3) || \ (STM32_MCOSEL == STM32_MCOSEL_PLL3) || \
(STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2)) && \ (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2)) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
(STM32_MCOSEL == STM32_MCOSEL_XT1) (STM32_MCOSEL == STM32_MCOSEL_XT1)
#error "HSE not enabled, required by STM32_MCOSEL" #error "HSE not enabled, required by STM32_MCOSEL"
#endif #endif

2
os/hal/ports/STM32/STM32F37x/hal_adc_lld.c
View File

@ -535,7 +535,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
} }
dmaStreamSetMemory0(adcp->dmastp, adcp->samples); dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
dmaStreamSetTransactionSize(adcp->dmastp, dmaStreamSetTransactionSize(adcp->dmastp,
(uint32_t)grpp->num_channels * (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth); (uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode); dmaStreamSetMode(adcp->dmastp, mode);
dmaStreamEnable(adcp->dmastp); dmaStreamEnable(adcp->dmastp);

2
os/hal/ports/STM32/STM32F37x/hal_lld.c
View File

@ -57,7 +57,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;

1
os/hal/ports/STM32/STM32F37x/stm32_rcc.h
View File

@ -742,7 +742,6 @@
*/ */
#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST) #define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
/** /**
* @brief Enables the TIM14 peripheral clock. * @brief Enables the TIM14 peripheral clock.
* *

2
os/hal/ports/STM32/STM32F3xx/hal_lld.c
View File

@ -57,7 +57,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;

2
os/hal/ports/STM32/STM32F4xx/hal_lld.c
View File

@ -184,7 +184,7 @@ void stm32_clock_init(void) {
/* Registers finally cleared to reset values.*/ /* Registers finally cleared to reset values.*/
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */ RCC->CFGR = 0; /* CFGR reset value. */
#if STM32_HSE_ENABLED #if STM32_HSE_ENABLED
/* HSE activation.*/ /* HSE activation.*/
#if defined(STM32_HSE_BYPASS) #if defined(STM32_HSE_BYPASS)

9
os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
View File

@ -32,7 +32,7 @@
* Foundation line. * Foundation line.
* - STM32F401xx, STM32F410xx, STM32F411xx, STM32F412xx * - STM32F401xx, STM32F410xx, STM32F411xx, STM32F412xx
* for High-performance STM32F4 devices of Access line. * for High-performance STM32F4 devices of Access line.
* - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx, * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx,
* STM32F479xx for High-performance STM32F4 devices of Advanced line. * STM32F479xx for High-performance STM32F4 devices of Advanced line.
* . * .
* *
@ -784,7 +784,7 @@
* @brief PLLI2SN multiplier value. * @brief PLLI2SN multiplier value.
* @note The allowed values are 192..432, except for * @note The allowed values are 192..432, except for
* STM32F446 where values are 50...432. * STM32F446 where values are 50...432.
* @note The default value is calculated for a 96MHz I2S clock * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock. * output from an external 8MHz HSE clock.
*/ */
#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
@ -794,7 +794,7 @@
/** /**
* @brief PLLI2SM divider value. * @brief PLLI2SM divider value.
* @note The allowed values are 2..63. * @note The allowed values are 2..63.
* @note The default value is calculated for a 96MHz I2S clock * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock. * output from an external 8MHz HSE clock.
*/ */
#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
@ -804,7 +804,7 @@
/** /**
* @brief PLLI2SR divider value. * @brief PLLI2SR divider value.
* @note The allowed values are 2..7. * @note The allowed values are 2..7.
* @note The default value is calculated for a 96MHz I2S clock * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock. * output from an external 8MHz HSE clock.
*/ */
#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
@ -1178,7 +1178,6 @@
#error "invalid VDD voltage specified" #error "invalid VDD voltage specified"
#endif #endif
#elif defined(STM32F401xx) #elif defined(STM32F401xx)
#if (STM32_VDD >= 270) && (STM32_VDD <= 360) #if (STM32_VDD >= 270) && (STM32_VDD <= 360)
#define STM32_0WS_THRESHOLD 30000000 #define STM32_0WS_THRESHOLD 30000000

6
os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
View File

@ -508,7 +508,7 @@
/** /**
* @brief PLLI2SM divider value. * @brief PLLI2SM divider value.
* @note The allowed values are 2..63. * @note The allowed values are 2..63.
* @note The default value is calculated for a 96MHz I2S clock * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock. * output from an external 8MHz HSE clock.
*/ */
#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
@ -519,7 +519,7 @@
* @brief PLLI2SN multiplier value. * @brief PLLI2SN multiplier value.
* @note The allowed values are 192..432, except for * @note The allowed values are 192..432, except for
* STM32F446 where values are 50...432. * STM32F446 where values are 50...432.
* @note The default value is calculated for a 96MHz I2S clock * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock. * output from an external 8MHz HSE clock.
*/ */
#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
@ -529,7 +529,7 @@
/** /**
* @brief PLLI2SR divider value. * @brief PLLI2SR divider value.
* @note The allowed values are 2..7. * @note The allowed values are 2..7.
* @note The default value is calculated for a 96MHz I2S clock * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock. * output from an external 8MHz HSE clock.
*/ */
#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)

2
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -949,7 +949,7 @@
#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK #elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
#define STM32_PLLCLKIN 0 #define STM32_PLLCLKIN 0
#else #else
#error "invalid STM32_PLLSRC value specified" #error "invalid STM32_PLLSRC value specified"
#endif #endif

6
os/hal/ports/STM32/STM32L0xx/hal_lld.c
View File

@ -55,7 +55,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->CSR |= RCC_CSR_RTCRST; RCC->CSR |= RCC_CSR_RTCRST;
RCC->CSR &= ~RCC_CSR_RTCRST; RCC->CSR &= ~RCC_CSR_RTCRST;
@ -64,8 +64,8 @@ static void hal_lld_backup_domain_init(void) {
/* If enabled then the LSE is started.*/ /* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED #if STM32_LSE_ENABLED
RCC->CSR |= RCC_CSR_LSEON; RCC->CSR |= RCC_CSR_LSEON;
while ((RCC->CSR & RCC_CSR_LSERDY) == 0) while ((RCC->CSR & RCC_CSR_LSERDY) == 0) {
; /* Waits until LSE is stable. */ ; /* Waits until LSE is stable. */
#endif #endif
#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK

2
os/hal/ports/STM32/STM32L0xx/hal_lld.h
View File

@ -26,7 +26,7 @@
* - STM32_HSE_BYPASS (optionally). * - STM32_HSE_BYPASS (optionally).
* . * .
* One of the following macros must also be defined: * One of the following macros must also be defined:
* - STM32L011xx, STM32L031xx, * - STM32L011xx, STM32L031xx,
* STM32L051xx, STM32L052xx, STM32L053xx, * STM32L051xx, STM32L052xx, STM32L053xx,
* STM32L061xx, STM32L062xx, STM32L063xx, * STM32L061xx, STM32L062xx, STM32L063xx,
* STM32L071xx, STM32L072xx, STM32L073xx for ultra-low-power MCUs. * STM32L071xx, STM32L072xx, STM32L073xx for ultra-low-power MCUs.

2
os/hal/ports/STM32/STM32L1xx/hal_lld.c
View File

@ -57,7 +57,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->CSR |= RCC_CSR_RTCRST; RCC->CSR |= RCC_CSR_RTCRST;
RCC->CSR &= ~RCC_CSR_RTCRST; RCC->CSR &= ~RCC_CSR_RTCRST;

3
os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.c
View File

@ -114,7 +114,6 @@ static const EFlashConfig efl_lld_config = {
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
static inline void stm32_flash_lock(EFlashDriver *eflp) { static inline void stm32_flash_lock(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_LOCK; eflp->flash->CR |= FLASH_CR_LOCK;
@ -511,7 +510,7 @@ flash_error_t efl_lld_start_erase_sector(void *instance,
* *
* @api * @api
*/ */
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec){ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
EFlashDriver *devp = (EFlashDriver *)instance; EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err; flash_error_t err;

2
os/hal/ports/STM32/STM32L4xx+/hal_lld.h
View File

@ -1314,7 +1314,7 @@
#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK #elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
#define STM32_PLLCLKIN 0 #define STM32_PLLCLKIN 0
#else #else
#error "invalid STM32_PLLSRC value specified" #error "invalid STM32_PLLSRC value specified"
#endif #endif

3
os/hal/ports/STM32/STM32L4xx/hal_efl_lld.c
View File

@ -78,7 +78,6 @@ static const flash_descriptor_t efl_lld_descriptor = {
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
static inline void stm32_flash_lock(EFlashDriver *eflp) { static inline void stm32_flash_lock(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_LOCK; eflp->flash->CR |= FLASH_CR_LOCK;
@ -447,7 +446,7 @@ flash_error_t efl_lld_start_erase_sector(void *instance,
* *
* @api * @api
*/ */
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec){ flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
EFlashDriver *devp = (EFlashDriver *)instance; EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err; flash_error_t err;

2
os/hal/ports/STM32/STM32L4xx/hal_lld.h
View File

@ -1233,7 +1233,7 @@
#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK #elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
#define STM32_PLLCLKIN 0 #define STM32_PLLCLKIN 0
#else #else
#error "invalid STM32_PLLSRC value specified" #error "invalid STM32_PLLSRC value specified"
#endif #endif

2
tools/style/style_hal.sh
View File

@ -2,4 +2,6 @@
find ../../os/hal/include -name "*.[ch]" -exec perl stylecheck.pl "{}" \; find ../../os/hal/include -name "*.[ch]" -exec perl stylecheck.pl "{}" \;
find ../../os/hal/src -name "*.[ch]" -exec perl stylecheck.pl "{}" \; find ../../os/hal/src -name "*.[ch]" -exec perl stylecheck.pl "{}" \;
find ../../os/hal/templates -name "*.[ch]" -exec perl stylecheck.pl "{}" \; find ../../os/hal/templates -name "*.[ch]" -exec perl stylecheck.pl "{}" \;
find ../../os/hal/osal -name "*.[ch]" -exec perl stylecheck.pl "{}" \;
find ../../os/hal/ports/STM32 -name "*.[ch]" -exec perl stylecheck.pl "{}" \;

4
tools/style/stylecheck.pl
View File

@ -115,7 +115,7 @@ foreach my $line (@c_source) {
#**************************************************************************** #****************************************************************************
# Check on loose semicolons. # Check on loose semicolons.
if ($line =~ /\s;/) { if ($line =~ /\S\s;/) {
style "detected loose semicolon"; style "detected loose semicolon";
} }
@ -145,7 +145,7 @@ foreach my $line (@c_source) {
if ($line =~ /\(\s+/) { if ($line =~ /\(\s+/) {
style "detected loose \"(\""; style "detected loose \"(\"";
} }
if ($line =~ /\s+\)/) { if ($line =~ /\S\s+\)/) {
style "detected loose \")\""; style "detected loose \")\"";
} }