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Addded pin lock capability to STM32 GPIOv3 driver and board files. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8476 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2015-11-13 09:52:26 +00:00
parent db45dfbe9e
commit 4fb6d9644e
6 changed files with 1970 additions and 1482 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
os/hal/boards/ST_NUCLEO_L476RG/board.c
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@ -25,35 +25,43 @@
const PALConfig pal_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
VAL_GPIOA_LOCKR},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
VAL_GPIOB_LOCKR},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
VAL_GPIOC_LOCKR},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
VAL_GPIOD_LOCKR},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
VAL_GPIOE_LOCKR},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
VAL_GPIOF_LOCKR},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
VAL_GPIOG_LOCKR},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
VAL_GPIOH_LOCKR},
#endif
};
#endif

981
os/hal/boards/ST_NUCLEO_L476RG/board.h
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File diff suppressed because it is too large Load Diff

2384
os/hal/boards/ST_NUCLEO_L476RG/cfg/board.chcfg
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File diff suppressed because it is too large Load Diff

42
os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c
View File

@ -156,7 +156,6 @@ void _pal_lld_init(const PALConfig *config) {
*
* @notapi
*/
#if 1
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode) {
@ -167,7 +166,7 @@ void _pal_lld_setgroupmode(ioportid_t port,
uint32_t pupdr = (mode & PAL_STM32_PUDR_MASK) >> 5;
uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
uint32_t bit = 0;
while (TRUE) {
while (true) {
if ((mask & 1) != 0) {
uint32_t altrmask, m1, m2, m4;
@ -194,45 +193,6 @@ void _pal_lld_setgroupmode(ioportid_t port,
bit++;
}
}
#else
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode) {
uint32_t afrm, moderm, pupdrm, otyperm, ospeedrm;
uint32_t m1 = (uint32_t)mask;
uint32_t m2 = 0;
uint32_t m4l = 0;
uint32_t m4h = 0;
uint32_t bit = 0;
do {
if ((mask & 1) != 0) {
m2 |= 3 << bit;
if (bit < 16)
m4l |= 15 << ((bit & 14) * 2);
else
m4h |= 15 << ((bit & 14) * 2);
}
bit += 2;
mask >>= 1;
} while (mask);
afrm = ((mode & PAL_STM32_ALTERNATE_MASK) >> 7) * 0x1111;
port->AFRL = (port->AFRL & ~m4l) | (afrm & m4l);
port->AFRH = (port->AFRH & ~m4h) | (afrm & m4h);
ospeedrm = ((mode & PAL_STM32_OSPEED_MASK) >> 3) * 0x5555;
port->OSPEEDR = (port->OSPEEDR & ~m2) | (ospeedrm & m2);
otyperm = ((mode & PAL_STM32_OTYPE_MASK) >> 2) * 0xffff;
port->OTYPER = (port->OTYPER & ~m1) | (otyperm & m1);
pupdrm = ((mode & PAL_STM32_PUDR_MASK) >> 5) * 0x5555;
port->PUPDR = (port->PUPDR & ~m2) | (pupdrm & m2);
moderm = ((mode & PAL_STM32_MODE_MASK) >> 0) * 0x5555;
port->MODER = (port->MODER & ~m2) | (moderm & m2);
}
#endif
#endif /* HAL_USE_PAL */

6
os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c
View File

@ -53,12 +53,14 @@
static void initgpio(stm32_gpio_t *gpiop, const stm32_gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->ASCR = config->ascr;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
gpiop->LOCKR = config->lockr;
}
/*===========================================================================*/
@ -147,8 +149,9 @@ void _pal_lld_setgroupmode(ioportid_t port,
uint32_t pupdr = (mode & PAL_STM32_PUDR_MASK) >> 5;
uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
uint32_t ascr = (mode & PAL_STM32_ASCR_MASK) >> 11;
uint32_t lockr = (mode & PAL_STM32_LOCKR_MASK) >> 12;
uint32_t bit = 0;
while (TRUE) {
while (true) {
if ((mask & 1) != 0) {
uint32_t altrmask, m1, m2, m4;
@ -165,6 +168,7 @@ void _pal_lld_setgroupmode(ioportid_t port,
port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
port->PUPDR = (port->PUPDR & ~m2) | pupdr;
port->MODER = (port->MODER & ~m2) | moder;
port->LOCKR = (port->LOCKR & ~m1) | lockr;
}
mask >>= 1;
if (!mask)

15
os/hal/ports/STM32/LLD/GPIOv3/pal_lld.h
View File

@ -72,6 +72,10 @@
#define PAL_STM32_ASCR_OFF (0U << 11U)
#define PAL_STM32_ASCR_ON (1U << 11U)
#define PAL_STM32_LOCKR_MASK (1U << 12U)
#define PAL_STM32_LOCKR_OFF (0U << 12U)
#define PAL_STM32_LOCKR_ON (1U << 12U)
/**
* @brief Alternate function.
*
@ -86,15 +90,16 @@
* @{
*/
/**
* @brief This mode is implemented as input.
* @brief Implemented as input.
*/
#define PAL_MODE_RESET PAL_STM32_MODE_INPUT
/**
* @brief This mode is implemented as analog with analog switch disabled.
* @brief Implemented as analog with analog switch disabled and lock.
*/
#define PAL_MODE_UNCONNECTED (PAL_STM32_MODE_ANALOG | \
PAL_STM32_ASCR_OFF)
PAL_STM32_ASCR_OFF | \
PAL_STM32_LOCKR_ON)
/**
* @brief Regular input high-Z pad.
@ -235,7 +240,7 @@ typedef struct {
uint16_t clear;
} H;
} BSRR;
volatile uint32_t LCKR;
volatile uint32_t LOCKR;
volatile uint32_t AFRL;
volatile uint32_t AFRH;
volatile uint32_t BRR;
@ -262,6 +267,8 @@ typedef struct {
uint32_t afrh;
/** Initial value for ASCR register.*/
uint32_t ascr;
/** Initial value for LOCKR register.*/
uint32_t lockr;
} stm32_gpio_setup_t;
/**