From 4fcf7891747a00b5df303854562c537145c9afe1 Mon Sep 17 00:00:00 2001 From: Andrey Gusakov Date: Tue, 30 May 2023 00:23:50 +0300 Subject: [PATCH] Artery AT32F4xx port: update clocks --- os/common/ext/Artery/AT32F4xx/at32f435xx.h | 49 +-- os/hal/ports/AT32/AT32F4xx/hal_lld.c | 25 +- os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h | 469 ++------------------- 3 files changed, 37 insertions(+), 506 deletions(-) diff --git a/os/common/ext/Artery/AT32F4xx/at32f435xx.h b/os/common/ext/Artery/AT32F4xx/at32f435xx.h index 50315d381..521cbd313 100644 --- a/os/common/ext/Artery/AT32F4xx/at32f435xx.h +++ b/os/common/ext/Artery/AT32F4xx/at32f435xx.h @@ -690,10 +690,10 @@ typedef struct __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ - __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + uint32_t RESERVED7[8]; /*!< Reserved, 0x80-0x9C */ + __IO uint32_t MISC1; /*!< Additional register 1 Address offset: 0xA0 */ + __IO uint32_t MISC2; /*!< Additional register 2 Address offset: 0xA4 */ + } RCC_TypeDef; /** @@ -10441,8 +10441,8 @@ typedef struct #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk -#define RCC_CR_HSITRIM_Pos (3U) -#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ +#define RCC_CR_HSITRIM_Pos (2U) +#define RCC_CR_HSITRIM_Msk (0x3FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ @@ -10479,40 +10479,16 @@ typedef struct #define RCC_CR_PLLON RCC_CR_PLLON_Msk #define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ -#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) - */ -#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */ - -#define RCC_CR_PLLI2SON_Pos (26U) -#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */ -#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk -#define RCC_CR_PLLI2SRDY_Pos (27U) -#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */ -#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) - */ -#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */ - -#define RCC_CR_PLLSAION_Pos (28U) -#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */ -#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk -#define RCC_CR_PLLSAIRDY_Pos (29U) -#define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */ -#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /******************** Bit definition for RCC_PLLCFGR register ***************/ #define RCC_PLLCFGR_PLLM_Pos (0U) -#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */ +#define RCC_PLLCFGR_PLLM_Msk (0xFU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000000F */ #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */ #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */ #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */ #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */ -#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ -#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ #define RCC_PLLCFGR_PLLN_Pos (6U) #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */ @@ -10541,15 +10517,6 @@ typedef struct #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U -#define RCC_PLLCFGR_PLLQ_Pos (24U) -#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */ -#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk -#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */ -#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */ -#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */ -#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */ - - /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ #define RCC_CFGR_SW_Pos (0U) diff --git a/os/hal/ports/AT32/AT32F4xx/hal_lld.c b/os/hal/ports/AT32/AT32F4xx/hal_lld.c index 65bff6e54..840bd913c 100644 --- a/os/hal/ports/AT32/AT32F4xx/hal_lld.c +++ b/os/hal/ports/AT32/AT32F4xx/hal_lld.c @@ -207,8 +207,7 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLL /* PLL activation.*/ - RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | - STM32_PLLM; + RCC->PLLCFGR = STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM; RCC->CR |= RCC_CR_PLLON; /* Artery */ @@ -236,28 +235,6 @@ void stm32_clock_init(void) { ; #endif /* STM32_ACTIVATE_PLL */ -#if STM32_ACTIVATE_PLLI2S - /* PLLI2S activation.*/ - RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP | - STM32_PLLI2SSRC | STM32_PLLI2SQ | STM32_PLLI2SM; - RCC->CR |= RCC_CR_PLLI2SON; - - /* Waiting for PLL lock.*/ - while (!(RCC->CR & RCC_CR_PLLI2SRDY)) - ; -#endif /* STM32_ACTIVATE_PLLI2S */ - -#if STM32_ACTIVATE_PLLSAI - /* PLLSAI activation.*/ - RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP | - STM32_PLLSAIQ | STM32_PLLSAIM; - RCC->CR |= RCC_CR_PLLSAION; - - /* Waiting for PLL lock.*/ - while (!(RCC->CR & RCC_CR_PLLSAIRDY)) - ; -#endif /* STM32_ACTIVATE_PLLSAI */ - /* Other clock-related settings (dividers, MCO etc).*/ #if !defined(STM32F413xx) RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | diff --git a/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h b/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h index 93375adf4..907e945bc 100644 --- a/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h +++ b/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h @@ -72,17 +72,17 @@ /** * @brief Absolute maximum system clock. */ -#define STM32_SYSCLK_MAX 180000000 +#define STM32_SYSCLK_MAX 288000000 /** * @brief Maximum HSE clock frequency. */ -#define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_MAX 25000000 /** * @brief Maximum HSE clock frequency using an external source. */ -#define STM32_HSECLK_BYP_MAX 50000000 +#define STM32_HSECLK_BYP_MAX 25000000 /** * @brief Minimum HSE clock frequency. @@ -112,32 +112,32 @@ /** * @brief Maximum PLLs input clock frequency. */ -#define STM32_PLLIN_MAX 2100000 +#define STM32_PLLIN_MAX 16000000 /** * @brief Minimum PLLs input clock frequency. */ -#define STM32_PLLIN_MIN 950000 +#define STM32_PLLIN_MIN 2000000 /** * @brief Maximum PLLs VCO clock frequency. */ -#define STM32_PLLVCO_MAX 432000000 +#define STM32_PLLVCO_MAX 1200000000 /** * @brief Minimum PLLs VCO clock frequency. */ -#define STM32_PLLVCO_MIN 192000000 +#define STM32_PLLVCO_MIN 500000000 /** * @brief Maximum PLL output clock frequency. */ -#define STM32_PLLOUT_MAX 180000000 +#define STM32_PLLOUT_MAX 288000000 /** * @brief Minimum PLL output clock frequency. */ -#define STM32_PLLOUT_MIN 24000000 +#define STM32_PLLOUT_MIN 16000000 /** * @brief Maximum PLLI2S output clock frequency. @@ -196,11 +196,11 @@ * @name RCC_PLLCFGR register bits definitions * @{ */ -#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ -#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ -#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ -#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ -#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ +#define STM32_PLLP_MASK (7 << 16) /**< PLLP mask. */ +#define STM32_PLLP_DIV4 (2 << 16) /**< PLL clock divided by 2. */ +#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 4. */ +#define STM32_PLLP_DIV16 (4 << 16) /**< PLL clock divided by 6. */ +#define STM32_PLLP_DIV32 (5 << 16) /**< PLL clock divided by 8. */ #define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ @@ -331,18 +331,6 @@ #define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/ #define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */ -#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */ -#define STM32_SAI1SEL_PLLSAI (0 << 20) /**< SAI1 source is PLLSAI. */ -#define STM32_SAI1SEL_PLLI2S (1 << 20) /**< SAI1 source is PLLI2S. */ -#define STM32_SAI1SEL_PLLR (2 << 20) /**< SAI1 source is PLLR. */ -#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/ - -#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */ -#define STM32_SAI2SEL_PLLSAI (0 << 22) /**< SAI2 source is PLLSAI. */ -#define STM32_SAI2SEL_PLLI2S (1 << 22) /**< SAI2 source is PLLI2S. */ -#define STM32_SAI2SEL_PLLR (2 << 22) /**< SAI2 source is PLLR. */ -#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/ - #define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */ #define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */ #define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */ @@ -479,12 +467,11 @@ #define STM32_SW STM32_SW_PLL #endif -#if defined(STM32F4XX) || defined(__DOXYGEN__) /** * @brief Clock source for the PLLs. * @note This setting has only effect if the PLL is selected as the * system clock source. - * @note The default value is calculated for a 168MHz system clock from + * @note The default value is calculated for a 120MHz system clock from * an external 8MHz HSE clock. */ #if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) @@ -493,107 +480,34 @@ /** * @brief PLLM divider value. - * @note The allowed values are 2..63. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLM_VALUE 8 -#endif - -/** - * @brief PLLN multiplier value. - * @note The allowed values are 192..432. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 336 -#endif - -/** - * @brief PLLP divider value. - * @note The allowed values are 2, 4, 6, 8. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLP_VALUE 2 -#endif - -/** - * @brief PLLQ multiplier value. - * @note The allowed values are 2..15. - * @note The default value is calculated for a 168MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLQ_VALUE 7 -#endif - -/** - * @brief PLLR divider value. - * @note The allowed values are 2..7. + * @note The allowed values are 1..15. * @note The default value is calculated for a 96MHz system clock from * an external 8MHz HSE clock. */ -#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLR_VALUE 4 -#endif - -#else /* !defined(STM32F4XX) */ -/** - * @brief Clock source for the PLLs. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLSRC STM32_PLLSRC_HSE -#endif - -/** - * @brief PLLM divider value. - * @note The allowed values are 2..63. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ #if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLM_VALUE 8 +#define STM32_PLLM_VALUE 2 #endif /** * @brief PLLN multiplier value. - * @note The allowed values are 192..432. + * @note The allowed values are 31..500. * @note The default value is calculated for a 120MHz system clock from * an external 8MHz HSE clock. */ #if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 240 +#define STM32_PLLN_VALUE 192 #endif /** * @brief PLLP divider value. - * @note The allowed values are 2, 4, 6, 8. + * @note The allowed values are 4, 8, 16, 32. * @note The default value is calculated for a 120MHz system clock from * an external 8MHz HSE clock. */ #if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLP_VALUE 2 +#define STM32_PLLP_VALUE 8 #endif -/** - * @brief PLLQ multiplier value. - * @note The allowed values are 2..15. - * @note The default value is calculated for a 120MHz system clock from - * an external 8MHz HSE clock. - */ -#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLQ_VALUE 5 -#endif -#endif /* !defined(STM32F4XX) */ - /** * @brief I2S clock source (post-PLL). * @note Not all devices have this setting, it is alternative to @@ -736,28 +650,6 @@ #define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF #endif -/** - * @brief PLLSAIDIVQ divider value (LCD clock divider). - * @note The allowed values are 1..32. - */ -#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAIDIVQ_VALUE 1 -#endif - -/** - * @brief SAI1SEL value (SAI1 clock source). - */ -#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__) -#define STM32_SAI1SEL STM32_SAI1SEL_OFF -#endif - -/** - * @brief SAI2SEL value (SAI2 clock source). - */ -#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__) -#define STM32_SAI2SEL STM32_SAI2SEL_OFF -#endif - /** * @brief TIM prescaler clock source. */ @@ -1210,18 +1102,6 @@ (STM32_PLLSRC == STM32_PLLSRC_HSI) #error "HSI not enabled, required by STM32_I2SSRC" #endif - -#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \ - (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_SAI1SEL" -#endif - -#if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_SAI2SEL" -#endif #endif /* !STM32_HSI_ENABLED */ /* @@ -1327,7 +1207,7 @@ /** * @brief STM32_PLLM field. */ -#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ +#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 15)) || \ defined(__DOXYGEN__) #define STM32_PLLM (STM32_PLLM_VALUE << 0) #else @@ -1367,7 +1247,7 @@ /** * @brief STM32_PLLN field. */ -#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \ +#if ((STM32_PLLN_VALUE >= 31) && (STM32_PLLN_VALUE <= 500)) || \ defined(__DOXYGEN__) #define STM32_PLLN (STM32_PLLN_VALUE << 6) #else @@ -1377,42 +1257,18 @@ /** * @brief STM32_PLLP field. */ -#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLP STM32_PLLP_DIV2 -#elif STM32_PLLP_VALUE == 4 +#if (STM32_PLLP_VALUE == 4) || defined(__DOXYGEN__) #define STM32_PLLP STM32_PLLP_DIV4 -#elif STM32_PLLP_VALUE == 6 -#define STM32_PLLP STM32_PLLP_DIV6 #elif STM32_PLLP_VALUE == 8 #define STM32_PLLP STM32_PLLP_DIV8 +#elif STM32_PLLP_VALUE == 16 +#define STM32_PLLP STM32_PLLP_DIV16 +#elif STM32_PLLP_VALUE == 32 +#define STM32_PLLP STM32_PLLP_DIV32 #else #error "invalid STM32_PLLP_VALUE value specified" #endif -/** - * @brief STM32_PLLQ field. - */ -#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \ - defined(__DOXYGEN__) -#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) -#else -#error "invalid STM32_PLLQ_VALUE value specified" -#endif - -#if defined(STM32F4XX) || defined(__DOXYGEN__) -/** - * @brief STM32_PLLR field. - */ -#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 7)) || \ - defined(__DOXYGEN__) -#define STM32_PLLR (STM32_PLLR_VALUE << 28) -#else -#error "invalid STM32_PLLR_VALUE value specified" -#endif -#else /* !defined(STM32F4XX) */ -#define STM32_PLLR 0 -#endif /* !defined(STM32F4XX) */ - /** * @brief PLL VCO frequency. */ @@ -1586,275 +1442,6 @@ #error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" #endif -/* - * PLLI2S enable check. - */ -#if (STM32_HAS_RCC_PLLI2S && \ - (STM32_CLOCK48_REQUIRED && \ - (STM32_HAS_RCC_CK48MSEL && \ - STM32_RCC_CK48MSEL_USES_I2S && \ - (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \ - (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \ - (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S))) || \ - defined(__DOXYGEN__) - -/** - * @brief PLLI2S activation flag. - */ -#define STM32_ACTIVATE_PLLI2S TRUE -#else -#define STM32_ACTIVATE_PLLI2S FALSE -#endif - -/** - * @brief STM32_PLLI2SM field. - */ -#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SM (STM32_PLLI2SM_VALUE << 0) -#else -#error "invalid STM32_PLLI2SM_VALUE value specified" -#endif - -/** - * @brief STM32_PLLI2SN field. - */ -#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) -#else -#error "invalid STM32_PLLI2SN_VALUE value specified" -#endif - -/** - * @brief STM32_PLLI2SP field. - */ -#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLI2SP STM32_PLLI2SP_DIV2 -#elif STM32_PLLI2SP_VALUE == 4 -#define STM32_PLLI2SP STM32_PLLI2SP_DIV4 -#elif STM32_PLLI2SP_VALUE == 6 -#define STM32_PLLI2SP STM32_PLLI2SP_DIV6 -#elif STM32_PLLI2SP_VALUE == 8 -#define STM32_PLLI2SP STM32_PLLI2SP_DIV8 -#else -#error "invalid STM32_PLLI2SP_VALUE value specified" -#endif - -/** - * @brief STM32_PLLI2SQ field. - */ -#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24) -#else -#error "invalid STM32_PLLI2SQ_VALUE value specified" -#endif - -/** - * @brief STM32_PLLI2SDIVQ field. - */ -#if ((STM32_PLLI2SDIVQ_VALUE >= 1) && (STM32_PLLI2SDIVQ_VALUE <= 32)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SDIVQ ((STM32_PLLI2SQ_VALUE - 1) << 0) -#else -#error "invalid STM32_PLLI2SDIVQ_VALUE value specified" -#endif - -/** - * @brief STM32_PLLI2SR field. - */ -#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \ - defined(__DOXYGEN__) -#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28) -#else -#error "invalid STM32_PLLI2SR_VALUE value specified" -#endif - -/** - * @brief PLLI2S input clock frequency. - */ -#if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__) -#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__) -#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE) -#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_CKIN -#define STM32_PLLI2SCLKIN (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE) -#else -#error "invalid STM32_PLLI2SSRC value specified" -#endif -#else -#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE) -#endif - -/** - * @brief PLLI2S VCO frequency. - */ -#define STM32_PLLI2SVCO (STM32_PLLI2SCLKIN * STM32_PLLI2SN_VALUE) - -/* - * PLLI2S VCO frequency range check. - */ -#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ - (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) -#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLLI2S P output clock frequency. - */ -#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE) - -/** - * @brief PLLI2S Q output clock frequency. - */ -#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE) - -/** - * @brief PLLI2S R output clock frequency. - */ -#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE) - -/* - * PLLSAI enable check. - */ -#if (STM32_HAS_RCC_PLLSAI && \ - (STM32_CLOCK48_REQUIRED && \ - (STM32_HAS_RCC_CK48MSEL && \ - !STM32_RCC_CK48MSEL_USES_I2S && \ - (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \ - (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \ - (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \ - (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI))) || \ - (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \ - defined(__DOXYGEN__) -/** - * @brief PLLSAI activation flag. - */ -#define STM32_ACTIVATE_PLLSAI TRUE -#else -#define STM32_ACTIVATE_PLLSAI FALSE -#endif - -/** - * @brief STM32_PLLSAIM field. - */ -#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0) -#else -#error "invalid STM32_PLLSAIM_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAIN field. - */ -#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6) -#else -#error "invalid STM32_PLLSAIN_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAIQ field. - */ -#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24) -#else -#error "invalid STM32_PLLSAIQ_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAIDIVQ_VALUE field. - */ -#if ((STM32_PLLSAIDIVQ_VALUE >= 1) && (STM32_PLLSAIDIVQ_VALUE <= 32)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAIDIVQ ((STM32_PLLSAIDIVQ_VALUE - 1) << 8) -#else -#error "invalid STM32_PLLSAIDIVQ_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAIR field. - */ -#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \ - defined(__DOXYGEN__) -#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28) -#else -#error "invalid STM32_PLLSAIR_VALUE value specified" -#endif - -/** - * @brief STM32_PLLSAIP field. - */ - -#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLSAIP STM32_PLLSAIP_DIV2 - -#elif STM32_PLLSAIP_VALUE == 4 -#define STM32_PLLSAIP STM32_PLLSAIP_DIV4 - -#elif STM32_PLLSAIP_VALUE == 6 -#define STM32_PLLSAIP STM32_PLLSAIP_DIV6 - -#elif STM32_PLLSAIP_VALUE == 8 -#define STM32_PLLSAIP STM32_PLLSAIP_DIV8 - -#else -#error "invalid STM32_PLLSAIP_VALUE value specified" -#endif - -/** - * @brief PLLSAI input clock frequency. - */ -#if defined(STM32F446xx) -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLSAIM_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLSAIM_VALUE) -#else -#error "invalid STM32_PLLSRC value specified" -#endif -#else /* !defined(STM32F446xx) */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLM_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLM_VALUE) -#else -#error "invalid STM32_PLLSRC value specified" -#endif -#endif /* defined(STM32F446xx) */ - -/** - * @brief PLLSAI VCO frequency. - */ -#define STM32_PLLSAIVCO (STM32_PLLSAICLKIN * STM32_PLLSAIN_VALUE) - -/* - * PLLSAI VCO frequency range check. - */ -#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \ - (STM32_PLLSAIVCO > STM32_PLLVCO_MAX) -#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" -#endif - -/** - * @brief PLLSAI P output clock frequency. - */ -#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE) - -/** - * @brief PLLSAI Q output clock frequency. - */ -#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE) - -/** - * @brief PLLSAI R output clock frequency. - */ -#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE) - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/