From 52b225739cc7791b90a8f60b654b7e790cedf969 Mon Sep 17 00:00:00 2001 From: cinsights Date: Mon, 12 Apr 2021 06:49:47 +0000 Subject: [PATCH] Add more RP peripheral definitions git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14166 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/common/ext/RP/RP2040/rp2040.h | 296 +++++++++++++++++++++++- os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.c | 187 +++++++++++++++ os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.h | 152 ++++++++++++ os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.c | 263 +++++++++++++++++++++ os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.h | 120 ++++++++++ 5 files changed, 1017 insertions(+), 1 deletion(-) create mode 100644 os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.c create mode 100644 os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.h create mode 100644 os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.c create mode 100644 os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.h diff --git a/os/common/ext/RP/RP2040/rp2040.h b/os/common/ext/RP/RP2040/rp2040.h index c6b59fd26..33513d23f 100644 --- a/os/common/ext/RP/RP2040/rp2040.h +++ b/os/common/ext/RP/RP2040/rp2040.h @@ -374,7 +374,7 @@ typedef struct { __IO uint32_t PHYDIRECT; __IO uint32_t PHYDIRECTOVERRIDE; __IO uint32_t PHYTRIM; - __IO uint32_t LINESTATE_TUNING; + __IO uint32_t LINESTATETUNING; __IO uint32_t INTR; __IO uint32_t INTE; __IO uint32_t INTF; @@ -1172,6 +1172,300 @@ typedef struct { #define WATCHDOG_TICK_CYCLES WATCHDOG_TICK_CYCLES_Msk /** @} */ +/** + * @name SPI bits definitions + * @{ + */ +#define SPI_SSPCR0_SCR_Pos 8U +#define SPI_SSPCR0_SCR_Msk (0xFFU << SPI_SSPCR0_SCR_Pos) +#define SPI_SSPCR0_SCR SPI_SSPCR0_SCR_Msk +#define SPI_SSPCR0_SPH_Pos 7U +#define SPI_SSPCR0_SPH_Msk (1U << SPI_SSPCR0_SPH_Pos) +#define SPI_SSPCR0_SPH SPI_SSPCR0_SPH_Msk +#define SPI_SSPCR0_SPO_Pos 6U +#define SPI_SSPCR0_SPO_Msk (1U << SPI_SSPCR0_SPO_Pos) +#define SPI_SSPCR0_SPO SPI_SSPCR0_SPO_Msk +#define SPI_SSPCR0_FRF_Pos 4U +#define SPI_SSPCR0_FRF_Msk (3U << SPI_SSPCR0_FRF_Pos) +#define SPI_SSPCR0_FRF SPI_SSPCR0_FRF_Msk +#define SPI_SSPCR0_DSS_Pos 0U +#define SPI_SSPCR0_DSS_Msk (0xFU << SPI_SSPCR0_DSS_Pos) +#define SPI_SSPCR0_DSS SPI_SSPCR0_DSS_Msk + +#define SPI_SSPCR1_SOD_Pos 3U +#define SPI_SSPCR1_SOD_Msk (1U << SPI_SSPCR1_SOD_Pos) +#define SPI_SSPCR1_SOD SPI_SSPCR1_SOD_Msk +#define SPI_SSPCR1_MS_Pos 2U +#define SPI_SSPCR1_MS_Msk (1U << SPI_SSPCR1_MS_Pos) +#define SPI_SSPCR1_MS SPI_SSPCR1_MS_Msk +#define SPI_SSPCR1_SSE_Pos 1U +#define SPI_SSPCR1_SSE_Msk (1U << SPI_SSPCR1_SSE_Pos) +#define SPI_SSPCR1_SSE SPI_SSPCR1_SSE_Msk +#define SPI_SSPCR1_LBM_Pos 0U +#define SPI_SSPCR1_LBM_Msk (1U << SPI_SSPCR1_LBM_Pos) +#define SPI_SSPCR1_LBM SPI_SSPCR1_LBM_Msk + +#define SPI_SSPDR_LBM_Pos 0U +#define SPI_SSPDR_LBM_Msk (0xFFFFU << SPI_SSPDR_LBM_Pos) +#define SPI_SSPDR_LBM SPI_SSPDR_LBM_Msk + +#define SPI_SSPSR_BSY_Pos 4U +#define SPI_SSPSR_BSY_Msk (1U << SPI_SSPSR_BSY_Pos) +#define SPI_SSPSR_BSY SPI_SSPSR_BSY_Msk +#define SPI_SSPSR_RFF_Pos 3U +#define SPI_SSPSR_RFF_Msk (1U << SPI_SSPSR_RFF_Pos) +#define SPI_SSPSR_RFF SPI_SSPSR_RFF_Msk +#define SPI_SSPSR_RNE_Pos 2U +#define SPI_SSPSR_RNE_Msk (1U << SPI_SSPSR_RNE_Pos) +#define SPI_SSPSR_RNE SPI_SSPSR_RNE_Msk +#define SPI_SSPSR_TNF_Pos 1U +#define SPI_SSPSR_TNF_Msk (1U << SPI_SSPSR_TNF_Pos) +#define SPI_SSPSR_TNF SPI_SSPSR_TNF_Msk +#define SPI_SSPSR_TFE_Pos 0U +#define SPI_SSPSR_TFE_Msk (1U << SPI_SSPSR_TFE_Pos) +#define SPI_SSPSR_TFE SPI_SSPSR_TFE_Msk + +#define SPI_SSPCPSR_CPSDVSR_Pos 0U +#define SPI_SSPCPSR_CPSDVSR_Msk (0xFF << SPI_SSPCPSR_CPSDVSR_Pos) +#define SPI_SSPCPSR_CPSDVSR SPI_SSPCPSR_CPSDVSR_Msk + +#define SPI_SSPIMSC_TXIM_Pos 3U +#define SPI_SSPIMSC_TXIM_Msk (1U << SPI_SSPIMSC_TXIM_Pos) +#define SPI_SSPIMSC_TXIM SPI_SSPIMSC_TXIM_Msk +#define SPI_SSPIMSC_RXIM_Pos 2U +#define SPI_SSPIMSC_RXIM_Msk (1U << SPI_SSPIMSC_RXIM_Pos) +#define SPI_SSPIMSC_RXIM SPI_SSPIMSC_RXIM_Msk +#define SPI_SSPIMSC_RTIM_Pos 1U +#define SPI_SSPIMSC_RTIM_Msk (1U << SPI_SSPIMSC_RTIM_Pos) +#define SPI_SSPIMSC_RTIM SPI_SSPIMSC_RTIM_Msk +#define SPI_SSPIMSC_RORIM_Pos 0U +#define SPI_SSPIMSC_RORIM_Msk (1U << SPI_SSPIMSC_RORIM_Pos) +#define SPI_SSPIMSC_RORIM SPI_SSPIMSC_RORIM_Msk + +#define SPI_SSPRIS_TXRIS_Pos 3U +#define SPI_SSPRIS_TXRIS_Msk (1U << SPI_SSPRIS_TXRIS_Pos) +#define SPI_SSPRIS_TXRIS SPI_SSPRIS_TXRIS_Msk +#define SPI_SSPRIS_RXRIS_Pos 2U +#define SPI_SSPRIS_RXRIS_Msk (1U << SPI_SSPRIS_RXRIS_Pos) +#define SPI_SSPRIS_RXRIS SPI_SSPRIS_RXRIS_Msk +#define SPI_SSPRIS_RTRIS_Pos 1U +#define SPI_SSPRIS_RTRIS_Msk (1U << SPI_SSPRIS_RTRIS_Pos) +#define SPI_SSPRIS_RTRIS SPI_SSPRIS_RTRIS_Msk +#define SPI_SSPRIS_RORRIS_Pos 0U +#define SPI_SSPRIS_RORRIS_Msk (1U << SPI_SSPRIS_RORRIS_Pos) +#define SPI_SSPRIS_RORRIS SPI_SSPRIS_RORRIS_Msk + +#define SPI_SSPMIS_TXMIS_Pos 3U +#define SPI_SSPMIS_TXMIS_Msk (1U << SPI_SSPMIS_TXMIS_Pos) +#define SPI_SSPMIS_TXMIS SPI_SSPMIS_TXMIS_Msk +#define SPI_SSPMIS_RXMIS_Pos 2U +#define SPI_SSPMIS_RXMIS_Msk (1U << SPI_SSPMIS_RXMIS_Pos) +#define SPI_SSPMIS_RXMIS SPI_SSPMIS_RXMIS_Msk +#define SPI_SSPMIS_RTMIS_Pos 1U +#define SPI_SSPMIS_RTMIS_Msk (1U << SPI_SSPMIS_RTMIS_Pos) +#define SPI_SSPMIS_RTMIS SPI_SSPMIS_RTMIS_Msk +#define SPI_SSPMIS_RORMIS_Pos 0U +#define SPI_SSPMIS_RORMIS_Msk (1U << SPI_SSPMIS_RORMIS_Pos) +#define SPI_SSPMIS_RORMIS SPI_SSPMIS_RORMIS_Msk + +#define SPI_SSPICR_RTIC_Pos 1U +#define SPI_SSPICR_RTIC_Msk (1U << SPI_SSPICR_RTIC_Pos) +#define SPI_SSPICR_RTIC SPI_SSPICR_RTIC_Msk +#define SPI_SSPICR_RORIC_Pos 0U +#define SPI_SSPICR_RORIC_Msk (1U << SPI_SSPICR_RORIC_Pos) +#define SPI_SSPICR_RORIC SPI_SSPICR_RORIC_Msk + +#define SPI_SSPDMACR_TXDMAE_Pos 1U +#define SPI_SSPDMACR_TXDMAE_Msk (1U << SPI_SSPDMACR_TXDMAE_Pos) +#define SPI_SSPDMACR_TXDMAE SPI_SSPDMACR_TXDMAE_Msk +#define SPI_SSPDMACR_RXDMAE_Pos 0U +#define SPI_SSPDMACR_RXDMAE_Msk (1U << SPI_SSPDMACR_RXDMAE_Pos) +#define SPI_SSPDMACR_RXDMAE SPI_SSPDMACR_RXDMAE_Msk +/** @} */ + +/** + * @name I2C bits definitions + * @{ + */ +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_Pos 10U +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_Msk (1U << I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_Pos) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_Msk +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_Pos 9U +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_Msk (1U << I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_Pos) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_Msk +#define I2C_IC_CON_TX_EMPTY_CTRL_Pos 8U +#define I2C_IC_CON_TX_EMPTY_CTRL_Msk (1U << I2C_IC_CON_TX_EMPTY_CTRL_Pos) +#define I2C_IC_CON_TX_EMPTY_CTRL I2C_IC_CON_TX_EMPTY_CTRL_Msk +#define I2C_IC_CON_STOP_DET_IFADDRESSED_Pos 7U +#define I2C_IC_CON_STOP_DET_IFADDRESSED_Msk (1U << I2C_IC_CON_STOP_DET_IFADDRESSED_Pos) +#define I2C_IC_CON_STOP_DET_IFADDRESSED I2C_IC_CON_STOP_DET_IFADDRESSED_Msk +#define I2C_IC_CON_IC_SLAVE_DISABLE_Pos 6U +#define I2C_IC_CON_IC_SLAVE_DISABLE_Msk (1U << I2C_IC_CON_IC_SLAVE_DISABLE_Pos) +#define I2C_IC_CON_IC_SLAVE_DISABLE I2C_IC_CON_IC_SLAVE_DISABLE_Msk +#define I2C_IC_CON_IC_RESTART_EN_Pos 5U +#define I2C_IC_CON_IC_RESTART_EN_Msk (1U << I2C_IC_CON_IC_RESTART_EN_Pos) +#define I2C_IC_CON_IC_RESTART_EN I2C_IC_CON_IC_RESTART_EN_Msk +#define I2C_IC_CON_IC_10BITADDR_MASTER_Pos 4U +#define I2C_IC_CON_IC_10BITADDR_MASTER_Msk (1U << I2C_IC_CON_IC_10BITADDR_MASTER_Pos) +#define I2C_IC_CON_IC_10BITADDR_MASTER I2C_IC_CON_IC_10BITADDR_MASTER_Msk +#define I2C_IC_CON_IC_10BITADDR_SLAVE_Pos 3U +#define I2C_IC_CON_IC_10BITADDR_SLAVE_Msk (1U << I2C_IC_CON_IC_10BITADDR_SLAVE_Pos) +#define I2C_IC_CON_IC_10BITADDR_SLAVE I2C_IC_CON_IC_10BITADDR_SLAVE_Msk +#define I2C_IC_CON_SPEED_Pos 1U +#define I2C_IC_CON_SPEED_Msk (3U << I2C_IC_CON_SPEED_Pos) +#define I2C_IC_CON_SPEED I2C_IC_CON_SPEED_Msk +#define I2C_IC_CON_MASTER_MODE_Pos 0U +#define I2C_IC_CON_MASTER_MODE_Msk (1U << I2C_IC_CON_MASTER_MODE_Pos) +#define I2C_IC_CON_MASTER_MODE I2C_IC_CON_MASTER_MODE_Msk + +#define I2C_IC_TAR_SPECIAL_Pos 11U +#define I2C_IC_TAR_SPECIAL_Msk (1U << I2C_IC_TAR_SPECIAL_Pos) +#define I2C_IC_TAR_SPECIAL I2C_IC_TAR_SPECIAL_Msk +#define I2C_IC_TAR_GC_OR_START_Pos 10U +#define I2C_IC_TAR_GC_OR_START_Msk (1U << I2C_IC_TAR_GC_OR_START_Pos) +#define I2C_IC_TAR_GC_OR_START I2C_IC_TAR_GC_OR_START_Msk +#define I2C_IC_TAR_IC_TAR_Pos 0U +#define I2C_IC_TAR_IC_TAR_Msk (0x3FFU << I2C_IC_TAR_IC_TAR_Pos) +#define I2C_IC_TAR_IC_TAR I2C_IC_TAR_IC_TAR_Msk + +#define I2C_IC_SAR_IC_SAR_Pos 0U +#define I2C_IC_SAR_IC_SAR_Msk (0x3FFU << I2C_IC_SAR_IC_SAR_Pos) +#define I2C_IC_SAR_IC_SAR I2C_IC_SAR_IC_SAR_Msk + +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_Pos 11U +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_Msk (1U << I2C_IC_DATA_CMD_FIRST_DATA_BYTE_Pos) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE I2C_IC_DATA_CMD_FIRST_DATA_BYTE_Msk +#define I2C_IC_DATA_CMD_RESTART_Pos 10U +#define I2C_IC_DATA_CMD_RESTART_Msk (1U << I2C_IC_DATA_CMD_RESTART_Pos) +#define I2C_IC_DATA_CMD_RESTART I2C_IC_DATA_CMD_RESTART_Msk +#define I2C_IC_DATA_CMD_STOP_Pos 9U +#define I2C_IC_DATA_CMD_STOP_Msk (1U << I2C_IC_DATA_CMD_STOP_Pos) +#define I2C_IC_DATA_CMD_STOP I2C_IC_DATA_CMD_STOP_Msk +#define I2C_IC_DATA_CMD_CMD_Pos 8U +#define I2C_IC_DATA_CMD_CMD_Msk (1U << I2C_IC_DATA_CMD_CMD_Pos) +#define I2C_IC_DATA_CMD_CMD I2C_IC_DATA_CMD_CMD_Msk +#define I2C_IC_DATA_CMD_DAT_Pos 0U +#define I2C_IC_DATA_CMD_DAT_Msk (0xFFU << I2C_IC_DATA_CMD_DAT_Pos) +#define I2C_IC_DATA_CMD_DAT I2C_IC_DATA_CMD_DAT_Msk + +#define I2C_IC_SS_SCL_HCNT_Pos 0U +#define I2C_IC_SS_SCL_HCNT_Msk (0xFFFFU << I2C_IC_SS_SCL_HCNT_Pos) +#define I2C_IC_SS_SCL_HCNT I2C_IC_SS_SCL_HCNT_Msk + +#define I2C_IC_SS_SCL_LCNT_Pos 0U +#define I2C_IC_SS_SCL_LCNT_Msk (0xFFFFU << I2C_IC_SS_SCL_LCNT_Pos) +#define I2C_IC_SS_SCL_LCNT I2C_IC_SS_SCL_LCNT_Msk + +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_Pos 0U +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_Msk (0xFFFFU << I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_Pos) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_Msk + +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_Pos 0U +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_Msk (0xFFFFU << I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_Pos) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_Msk + +#define I2C_IC_FS_SCL_HCNT_Pos 0U +#define I2C_IC_FS_SCL_HCNT_Msk (0xFFFFU << I2C_IC_FS_SCL_HCNT_Pos) +#define I2C_IC_FS_SCL_HCNT I2C_IC_FS_SCL_HCNT_Msk + +#define I2C_IC_FS_SCL_LCNT_Pos 0U +#define I2C_IC_FS_SCL_LCNT_Msk (0xFFFFU << I2C_IC_FS_SCL_LCNT_Pos) +#define I2C_IC_FS_SCL_LCNT I2C_IC_FS_SCL_LCNT_Msk + +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Pos 0U +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Msk (0xFFFFU << I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Pos) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Msk + +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Pos 0U +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Msk (0xFFFFU << I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Pos) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Msk + +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_Pos 13U +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_Msk (1U << I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_Pos) +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_Msk +#define I2C_IC_INTR_STAT_R_RESTART_DET_Pos 12U +#define I2C_IC_INTR_STAT_R_RESTART_DET_Msk (1U << I2C_IC_INTR_STAT_R_RESTART_DET_Pos) +#define I2C_IC_INTR_STAT_R_RESTART_DET I2C_IC_INTR_STAT_R_RESTART_DET_Msk +#define I2C_IC_INTR_STAT_R_GEN_CALL_Pos 11U +#define I2C_IC_INTR_STAT_R_GEN_CALL_Msk (1U << I2C_IC_INTR_STAT_R_GEN_CALL_Pos) +#define I2C_IC_INTR_STAT_R_GEN_CALL I2C_IC_INTR_STAT_R_GEN_CALL_Msk +#define I2C_IC_INTR_STAT_R_START_DET_Pos 10U +#define I2C_IC_INTR_STAT_R_START_DET_Msk (1U << I2C_IC_INTR_STAT_R_START_DET_Pos) +#define I2C_IC_INTR_STAT_R_START_DET I2C_IC_INTR_STAT_R_START_DET_Msk +#define I2C_IC_INTR_STAT_R_STOP_DET_Pos 9U +#define I2C_IC_INTR_STAT_R_STOP_DET_Msk (1U << I2C_IC_INTR_STAT_R_STOP_DET_Pos) +#define I2C_IC_INTR_STAT_R_STOP_DET I2C_IC_INTR_STAT_R_STOP_DET_Msk +#define I2C_IC_INTR_STAT_R_ACTIVITY_Pos 8U +#define I2C_IC_INTR_STAT_R_ACTIVITY_Msk (1U << I2C_IC_INTR_STAT_R_ACTIVITY_Pos) +#define I2C_IC_INTR_STAT_R_ACTIVITY I2C_IC_INTR_STAT_R_ACTIVITY_Msk +#define I2C_IC_INTR_STAT_R_RX_DONE_Pos 7U +#define I2C_IC_INTR_STAT_R_RX_DONE_Msk (1U << I2C_IC_INTR_STAT_R_RX_DONE_Pos) +#define I2C_IC_INTR_STAT_R_RX_DONE I2C_IC_INTR_STAT_R_RX_DONE_Msk +#define I2C_IC_INTR_STAT_R_TX_ABRT_Pos 6U +#define I2C_IC_INTR_STAT_R_TX_ABRT_Msk (1U << I2C_IC_INTR_STAT_R_TX_ABRT_Pos) +#define I2C_IC_INTR_STAT_R_TX_ABRT I2C_IC_INTR_STAT_R_TX_ABRT_Msk +#define I2C_IC_INTR_STAT_R_RD_REQ_Pos 5U +#define I2C_IC_INTR_STAT_R_RD_REQ_Msk (1U << I2C_IC_INTR_STAT_R_RD_REQ_Pos) +#define I2C_IC_INTR_STAT_R_RD_REQ I2C_IC_INTR_STAT_R_RD_REQ_Msk +#define I2C_IC_INTR_STAT_R_TX_EMPTY_Pos 4U +#define I2C_IC_INTR_STAT_R_TX_EMPTY_Msk (1U << I2C_IC_INTR_STAT_R_TX_EMPTY_Pos) +#define I2C_IC_INTR_STAT_R_TX_EMPTY I2C_IC_INTR_STAT_R_TX_EMPTY_Msk +#define I2C_IC_INTR_STAT_R_TX_OVER_Pos 3U +#define I2C_IC_INTR_STAT_R_TX_OVER_Msk (1U << I2C_IC_INTR_STAT_R_TX_OVER_Pos) +#define I2C_IC_INTR_STAT_R_TX_OVER I2C_IC_INTR_STAT_R_TX_OVER_Msk +#define I2C_IC_INTR_STAT_R_RX_FULL_Pos 2U +#define I2C_IC_INTR_STAT_R_RX_FULL_Msk (1U << I2C_IC_INTR_STAT_R_RX_FULL_Pos) +#define I2C_IC_INTR_STAT_R_RX_FULL I2C_IC_INTR_STAT_R_RX_FULL_Msk +#define I2C_IC_INTR_STAT_R_RX_OVER_Pos 1U +#define I2C_IC_INTR_STAT_R_RX_OVER_Msk (1U << I2C_IC_INTR_STAT_R_RX_OVER_Pos) +#define I2C_IC_INTR_STAT_R_RX_OVER I2C_IC_INTR_STAT_R_RX_OVER_Msk +#define I2C_IC_INTR_STAT_R_RX_UNDER_Pos 0U +#define I2C_IC_INTR_STAT_R_RX_UNDER_Msk (1U << I2C_IC_INTR_STAT_R_RX_UNDER_Pos) +#define I2C_IC_INTR_STAT_R_RX_UNDER I2C_IC_INTR_STAT_R_RX_UNDER_Msk + +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Pos 13U +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Msk (1U << I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Pos) +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Msk +#define I2C_IC_INTR_MASK_M_RESTART_DET_Pos 12U +#define I2C_IC_INTR_MASK_M_RESTART_DET_Msk (1U << I2C_IC_INTR_MASK_M_RESTART_DET_Pos) +#define I2C_IC_INTR_MASK_M_RESTART_DET I2C_IC_INTR_MASK_M_RESTART_DET_Msk +#define I2C_IC_INTR_MASK_M_GEN_CALL_Pos 11U +#define I2C_IC_INTR_MASK_M_GEN_CALL_Msk (1U << I2C_IC_INTR_MASK_M_GEN_CALL_Pos) +#define I2C_IC_INTR_MASK_M_GEN_CALL I2C_IC_INTR_MASK_M_GEN_CALL_Msk +#define I2C_IC_INTR_MASK_M_START_DET_Pos 10U +#define I2C_IC_INTR_MASK_M_START_DET_Msk (1U << I2C_IC_INTR_MASK_M_START_DET_Pos) +#define I2C_IC_INTR_MASK_M_START_DET I2C_IC_INTR_MASK_M_START_DET_Msk +#define I2C_IC_INTR_MASK_M_STOP_DET_Pos 9U +#define I2C_IC_INTR_MASK_M_STOP_DET_Msk (1U << I2C_IC_INTR_MASK_M_STOP_DET_Pos) +#define I2C_IC_INTR_MASK_M_STOP_DET I2C_IC_INTR_MASK_M_STOP_DET_Msk +#define I2C_IC_INTR_MASK_M_ACTIVITY_Pos 8U +#define I2C_IC_INTR_MASK_M_ACTIVITY_Msk (1U << I2C_IC_INTR_MASK_M_ACTIVITY_Pos) +#define I2C_IC_INTR_MASK_M_ACTIVITY I2C_IC_INTR_MASK_M_ACTIVITY_Msk +#define I2C_IC_INTR_MASK_M_RX_DONE_Pos 7U +#define I2C_IC_INTR_MASK_M_RX_DONE_Msk (1U << I2C_IC_INTR_MASK_M_RX_DONE_Pos) +#define I2C_IC_INTR_MASK_M_RX_DONE I2C_IC_INTR_MASK_M_RX_DONE_Msk +#define I2C_IC_INTR_MASK_M_TX_ABRT_Pos 6U +#define I2C_IC_INTR_MASK_M_TX_ABRT_Msk (1U << I2C_IC_INTR_MASK_M_TX_ABRT_Pos) +#define I2C_IC_INTR_MASK_M_TX_ABRT I2C_IC_INTR_MASK_M_TX_ABRT_Msk +#define I2C_IC_INTR_MASK_M_RD_REQ_Pos 5U +#define I2C_IC_INTR_MASK_M_RD_REQ_Msk (1U << I2C_IC_INTR_MASK_M_RD_REQ_Pos) +#define I2C_IC_INTR_MASK_M_RD_REQ I2C_IC_INTR_MASK_M_RD_REQ_Msk +#define I2C_IC_INTR_MASK_M_TX_EMPTY_Pos 4U +#define I2C_IC_INTR_MASK_M_TX_EMPTY_Msk (1U << I2C_IC_INTR_MASK_M_TX_EMPTY_Pos) +#define I2C_IC_INTR_MASK_M_TX_EMPTY I2C_IC_INTR_MASK_M_TX_EMPTY_Msk +#define I2C_IC_INTR_MASK_M_TX_OVER_Pos 3U +#define I2C_IC_INTR_MASK_M_TX_OVER_Msk (1U << I2C_IC_INTR_MASK_M_TX_OVER_Pos) +#define I2C_IC_INTR_MASK_M_TX_OVER I2C_IC_INTR_MASK_M_TX_OVER_Msk +#define I2C_IC_INTR_MASK_M_RX_FULL_Pos 2U +#define I2C_IC_INTR_MASK_M_RX_FULL_Msk (1U << I2C_IC_INTR_MASK_M_RX_FULL_Pos) +#define I2C_IC_INTR_MASK_M_RX_FULL I2C_IC_INTR_MASK_M_RX_FULL_Msk +#define I2C_IC_INTR_MASK_M_RX_OVER_Pos 1U +#define I2C_IC_INTR_MASK_M_RX_OVER_Msk (1U << I2C_IC_INTR_MASK_M_RX_OVER_Pos) +#define I2C_IC_INTR_MASK_M_RX_OVER I2C_IC_INTR_MASK_M_RX_OVER_Msk +#define I2C_IC_INTR_MASK_M_RX_UNDER_Pos 0U +#define I2C_IC_INTR_MASK_M_RX_UNDER_Msk (1U << I2C_IC_INTR_MASK_M_RX_UNDER_Pos) +#define I2C_IC_INTR_MASK_M_RX_UNDER I2C_IC_INTR_MASK_M_RX_UNDER_Msk +/** @} */ #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.c new file mode 100644 index 000000000..bf341df12 --- /dev/null +++ b/os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.c @@ -0,0 +1,187 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_i2c_lld.c + * @brief RP2040 I2C subsystem low level driver source. + * + * @addtogroup I2C + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief I2C1 driver identifier. + */ +#if (PLATFORM_I2C_USE_I2C1 == TRUE) || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if PLATFORM_I2C_USE_I2C1 == TRUE + i2cObjectInit(&I2CD1); +#endif +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) { + + if (i2cp->state == I2C_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_I2C_USE_I2C1 == TRUE + if (&I2CD1 == i2cp) { + + } +#endif + } + +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) { + + if (i2cp->state != I2C_STOP) { + + /* Disables the peripheral.*/ +#if PLATFORM_I2C_USE_I2C1 == TRUE + if (&I2CD1 == i2cp) { + + } +#endif + } +} + +/** + * @brief Receives data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout) { + + (void)i2cp; + (void)addr; + (void)rxbuf; + (void)rxbytes; + (void)timeout; + + return MSG_OK; +} + +/** + * @brief Transmits data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout) { + + (void)i2cp; + (void)addr; + (void)txbuf; + (void)txbytes; + (void)rxbuf; + (void)rxbytes; + (void)timeout; + + return MSG_OK; +} + +#endif /* HAL_USE_I2C == TRUE */ + +/** @} */ diff --git a/os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.h b/os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.h new file mode 100644 index 000000000..0e85ce624 --- /dev/null +++ b/os/hal/ports/RP/LLD/I2Cv1/hal_i2c_lld.h @@ -0,0 +1,152 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_i2c_lld.h + * @brief RP2040 I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef HAL_I2C_LLD_H +#define HAL_I2C_LLD_H + +#if (HAL_USE_I2C == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define PLATFORM_I2C_USE_I2C1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing an I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief Type of I2C Driver condition flags. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Type of I2C driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + /* End of the mandatory fields.*/ + uint32_t dummy; +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if (I2C_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + mutex_t mutex; +#endif +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (PLATFORM_I2C_USE_I2C1 == TRUE) && !defined(__DOXYGEN__) +extern I2CDriver I2CD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C == TRUE */ + +#endif /* HAL_I2C_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.c b/os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.c new file mode 100644 index 000000000..534066da5 --- /dev/null +++ b/os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.c @@ -0,0 +1,263 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_spi_lld.c + * @brief RP2040 SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver identifier. + */ +#if (PLATFORM_SPI_USE_SPI1 == TRUE) || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if PLATFORM_SPI_USE_SPI1 == TRUE + /* Driver initialization.*/ + spiObjectInit(&SPID1); +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Enables the peripheral.*/ +#if PLATFORM_SPI_USE_SPI1 == TRUE + if (&SPID1 == spip) { + + } +#endif + } + /* Configures the peripheral.*/ + +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state == SPI_READY) { + /* Disables the peripheral.*/ +#if PLATFORM_SPI_USE_SPI1 == TRUE + if (&SPID1 == spip) { + + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + (void)spip; + +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + (void)spip; + +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + (void)spip; + (void)n; + +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + (void)spip; + (void)n; + (void)txbuf; + (void)rxbuf; + +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + (void)spip; + (void)n; + (void)txbuf; + +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + (void)spip; + (void)n; + (void)rxbuf; + +} + +#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__) +/** + * @brief Aborts the ongoing SPI operation, if any. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_abort(SPIDriver *spip) { + + (void)spip; +} +#endif /* SPI_SUPPORTS_CIRCULAR == TRUE */ + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + * + * @notapi + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + (void)spip; + (void)frame; + + return 0; +} + +#endif /* HAL_USE_SPI == TRUE */ + +/** @} */ diff --git a/os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.h b/os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.h new file mode 100644 index 000000000..bddd7649e --- /dev/null +++ b/os/hal/ports/RP/LLD/SPIv1/hal_spi_lld.h @@ -0,0 +1,120 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_spi_lld.h + * @brief RP2040 SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef HAL_SPI_LLD_H +#define HAL_SPI_LLD_H + +#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Circular mode support flag. + */ +#define SPI_SUPPORTS_CIRCULAR TRUE + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define PLATFORM_SPI_USE_SPI1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the SPI driver structure. + */ +#define spi_lld_driver_fields \ + /* Dummy field, it is not needed.*/ \ + uint32_t dummy + +/** + * @brief Low level fields of the SPI configuration structure. + */ +#define spi_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (PLATFORM_SPI_USE_SPI1 == TRUE) && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); +#endif + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); +#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__) + void spi_lld_abort(SPIDriver *spip); +#endif + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI == TRUE */ + +#endif /* HAL_SPI_LLD_H */ + +/** @} */