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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5804 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-06-03 14:40:57 +00:00
parent 53d4dfdc10
commit 52cac10dbc
7 changed files with 197 additions and 56 deletions
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49
demos/PPC-SPC563M-GCC/mcuconf.h
View File

@ -53,7 +53,27 @@
#define SPC5_ADC_USE_ADC1_Q3 FALSE
#define SPC5_ADC_USE_ADC1_Q4 FALSE
#define SPC5_ADC_USE_ADC1_Q5 FALSE
#define SPC5_ADC_FIFO0_DMA_PRIO 12
#define SPC5_ADC_FIFO1_DMA_PRIO 12
#define SPC5_ADC_FIFO2_DMA_PRIO 12
#define SPC5_ADC_FIFO3_DMA_PRIO 12
#define SPC5_ADC_FIFO4_DMA_PRIO 12
#define SPC5_ADC_FIFO5_DMA_PRIO 12
#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12
#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \
ADC_PUDCR_NONE, \
ADC_PUDCR_NONE, \
ADC_PUDCR_NONE, \
ADC_PUDCR_NONE, \
ADC_PUDCR_NONE, \
ADC_PUDCR_NONE, \
ADC_PUDCR_NONE}
/*
* SERIAL driver system settings.
@ -62,3 +82,32 @@
#define SPC5_USE_ESCIB TRUE
#define SPC5_ESCIA_PRIORITY 8
#define SPC5_ESCIB_PRIORITY 8
/*
* SPI driver system settings.
*/
#define SPC5_SPI_USE_DSPI1 FALSE
#define SPC5_SPI_USE_DSPI2 FALSE
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI1_DMA_PRIO 10
#define SPC5_SPI_DSPI2_DMA_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_IRQ_PRIO 10
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()

10
os/hal/platforms/SPC563Mxx/spc563m_registry.h
View File

@ -39,14 +39,20 @@
#define SPC5_HAS_DSPI2 TRUE
#define SPC5_HAS_DSPI3 FALSE
#define SPC5_DSPI_FIFO_DEPTH 16
#define SPC5_DSPI1_TX_DMA_DEV_ID 12
#define SPC5_DSPI1_TX1_DMA_DEV_ID 12
#define SPC5_DSPI1_TX2_DMA_DEV_ID 25
#define SPC5_DSPI1_RX_DMA_DEV_ID 13
#define SPC5_DSPI2_TX_DMA_DEV_ID 14
#define SPC5_DSPI2_TX1_DMA_DEV_ID 14
#define SPC5_DSPI2_TX2_DMA_DEV_ID 26
#define SPC5_DSPI2_RX_DMA_DEV_ID 15
#define SPC5_DSPI1_EOQF_HANDLER vector132
#define SPC5_DSPI1_EOQF_NUMBER 132
#define SPC5_DSPI1_TFFF_HANDLER vector133
#define SPC5_DSPI1_TFFF_NUMBER 133
#define SPC5_DSPI2_EOQF_HANDLER vector137
#define SPC5_DSPI2_EOQF_NUMBER 137
#define SPC5_DSPI2_TFFF_HANDLER vector138
#define SPC5_DSPI2_TFFF_NUMBER 138
#define SPC5_DSPI1_ENABLE_CLOCK()
#define SPC5_DSPI1_DISABLE_CLOCK()
#define SPC5_DSPI2_ENABLE_CLOCK()

69
os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
View File

@ -38,20 +38,6 @@ static void spi_serve_dma_error_irq(edma_channel_t channel,
/* Driver local definitions. */
/*===========================================================================*/
/* Enforced MCR bits.*/
#define DSPI_MCR_ENFORCED_BITS (SPC5_MCR_MSTR)
/* Excluded MCR bits.*/
#define DSPI_MCR_EXCLUDED_BITS (SPC5_MCR_CONT_SCKE | \
SPC5_MCR_DCONF_MASK | \
SPC5_MCR_ROOE | \
SPC5_MCR_MDIS | \
SPC5_MCR_DIS_TXF | \
SPC5_MCR_DIS_RXF | \
SPC5_MCR_CLR_TXF | \
SPC5_MCR_CLR_RXF | \
SPC5_MCR_HALT)
/* Excluded PUSHR bits.*/
#define DSPI_PUSHR_EXCLUDED_BITS (SPC5_PUSHR_CTAS_MASK | \
SPC5_PUSHR_EOQ | \
@ -530,9 +516,7 @@ static void spi_serve_rx_irq(edma_channel_t channel, void *p) {
edmaChannelStop(channel);
/* Stops the DSPI and clears the queues.*/
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT |
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF |
spip->config->mcr;
spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
/* Portable SPI ISR code defined in the high level driver, note, it is
a macro.*/
@ -586,8 +570,7 @@ static void spi_serve_dma_error_irq(edma_channel_t channel,
(void)esr;
/* Stops the DSPI and clears the queues.*/
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT |
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
edmaChannelStop(spip->tx1_channel);
edmaChannelStop(spip->tx2_channel);
@ -734,6 +717,8 @@ void spi_lld_init(void) {
SPID1.tx1_channel = EDMA_ERROR;
SPID1.tx2_channel = EDMA_ERROR;
SPID1.rx_channel = EDMA_ERROR;
SPC5_DSPI0.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
SPC5_SPI_DSPI0_MCR;
INTC.PSR[SPC5_DSPI0_TFFF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI0 */
@ -744,6 +729,8 @@ void spi_lld_init(void) {
SPID2.tx1_channel = EDMA_ERROR;
SPID2.tx2_channel = EDMA_ERROR;
SPID2.rx_channel = EDMA_ERROR;
SPC5_DSPI1.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
SPC5_SPI_DSPI1_MCR;
INTC.PSR[SPC5_DSPI1_TFFF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI1 */
@ -754,6 +741,8 @@ void spi_lld_init(void) {
SPID3.tx1_channel = EDMA_ERROR;
SPID3.tx2_channel = EDMA_ERROR;
SPID3.rx_channel = EDMA_ERROR;
SPC5_DSPI2.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
SPC5_SPI_DSPI2_MCR;
INTC.PSR[SPC5_DSPI2_TFFF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI2 */
@ -764,6 +753,8 @@ void spi_lld_init(void) {
SPID4.tx1_channel = EDMA_ERROR;
SPID4.tx2_channel = EDMA_ERROR;
SPID4.rx_channel = EDMA_ERROR;
SPC5_DSPI3.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
SPC5_SPI_DSPI3_MCR;
INTC.PSR[SPC5_DSPI3_TFFF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI3 */
}
@ -779,8 +770,6 @@ void spi_lld_start(SPIDriver *spip) {
chDbgAssert((spip->config->pushr & DSPI_PUSHR_EXCLUDED_BITS) == 0,
"spi_lld_start(), #1", "invalid PUSHR bits specified");
chDbgAssert((spip->config->mcr & DSPI_MCR_EXCLUDED_BITS) == 0,
"spi_lld_start(), #2", "invalid PUSHR bits specified");
if (spip->state == SPI_STOP) {
/* Enables the peripheral.*/
@ -828,12 +817,11 @@ void spi_lld_start(SPIDriver *spip) {
}
/* Configures the peripheral.*/
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT |
spip->config->mcr;
spip->dspi->CTAR[0].R = spip->config->ctar0;
spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.B.MDIS = 0;
spip->dspi->CTAR[0].R = spip->config->ctar0;
spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
spip->dspi->SR.R = spip->dspi->SR.R;
}
/**
@ -852,12 +840,12 @@ void spi_lld_stop(SPIDriver *spip) {
edmaChannelRelease(spip->rx_channel);
/* Resets the peripheral.*/
spip->dspi->CTAR[0].R = 0;
spip->dspi->RSER.R = 0;
spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_MDIS |
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF |
SPC5_MCR_HALT;
spip->dspi->CTAR[0].R = 0;
spip->dspi->RSER.R = 0;
spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.R |= SPC5_MCR_HALT |
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
spip->dspi->MCR.B.MDIS = 1;
#if SPC5_SPI_USE_DSPI0
if (&SPID1 == spip) {
@ -927,7 +915,7 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
/* Starting transfer.*/
spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | spip->config->mcr;
spip->dspi->MCR.B.HALT = 0;
/* Setting up the RX DMA channel.*/
spi_start_dma_rx_ignore(spip, n);
@ -963,7 +951,7 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
/* Starting transfer.*/
spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | spip->config->mcr;
spip->dspi->MCR.B.HALT = 0;
/* DMAs require a different setup depending on the frame size.*/
if (spip->dspi->CTAR[0].B.FMSZ < 8) {
@ -1013,7 +1001,7 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
/* Starting transfer.*/
spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | spip->config->mcr;
spip->dspi->MCR.B.HALT = 0;
/* Setting up the RX DMA channel.*/
spi_start_dma_rx_ignore(spip, n);
@ -1060,7 +1048,7 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
/* Starting transfer.*/
spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | spip->config->mcr;
spip->dspi->MCR.B.HALT = 0;
/* DMAs require a different setup depending on the frame size.*/
if (spip->dspi->CTAR[0].B.FMSZ < 8) {
@ -1096,13 +1084,16 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
* @return The received data frame from the SPI bus.
*/
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
uint32_t popr;
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | spip->config->mcr;
spip->dspi->MCR.B.HALT = 0;
spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | spip->config->pushr |
(uint32_t)frame) & ~SPC5_PUSHR_CONT;
while (!spip->dspi->SR.B.RFDF)
;
return (uint16_t)spip->dspi->POPR.R;
popr = spip->dspi->POPR.R;
spip->dspi->MCR.B.HALT = 1;
return (uint16_t)popr;
}
#endif /* HAL_USE_SPI */

63
os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
View File

@ -223,6 +223,7 @@
#if !defined(SPC5_SPI_USE_DSPI1) || defined(__DOXYGEN__)
#define SPC5_SPI_USE_DSPI1 FALSE
#endif
/**
* @brief SPID3 driver enable switch.
* @details If set to @p TRUE the support for DSPI2 is included.
@ -239,6 +240,62 @@
#define SPC5_SPI_USE_DSPI3 FALSE
#endif
/**
* @brief DSPI0 MCR PCS defaults.
*/
#if !defined(SPC5_SPI_DSPI0_MCR) || defined(__DOXYGEN__)
#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#endif
/**
* @brief DSPI1 MCR PCS defaults.
*/
#if !defined(SPC5_SPI_DSPI1_MCR) || defined(__DOXYGEN__)
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#endif
/**
* @brief DSP2 MCR PCS defaults.
*/
#if !defined(SPC5_SPI_DSPI2_MCR) || defined(__DOXYGEN__)
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#endif
/**
* @brief DSPI3 MCR PCS defaults.
*/
#if !defined(SPC5_SPI_DSPI3_MCR) || defined(__DOXYGEN__)
#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#endif
/**
* @brief DSPI0 DMA priority.
*/
@ -392,12 +449,6 @@ typedef struct {
* @brief The chip select line pad number.
*/
uint16_t sspad;
/**
* @brief DSPI MCR value for this session.
* @note Some bits are ignored: CONT_SCKE, DCONF, ROOE, MDIS, DIS_TXF,
* DIS_RXF, CLR_TXF, CLR_RXF, HALT.
*/
uint32_t mcr;
/**
* @brief DSPI CTAR0 value for this session.
*/

29
testhal/SPC563Mxx/ADC/mcuconf.h
View File

@ -82,3 +82,32 @@
#define SPC5_USE_ESCIB TRUE
#define SPC5_ESCIA_PRIORITY 8
#define SPC5_ESCIB_PRIORITY 8
/*
* SPI driver system settings.
*/
#define SPC5_SPI_USE_DSPI1 FALSE
#define SPC5_SPI_USE_DSPI2 FALSE
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI1_DMA_PRIO 10
#define SPC5_SPI_DSPI2_DMA_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_IRQ_PRIO 10
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()

5
testhal/SPC563Mxx/SPI/main.c
View File

@ -24,10 +24,9 @@ static const SPIConfig hs_spicfg = {
NULL,
0,
0,
SPC5_MCR_PCSIS0, /* MCR. */
SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) |
SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */
SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */
SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */
};
/*
@ -37,7 +36,6 @@ static const SPIConfig ls_spicfg = {
NULL,
0,
0,
SPC5_MCR_PCSIS0, /* MCR. */
SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) |
SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */
SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */
@ -119,6 +117,7 @@ int main(void) {
SIU.PCR[103].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SIN */
SIU.PCR[104].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */
SIU.PCR[105].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* PCS[0] */
SIU.PCR[106].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* PCS[1] */
/* Testing sending and receiving at the same time.*/
spiExchange(&SPID2, 4, txbuf, rxbuf);

28
testhal/SPC563Mxx/SPI/mcuconf.h
View File

@ -47,12 +47,12 @@
/*
* ADC driver settings.
*/
#define SPC5_ADC_USE_ADC0_Q0 TRUE
#define SPC5_ADC_USE_ADC0_Q1 TRUE
#define SPC5_ADC_USE_ADC0_Q2 TRUE
#define SPC5_ADC_USE_ADC1_Q3 TRUE
#define SPC5_ADC_USE_ADC1_Q4 TRUE
#define SPC5_ADC_USE_ADC1_Q5 TRUE
#define SPC5_ADC_USE_ADC0_Q0 FALSE
#define SPC5_ADC_USE_ADC0_Q1 FALSE
#define SPC5_ADC_USE_ADC0_Q2 FALSE
#define SPC5_ADC_USE_ADC1_Q3 FALSE
#define SPC5_ADC_USE_ADC1_Q4 FALSE
#define SPC5_ADC_USE_ADC1_Q5 FALSE
#define SPC5_ADC_FIFO0_DMA_PRIO 12
#define SPC5_ADC_FIFO1_DMA_PRIO 12
#define SPC5_ADC_FIFO2_DMA_PRIO 12
@ -88,6 +88,22 @@
*/
#define SPC5_SPI_USE_DSPI1 TRUE
#define SPC5_SPI_USE_DSPI2 TRUE
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
SPC5_MCR_PCSIS1 | \
SPC5_MCR_PCSIS2 | \
SPC5_MCR_PCSIS3 | \
SPC5_MCR_PCSIS4 | \
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI1_DMA_PRIO 10
#define SPC5_SPI_DSPI2_DMA_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10