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STM32: fixed range of PLL2_DIVP and PLL3_DIVP for H7 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14767 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
akscram 2021-09-14 09:43:31 +00:00
parent 3de0c64dd2
commit 537f7aadbe
1 changed files with 2 additions and 2 deletions
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4
os/hal/ports/STM32/STM32H7xx/hal_lld.h
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@ -1764,7 +1764,7 @@
/**
* @brief PLL2 DIVP field.
*/
#if ((STM32_PLL2_DIVP_VALUE >= 2) && (STM32_PLL2_DIVP_VALUE <= 128)) || \
#if ((STM32_PLL2_DIVP_VALUE >= 1) && (STM32_PLL2_DIVP_VALUE <= 128)) || \
defined(__DOXYGEN__)
#define STM32_PLL2_DIVP ((STM32_PLL2_DIVP_VALUE - 1U) << 9U)
#else
@ -1774,7 +1774,7 @@
/**
* @brief PLL3 DIVP field.
*/
#if ((STM32_PLL3_DIVP_VALUE >= 2) && (STM32_PLL3_DIVP_VALUE <= 128)) || \
#if ((STM32_PLL3_DIVP_VALUE >= 1) && (STM32_PLL3_DIVP_VALUE <= 128)) || \
defined(__DOXYGEN__)
#define STM32_PLL3_DIVP ((STM32_PLL3_DIVP_VALUE - 1U) << 9U)
#else