diff --git a/os/hal/ports/STM32/LLD/RCCv2/stm32_csi.inc b/os/hal/ports/STM32/LLD/RCCv2/stm32_csi.inc new file mode 100644 index 000000000..cab747695 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv2/stm32_csi.inc @@ -0,0 +1,109 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_csi.inc + * @brief Shared CSI clock handler. + * + * @addtogroup STM32_CSI_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief CSI clock frequency. + */ +#define STM32_CSICLK 4000000U + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_RCC_HAS_CSI) +#error "STM32_RCC_HAS_CSI not defined in stm32_registry.h" +#endif + +/* Checks on configurations.*/ +#if !defined(STM32_CSI_ENABLED) +#error "STM32_CSI_ENABLED not defined in mcuconf.h" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE void csi_enable(void) { + +#if 0 + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0U) { + /* Waiting for CSI activation.*/ + } +#endif +} + +__STATIC_INLINE void csi_disable(void) { + +#if 0 + RCC->CR &= ~RCC_CR_HSION; +#endif +} + +__STATIC_INLINE void csi_reset(void) { + +#if 0 + /* Making sure HSI is active and ready.*/ + hsi16_enable(); + + /* Clocking from HSI, in case HSI was not the default source.*/ + RCC->CFGR = RCC_CFGR_SW_HSI; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) { + /* Wait until HSI is selected.*/ + } +#endif +} + +__STATIC_INLINE void csi_init(void) { + +#if 0 +#if STM32_CSI_ENABLED + /* HSI activation.*/ + hsi16_enable(); +#endif +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv2/stm32_hse.inc b/os/hal/ports/STM32/LLD/RCCv2/stm32_hse.inc new file mode 100644 index 000000000..f44b5dfe5 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv2/stm32_hse.inc @@ -0,0 +1,131 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv2/stm32_hse.inc + * @brief Shared HSE clock handler. + * + * @addtogroup STM32_HSE_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_RCC_HAS_HSE) +#error "STM32_RCC_HAS_HSE not defined in stm32_registry.h" +#endif + +/* Checks on configurations.*/ +#if !defined(STM32_HSE_ENABLED) +#error "STM32_HSE_ENABLED not defined in mcuconf.h" +#endif + +#if !defined(STM32_HSECLK) +#error "STM32_HSECLK not defined in board.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_HSECLK_MAX) +#error "STM32_HSECLK_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_HSECLK_MIN) +#error "STM32_HSECLK_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_HSECLK_BYP_MAX) +#error "STM32_HSECLK_BYP_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_HSECLK_BYP_MIN) +#error "STM32_HSECLK_BYP_MIN not defined in hal_lld.h" +#endif + +#if STM32_HSE_ENABLED + #if STM32_HSECLK == 0 + #error "HSE frequency not defined" + #else /* STM32_HSECLK != 0 */ + #if defined(STM32_HSE_BYPASS) + #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX) + #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)" + #endif + #else /* !defined(STM32_HSE_BYPASS) */ + #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) + #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" + #endif + #endif /* !defined(STM32_HSE_BYPASS) */ + #endif /* STM32_HSECLK != 0 */ +#endif /* STM32_HSE_ENABLED */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE void hse_enable(void) { + +#if 0 +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass case.*/ + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; +#else + RCC->CR |= RCC_CR_HSEON; +#endif + while ((RCC->CR & RCC_CR_HSERDY) == 0U) { + /* Waiting for HSE activation.*/ + } +#endif +} + +__STATIC_INLINE void hse_disable(void) { + +#if 0 + RCC->CR &= ~RCC_CR_HSEON; +#endif +} + +__STATIC_INLINE void hse_init(void) { + +#if 0 +#if STM32_HSE_ENABLED + hse_enable(); +#endif +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv2/stm32_hsi64.inc b/os/hal/ports/STM32/LLD/RCCv2/stm32_hsi64.inc new file mode 100644 index 000000000..5af8fcb69 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv2/stm32_hsi64.inc @@ -0,0 +1,109 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_hsi64.inc + * @brief Shared HSI64 clock handler. + * + * @addtogroup STM32_HSI64_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief HSI64 clock frequency. + */ +#define STM32_HSI64CLK 64000000U + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_RCC_HAS_HSI64) +#error "STM32_RCC_HAS_HSI64 not defined in stm32_registry.h" +#endif + +/* Checks on configurations.*/ +#if !defined(STM32_HSI64_ENABLED) +#error "STM32_HSI64_ENABLED not defined in mcuconf.h" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE void hsi65_enable(void) { + +#if 0 + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0U) { + /* Waiting for HSI64 activation.*/ + } +#endif +} + +__STATIC_INLINE void hsi16_disable(void) { + +#if 0 + RCC->CR &= ~RCC_CR_HSION; +#endif +} + +__STATIC_INLINE void hsi64_reset(void) { + +#if 0 + /* Making sure HSI is active and ready.*/ + hsi16_enable(); + + /* Clocking from HSI, in case HSI was not the default source.*/ + RCC->CFGR = RCC_CFGR_SW_HSI; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) { + /* Wait until HSI is selected.*/ + } +#endif +} + +__STATIC_INLINE void hsi64_init(void) { + +#if 0 +#if STM32_HSI64_ENABLED + /* HSI activation.*/ + hsi16_enable(); +#endif +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32MP1xx/hal_lld.h b/os/hal/ports/STM32/STM32MP1xx/hal_lld.h index 5b17410ce..ff2f5b87f 100644 --- a/os/hal/ports/STM32/STM32MP1xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32MP1xx/hal_lld.h @@ -91,15 +91,6 @@ #define CLK_ARRAY_SIZE 12U /** @} */ -/** - * @name Internal clocks - * @{ - */ -#define STM32_HSICLK 64000000 -#define STM32_CSICLK 4000000 -#define STM32_LSICLK 32000 -/** @} */ - /** * @name RCC_RCK3SELR register bits definitions * @{ @@ -193,17 +184,41 @@ #define STM32_I2S_CKIN_VALUE 0 #endif +/** + * @brief Enables or disables the HSE clock source. + * @note This initialization is performed only if TZEN=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSI64 clock source. + * @note This initialization is performed only if TZEN=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. + */ +#if !defined(STM32_HSI64_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI64_ENABLED TRUE +#endif + /** * @brief Enables or disables the CSI clock source. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_CSI_ENABLED) || defined(__DOXYGEN__) -#define STM32_CSI_ENABLED FALSE +#define STM32_CSI_ENABLED TRUE #endif /** * @brief Clock source for the PLL3. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_PLL3SRC) || defined(__DOXYGEN__) #define STM32_PLL3SRC STM32_PLL3SRC_HSE @@ -212,7 +227,9 @@ /** * @brief PLL3 M divider value. * @note The allowed values are 1..64. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_PLL3DIVM_VALUE) || defined(__DOXYGEN__) #define STM32_PLL3DIVM_VALUE 3 @@ -221,7 +238,9 @@ /** * @brief PLL3 N multiplier value. * @note The allowed values are 25..200. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_PLL3DIVN_VALUE) || defined(__DOXYGEN__) #define STM32_PLL3DIVN_VALUE 50 @@ -230,7 +249,9 @@ /** * @brief PLL3 P divider value or zero if disabled. * @note The allowed values are 1..128. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_PLL3DIVP_VALUE) || defined(__DOXYGEN__) #define STM32_PLL3DIVP_VALUE 2 @@ -239,7 +260,9 @@ /** * @brief PLL3 Q divider value. * @note The allowed values are 1..128. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_PLL3DIVQ_VALUE) || defined(__DOXYGEN__) #define STM32_PLL3DIVQ_VALUE 4 @@ -248,7 +271,9 @@ /** * @brief PLL3 R divider value. * @note The allowed values are 1..128. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_PLL3DIVR_VALUE) || defined(__DOXYGEN__) #define STM32_PLL3DIVR_VALUE 4 @@ -303,7 +328,9 @@ /** * @brief MCU divider setting. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_MCUDIV) || defined(__DOXYGEN__) #define STM32_MCUDIV 2222222222 @@ -311,7 +338,9 @@ /** * @brief MCU main clock source selection. - * @note This initialization is performed only if TZEN=0 or MCKPROT=0. + * @note This initialization is performed only if TZEN=0 or MCKPROT=0 + * otherwise the setting must match the initialization performed + * on the Cortex-A side. */ #if !defined(STM32_MCUSSRC) || defined(__DOXYGEN__) #define STM32_MCUSSRC 2222222222 @@ -405,6 +434,12 @@ * @{ */ #define STM32_MCUSS_CK_MAX 209000000 + +#define STM32_HSECLK_MAX 48000000 +#define STM32_HSECLK_MIN 8000000 +#define STM32_HSECLK_BYP_MAX 48000000 +#define STM32_HSECLK_BYP_MIN 8000000 + #define STM32_PLL3INCLK_MAX 16000000 #define STM32_PLL3INCLK_MIN 4000000 #define STM32_PLL3INCLK_SD_MIN 8000000 @@ -443,8 +478,9 @@ #endif /* Clock handlers.*/ -//#include "stm32_csi.inc" -//#include "stm32_hsi64.inc" +#include "stm32_csi.inc" +#include "stm32_hsi64.inc" +#include "stm32_hse.inc" /* * CSI related checks. @@ -469,7 +505,7 @@ * @brief PLL3 input clock frequency. */ #if (STM32_PLL3SRC == STM32_PLL3SRC_HSI) || defined(__DOXYGEN__) - #define STM32_PLL3MCLK STM32_HSICLK + #define STM32_PLL3MCLK STM32_HSI64CLK #elif STM32_PLL3SRC == STM32_PLL3SRC_HSE #define STM32_PLL3MCLK STM32_HSECLK @@ -539,7 +575,7 @@ * @brief PLL4 input clock frequency. */ #if (STM32_PLL4SRC == STM32_PLL4SRC_HSI) || defined(__DOXYGEN__) - #define STM32_PLL4MCLK STM32_HSICLK + #define STM32_PLL4MCLK STM32_HSI64CLK #elif STM32_PLL4SRC == STM32_PLL4SRC_HSE #define STM32_PLL4MCLK STM32_HSECLK diff --git a/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h b/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h index c13b2d2c7..2b58a945c 100644 --- a/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h @@ -53,6 +53,9 @@ defined(__DOXYGEN__) /* RCC attributes.*/ +#define STM32_RCC_HAS_CSI TRUE +#define STM32_RCC_HAS_HSI64 TRUE +#define STM32_RCC_HAS_HSE TRUE #define STM32_RCC_HAS_PLL3 TRUE #define STM32_RCC_PLL3_HAS_P TRUE #define STM32_RCC_PLL3_HAS_Q TRUE