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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1916 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-05-14 06:43:02 +00:00
parent fee7253047
commit 55b7744199
11 changed files with 73 additions and 22 deletions
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6
boards/ST_STM3210C_EVAL/board.c
View File

@ -42,6 +42,12 @@ void hwinit1(void) {
*/
halInit();
/*
* Remap USART2 to the PD5/PD6 pins, done after halInit since HAL resets
* these.
*/
AFIO->MAPR |= AFIO_MAPR_USART2_REMAP;
/*
* ChibiOS/RT initialization.
*/

36
boards/ST_STM3210C_EVAL/board.h
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@ -38,7 +38,7 @@
/*
* MCU type, this macro is used by both the ST library and the ChibiOS/RT
* native STM32 HAL.
* native STM32 HAL.
*/
#define STM32F10X_CL
@ -73,41 +73,45 @@
/*
* Port A setup.
* Everything input with pull-up except:
* Everything input except:
*/
#define VAL_GPIOACRL 0x88888888 /* PA7...PA0 */
#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */
#define VAL_GPIOACRL 0x44444444 /* PA7...PA0 */
#define VAL_GPIOACRH 0x44444444 /* PA15...PA8 */
#define VAL_GPIOAODR 0xFFFFFFFF
/*
* Port B setup.
* Everything input with pull-up except:
* Everything input except:
*/
#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
#define VAL_GPIOBCRL 0x44444444 /* PB7...PB0 */
#define VAL_GPIOBCRH 0x44444444 /* PB15...PB8 */
#define VAL_GPIOBODR 0xFFFFFFFF
/*
* Port C setup.
* Everything input with pull-up except:
* Everything input except:
*/
#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */
#define VAL_GPIOCCRH 0x88888888 /* PC15...PC8 */
#define VAL_GPIOCCRL 0x44444444 /* PC7...PC0 */
#define VAL_GPIOCCRH 0x44444444 /* PC15...PC8 */
#define VAL_GPIOCODR 0xFFFFFFFF
/*
* Port D setup.
* Everything input with pull-up except:
* Everything input except:
* PD5 - USART2TX (remapped) AF PP Output
* PD6 - USART2RX (remapped) Digital Input
* PD7 - LED (LD1) PP Output
*/
#define VAL_GPIODCRL 0x88888888 /* PD7...PD0 */
#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */
#define VAL_GPIODODR 0xFFFFFFFF
#define VAL_GPIODCRL 0x34B44444 /* PD7...PD0 */
#define VAL_GPIODCRH 0x44444444 /* PD15...PD8 */
#define VAL_GPIODODR 0x0F0FFFFF
/*
* Port E setup.
* Everything input except:
*/
#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */
#define VAL_GPIOECRL 0x44444444 /* PE7...PE0 */
#define VAL_GPIOECRH 0x44444444 /* PE15...PE8 */
#define VAL_GPIOEODR 0xFFFFFFFF
#endif /* _BOARD_H_ */

1
demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h
View File

@ -42,6 +42,7 @@
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCO STM32_MCO_NOCLOCK
/*
* ADC driver system settings.

1
demos/ARMCM3-STM32F103-GCC/mcuconf.h
View File

@ -42,6 +42,7 @@
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCO STM32_MCO_NOCLOCK
/*
* ADC driver system settings.

8
demos/ARMCM3-STM32F107-GCC/main.c
View File

@ -29,9 +29,9 @@ static msg_t Thread1(void *arg) {
(void)arg;
while (TRUE) {
// palClearPad(IOPORT3, GPIOC_LED);
palClearPad(IOPORT4, 7);
chThdSleepMilliseconds(500);
// palSetPad(IOPORT3, GPIOC_LED);
palSetPad(IOPORT4, 7);
chThdSleepMilliseconds(500);
}
return 0;
@ -61,8 +61,8 @@ int main(int argc, char **argv) {
* sleeping in a loop and check the button state.
*/
while (TRUE) {
// if (palReadPad(IOPORT1, GPIOA_BUTTON))
// TestThread(&SD2);
if (palReadPad(IOPORT2, 9) == 0)
TestThread(&SD2);
chThdSleepMilliseconds(500);
}
return 0;

1
demos/ARMCM3-STM32F107-GCC/mcuconf.h
View File

@ -45,6 +45,7 @@
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCO STM32_MCO_NOCLOCK
/*
* ADC driver system settings.

9
os/hal/platforms/STM32/hal_lld.c
View File

@ -126,7 +126,7 @@ void stm32_clock_init(void) {
#endif
/* Clock settings.*/
RCC->CFGR = STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup and final clock selection. */
@ -184,6 +184,13 @@ void stm32_clock_init(void) {
; /* Waits until PLL2 is stable. */
#endif
/* Clock settings.*/
RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
/* Switching on the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */

17
os/hal/platforms/STM32/hal_lld_F107.h
View File

@ -74,6 +74,16 @@
#define STM32_OTGFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */
#define STM32_OTGFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */
#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define STM32_MCO_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */
#define STM32_MCO_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */
#define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
#define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
/* RCC_CFGR2 register bits definitions.*/
#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */
#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */
@ -188,6 +198,13 @@
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#endif
/**
* @brief MCO pin setting.
*/
#if !defined(STM32_MCO) || defined(__DOXYGEN__)
#define STM32_MCO STM32_MCO_NOCLOCK
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

13
os/hal/platforms/STM32/hal_lld_F10x.h
View File

@ -73,6 +73,12 @@
#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -150,6 +156,13 @@
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#endif
/**
* @brief MCO pin setting.
*/
#if !defined(STM32_MCO) || defined(__DOXYGEN__)
#define STM32_MCO STM32_MCO_NOCLOCK
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

2
os/hal/platforms/STM32/pal_lld.c
View File

@ -46,7 +46,7 @@
RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
#else
/* Defaults on Medium Density devices.*/
/* Defaults on Medium Density and Connection Line devices.*/
#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_AFIORST);

1
testhal/STM32/mcuconf.h
View File

@ -42,6 +42,7 @@
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCO STM32_MCO_NOCLOCK
/*
* ADC driver system settings.