git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1916 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -42,6 +42,12 @@ void hwinit1(void) {
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*/
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halInit();
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/*
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* Remap USART2 to the PD5/PD6 pins, done after halInit since HAL resets
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* these.
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*/
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AFIO->MAPR |= AFIO_MAPR_USART2_REMAP;
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/*
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* ChibiOS/RT initialization.
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*/
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@ -73,41 +73,45 @@
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/*
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* Port A setup.
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* Everything input with pull-up except:
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* Everything input except:
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*/
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#define VAL_GPIOACRL 0x88888888 /* PA7...PA0 */
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#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */
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#define VAL_GPIOACRL 0x44444444 /* PA7...PA0 */
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#define VAL_GPIOACRH 0x44444444 /* PA15...PA8 */
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#define VAL_GPIOAODR 0xFFFFFFFF
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/*
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* Port B setup.
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* Everything input with pull-up except:
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* Everything input except:
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*/
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#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
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#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
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#define VAL_GPIOBCRL 0x44444444 /* PB7...PB0 */
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#define VAL_GPIOBCRH 0x44444444 /* PB15...PB8 */
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#define VAL_GPIOBODR 0xFFFFFFFF
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/*
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* Port C setup.
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* Everything input with pull-up except:
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* Everything input except:
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*/
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#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */
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#define VAL_GPIOCCRH 0x88888888 /* PC15...PC8 */
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#define VAL_GPIOCCRL 0x44444444 /* PC7...PC0 */
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#define VAL_GPIOCCRH 0x44444444 /* PC15...PC8 */
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#define VAL_GPIOCODR 0xFFFFFFFF
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/*
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* Port D setup.
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* Everything input with pull-up except:
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* Everything input except:
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* PD5 - USART2TX (remapped) AF PP Output
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* PD6 - USART2RX (remapped) Digital Input
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* PD7 - LED (LD1) PP Output
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*/
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#define VAL_GPIODCRL 0x88888888 /* PD7...PD0 */
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#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */
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#define VAL_GPIODODR 0xFFFFFFFF
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#define VAL_GPIODCRL 0x34B44444 /* PD7...PD0 */
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#define VAL_GPIODCRH 0x44444444 /* PD15...PD8 */
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#define VAL_GPIODODR 0x0F0FFFFF
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/*
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* Port E setup.
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* Everything input except:
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*/
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#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
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#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */
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#define VAL_GPIOECRL 0x44444444 /* PE7...PE0 */
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#define VAL_GPIOECRH 0x44444444 /* PE15...PE8 */
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#define VAL_GPIOEODR 0xFFFFFFFF
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#endif /* _BOARD_H_ */
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@ -42,6 +42,7 @@
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCO STM32_MCO_NOCLOCK
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/*
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* ADC driver system settings.
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@ -42,6 +42,7 @@
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCO STM32_MCO_NOCLOCK
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/*
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* ADC driver system settings.
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@ -29,9 +29,9 @@ static msg_t Thread1(void *arg) {
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(void)arg;
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while (TRUE) {
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// palClearPad(IOPORT3, GPIOC_LED);
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palClearPad(IOPORT4, 7);
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chThdSleepMilliseconds(500);
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// palSetPad(IOPORT3, GPIOC_LED);
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palSetPad(IOPORT4, 7);
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chThdSleepMilliseconds(500);
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}
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return 0;
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@ -61,8 +61,8 @@ int main(int argc, char **argv) {
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* sleeping in a loop and check the button state.
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*/
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while (TRUE) {
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// if (palReadPad(IOPORT1, GPIOA_BUTTON))
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// TestThread(&SD2);
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if (palReadPad(IOPORT2, 9) == 0)
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TestThread(&SD2);
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chThdSleepMilliseconds(500);
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}
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return 0;
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@ -45,6 +45,7 @@
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCO STM32_MCO_NOCLOCK
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/*
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* ADC driver system settings.
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@ -126,7 +126,7 @@ void stm32_clock_init(void) {
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#endif
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/* Clock settings.*/
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RCC->CFGR = STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
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RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
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STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* Flash setup and final clock selection. */
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@ -184,6 +184,13 @@ void stm32_clock_init(void) {
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; /* Waits until PLL2 is stable. */
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#endif
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/* Clock settings.*/
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RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
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STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* Flash setup and final clock selection. */
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FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
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/* Switching on the configured clock source if it is different from HSI.*/
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#if (STM32_SW != STM32_SW_HSI)
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RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
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@ -74,6 +74,16 @@
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#define STM32_OTGFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */
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#define STM32_OTGFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */
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#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
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#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
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#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
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#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
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#define STM32_MCO_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */
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#define STM32_MCO_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */
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#define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
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#define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
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/* RCC_CFGR2 register bits definitions.*/
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#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */
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#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */
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@ -188,6 +198,13 @@
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#endif
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/**
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* @brief MCO pin setting.
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*/
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#if !defined(STM32_MCO) || defined(__DOXYGEN__)
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#define STM32_MCO STM32_MCO_NOCLOCK
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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@ -73,6 +73,12 @@
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#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
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#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
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#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
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#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
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#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
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#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#endif
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/**
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* @brief MCO pin setting.
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*/
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#if !defined(STM32_MCO) || defined(__DOXYGEN__)
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#define STM32_MCO STM32_MCO_NOCLOCK
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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@ -46,7 +46,7 @@
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
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RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
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#else
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/* Defaults on Medium Density devices.*/
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/* Defaults on Medium Density and Connection Line devices.*/
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#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
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RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
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RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_AFIORST);
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#define STM32_MCO STM32_MCO_NOCLOCK
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/*
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* ADC driver system settings.
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