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merged RX stuff 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6831 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
lbednarz 2014-04-02 18:26:14 +00:00
parent 6a62119514
commit 56f18ed54d
68 changed files with 20809 additions and 1 deletions
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80
boards/RENESAS_RPBRX62N/board.c Normal file
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
#if HAL_USE_PAL || defined(__DOXYGEN__)
const PALConfig pal_default_config = {
{VAL_PORT0DATA, VAL_PORT0DIR, VAL_PORT0ICR, VAL_PORT0ODR, 0},
{VAL_PORT1DATA, VAL_PORT1DIR, VAL_PORT1ICR, VAL_PORT1ODR, 0},
{VAL_PORT2DATA, VAL_PORT2DIR, VAL_PORT2ICR, VAL_PORT2ODR, 0},
{VAL_PORT3DATA, VAL_PORT3DIR, VAL_PORT3ICR, VAL_PORT3ODR, 0},
{VAL_PORT4DATA, VAL_PORT4DIR, VAL_PORT4ICR, 0 , 0},
{VAL_PORT5DATA, VAL_PORT5DIR, VAL_PORT5ICR, 0 , 0},
{VAL_PORTADATA, VAL_PORTADIR, VAL_PORTAICR, 0 , VAL_PORTAPCR},
{VAL_PORTBDATA, VAL_PORTBDIR, VAL_PORTBICR, 0 , VAL_PORTBPCR},
{VAL_PORTCDATA, VAL_PORTCDIR, VAL_PORTCICR, VAL_PORTCODR, VAL_PORTCPCR},
{VAL_PORTDDATA, VAL_PORTDDIR, VAL_PORTDICR, 0 , VAL_PORTDPCR},
{VAL_PORTEDATA, VAL_PORTEDIR, VAL_PORTEICR, 0 , VAL_PORTEPCR},
};
#endif
/**
* @brief CMT3 interrupt handler.
*/
CH_IRQ_HANDLER(Excep_CMTU1_CMT3) {
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
rx62n_clock_init();
}
/*
* Board-specific initialization code.
*/
void boardInit(void) {
/* Setup tick timer */
MSTP(CMT3) = 0; /* Enable CMT3 timer (cancel module stop state) */
CMT.CMSTR1.BIT.STR3 = 0; /* Stop timer */
CMT3.CMCR.BIT.CKS = 2; /* PCLK/128 */
CMT3.CMCNT = 0;
CMT3.CMCOR = RX62N_PERCLK / 128 / CH_FREQUENCY;
CMT3.CMCR.BIT.CMIE = 1; /* Enable compare match interrupts */
IEN(CMT3,CMI3) = 1; /* Set Interrupt Enable Register */
IPR(CMT3,CMI3) = 8; /* Setup interrupt priority */
CMT.CMSTR1.BIT.STR3 = 1; /* Start timer */
}

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boards/RENESAS_RPBRX62N/board.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Renesas RPBRX62N board
*/
/*
* Board identifiers.
*/
#define BOARD_RPBRX62N
#define BOARD_NAME "Renesas RPBRX62N"
/*
* Board frequencies.
*/
#define EXTALCLK 12000000
#define SUBCLK 32768
/*
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
*/
#define RX62NXBDFP
/* TODO: move this to hal/include/mii.h */
#define MII_LAN8700_ID 0x0007C0C4
/*
* Ethernet PHY type.
*/
#define BOARD_PHY_ID MII_LAN8700_ID
/*
* Ethernet PHY address.
*/
#define BOARD_PHY_ADDRESS 31
#define RX62N_MAC_PHY_TIMEOUT 0
/*
* Use ethernet PHY RMII interface (if defined).
*/
/*#define BOARD_PHY_RMII*/
/*
* Ethernet PHY hardware reset
* PORTA_ETH_RESETOUT must be held low for at least 100us.
*/
#define BOARD_PHY_RESET() do { \
palClearPad(GPIO10, PORTA_ETH_RESETOUT); \
asm volatile ("mov.l #2640,r2 \n\t" \
"1: \n\t" \
"sub #1,r2 \n\t" \
"bne.b 1b \n\t"); \
palSetPad(GPIO10, PORTA_ETH_RESETOUT); \
} while(0)
/*
* PORT 0 initial setup.
*/
#define VAL_PORT0DIR 0x00
#define VAL_PORT0DATA 0x00
#define VAL_PORT0ICR 0x00
#define VAL_PORT0ODR 0x00
/*
* PORT 1 initial setup.
*/
#define VAL_PORT1DIR 0x00
#define VAL_PORT1DATA 0x00
#define VAL_PORT1ICR 0x00
#define VAL_PORT1ODR 0x00
/*
* PORT 2 initial setup.
*/
#define VAL_PORT2DIR 0x00
#define VAL_PORT2DATA 0x00
#define VAL_PORT2ICR 0x00
#define VAL_PORT2ODR 0x00
/*
* PORT 3 initial setup.
*/
#define VAL_PORT3DIR 0x00
#define VAL_PORT3DATA 0x00
#define VAL_PORT3ICR 0x00
#define VAL_PORT3ODR 0x00
/*
* PORT 4 initial setup.
*/
#define VAL_PORT4DIR 0x00
#define VAL_PORT4DATA 0x00
#define VAL_PORT4ICR 0x00
/*
* PORT 5 initial setup.
*/
#define VAL_PORT5DIR 0x00
#define VAL_PORT5DATA 0x00
#define VAL_PORT5ICR 0x00
/*
* GPIO A initial setup.
*/
#define VAL_PORTADIR PAL_PORT_BIT(PORTA_LED0) | \
PAL_PORT_BIT(PORTA_LED1) | \
PAL_PORT_BIT(PORTA_LED2) | \
PAL_PORT_BIT(PORTA_MII_MDIO) | \
PAL_PORT_BIT(PORTA_MII_MDC) | \
PAL_PORT_BIT(PORTA_ETH_LINKSTA) | \
PAL_PORT_BIT(PORTA_ETH_RESETOUT)
#define VAL_PORTADATA PAL_PORT_BIT(PORTA_LED0) | \
PAL_PORT_BIT(PORTA_LED1) | \
PAL_PORT_BIT(PORTA_LED2) | \
PAL_PORT_BIT(PORTA_ETH_RESETOUT)
#define VAL_PORTAICR PAL_PORT_BIT(PORTA_MII_MDIO) | \
PAL_PORT_BIT(PORTA_ETH_LINKSTA)
#define VAL_PORTAPCR 0x00
/*
* PORT B initial setup.
*/
#define VAL_PORTBDIR PAL_PORT_BIT(PORTB_MII_TXD1) | \
PAL_PORT_BIT(PORTB_MII_TXD0) | \
PAL_PORT_BIT(PORTB_MII_TXEN)
#define VAL_PORTBDATA 0x00
#define VAL_PORTBICR PAL_PORT_BIT(PORTB_MII_CRS) | \
PAL_PORT_BIT(PORTB_MII_RXER) | \
PAL_PORT_BIT(PORTB_MII_RXCLK) | \
PAL_PORT_BIT(PORTB_MII_RXD0) | \
PAL_PORT_BIT(PORTB_MII_RXD1)
#define VAL_PORTBPCR 0x00
/*
* PORT C initial setup.
*/
#define VAL_PORTCDIR PAL_PORT_BIT(PORTC_MII_TXD3) | \
PAL_PORT_BIT(PORTC_MII_TXD2) | \
PAL_PORT_BIT(PORTC_MII_TXER)
#define VAL_PORTCDATA 0x00
#define VAL_PORTCICR PAL_PORT_BIT(PORTC_MII_COL) | \
PAL_PORT_BIT(PORTC_MII_TXCLK) | \
PAL_PORT_BIT(PORTC_MII_TXER) | \
PAL_PORT_BIT(PORTC_MII_RXDV) | \
PAL_PORT_BIT(PORTC_MII_RXD2) | \
PAL_PORT_BIT(PORTC_MII_RXD3)
#define VAL_PORTCODR 0x00
#define VAL_PORTCPCR 0x00
/*
* PORT D initial setup.
*/
#define VAL_PORTDDIR 0x00
#define VAL_PORTDDATA 0x00
#define VAL_PORTDICR 0x00
#define VAL_PORTDPCR 0x00
/*
* PORT E initial setup.
*/
#define VAL_PORTEDIR 0x00
#define VAL_PORTEDATA 0x00
#define VAL_PORTEICR 0x00
#define VAL_PORTEPCR 0x00
/*
* Pin definitions.
*/
#define PORTA_ETH_RESETOUT 7
#define PORTA_ETH_LINKSTA 5
#define PORTA_MII_MDC 4
#define PORTA_MII_MDIO 3
#define PORTA_LED0 2
#define PORTA_LED1 1
#define PORTA_LED2 0
#define PORTB_MII_CRS 7
#define PORTB_MII_TXD1 6
#define PORTB_MII_TXD0 5
#define PORTB_MII_TXEN 4
#define PORTB_MII_RXER 3
#define PORTB_MII_RXCLK 2
#define PORTB_MII_RXD0 1
#define PORTB_MII_RXD1 0
#define PORTC_MII_COL 7
#define PORTC_MII_TXD3 6
#define PORTC_MII_TXD2 5
#define PORTC_MII_TXCLK 4
#define PORTC_MII_TXER 3
#define PORTC_MII_RXDV 2
#define PORTC_MII_RXD2 1
#define PORTC_MII_RXD3 0
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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demos/RX-RX62N-RPB-MAC/bin/Release_ram/!prog.bat Normal file
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@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V442a
jlink.exe r5f562n8bdfp_ram_wr.script

3
demos/RX-RX62N-RPB-MAC/bin/Release_ram/!rd.bat Normal file
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@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V442a
jlink.exe r5f562n8bdfp_rd.script

3
demos/RX-RX62N-RPB-MAC/bin/Release_ram/!rst.bat Normal file
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@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V432b
jlink.exe reset.script

3
demos/RX-RX62N-RPB-MAC/bin/Release_ram/lss.bat Normal file
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@echo off
set path="d:\Program Files\KPIT\GNURX\rx-elf\rx-elf\bin"
rx-elf-objdump -h -S rx62n_demo.exe >rx62n_demo.lss

6
demos/RX-RX62N-RPB-MAC/bin/Release_ram/r5f562n8bdfp_ram_wr.script Normal file
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exec device = RX62N
speed auto
loadbin rx62n_demo.bin, 0x00000000
r
g
q

6
demos/RX-RX62N-RPB-MAC/bin/Release_ram/r5f562n8bdfp_rd.script Normal file
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exec device = RX62N
speed auto
savebin ram_dump.bin, 0x00000000, 0x18000
r
g
q

5
demos/RX-RX62N-RPB-MAC/bin/Release_ram/reset.script Normal file
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exec device = RX62N
speed auto
r
g
q

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demos/RX-RX62N-RPB-MAC/bin/Release_ram/rx62n_demo_vectors_0xFFFFFF80.bin Normal file
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demos/RX-RX62N-RPB-MAC/chconf.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC TRUE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 115200
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#include "chprintf.h"
#include "lwipthread.h"
#include "web/web.h"
static WORKING_AREA(waThread1, 128);
static msg_t Thread1(void *arg) {
while (TRUE) {
palClearPad(GPIO10, PORTA_LED0);
chThdSleepMilliseconds(50);
palClearPad(GPIO10, PORTA_LED1);
chThdSleepMilliseconds(50);
palClearPad(GPIO10, PORTA_LED2);
palSetPad(GPIO10, PORTA_LED0);
chThdSleepMilliseconds(50);
palSetPad(GPIO10, PORTA_LED1);
chThdSleepMilliseconds(50);
palSetPad(GPIO10, PORTA_LED2);
chThdSleepMilliseconds(50);
chThdSleepMilliseconds(400);
}
return 0;
}
/*===========================================================================*/
/* Main and generic code. */
/*===========================================================================*/
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
/*
* Starts the LED blinker thread.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
/*
* Creates the LWIP threads (it changes priority internally).
*/
chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1,
lwip_thread, NULL);
/*
* Creates the HTTP thread (it changes priority internally).
*/
chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
http_server, NULL);
chprintf((BaseSequentialStream *)&SD1, "\r\nRX62N Ethernet demo.\r\n");
/*
* Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop and listen for events.
*/
while (TRUE) {
chThdSleepMilliseconds(1000);
}
return 0;
}

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* RX62N drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the driver
* is enabled in halconf.h.
*/
/*
* HAL driver system settings.
*/
#define RX62N_ICLK_MUL 8
#define RX62N_PCLK_MUL 4
#define RX62N_BCLK_MUL 1
#define RX62N_SDCLK_OUTPUT_ENABLED FALSE
#define RX62N_BCLK_OUTPUT_ENABLED FALSE
/*
* ADC driver system settings.
*/
/*
* CAN driver system settings.
*/
/*
* MAC driver system settings.
*/
#define RX62N_MAC_ETH1_IRQ_PRIORITY 5
/*
* PWM driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define RX62N_SERIAL_USE_UART0 TRUE
#define RX62N_SERIAL_UART0_IRQ_PRIORITY 3
#define RX62N_SERIAL_USE_UART1 FALSE
/*
* SPI driver system settings.
*/
/*
* USB driver system settings.
*/
#define RX62N_USE_USB0 FALSE
#define RX62N_USB0_IRQ_PRIORITY 7

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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<CodeBlocks_project_file>
<FileVersion major="1" minor="6" />
<Project>
<Option title="rx62n_demo" />
<Option pch_mode="2" />
<Option compiler="kpit_rx_gcc_compiler" />
<Build>
<Target title="Release_ram">
<Option output="bin/Release_ram/rx62n_demo" prefix_auto="1" extension_auto="1" />
<Option object_output="obj/Release_ram/" />
<Option type="1" />
<Option compiler="kpit_rx_gcc_compiler" />
<Compiler>
<Add option="-O2" />
<Add option="-nofpu" />
<Add option="-DRAMRUN=1" />
</Compiler>
<Linker>
<Add option="-T../../os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld" />
<Add option="-nostdlib" />
<Add library="c" />
<Add library="m" />
<Add directory="d:/Program Files/KPIT/GNURXv12.03-ELF/rx-elf/rx-elf/rx-elf/lib/no-fpu-libs" />
<Add directory="d:/Program Files/KPIT/GNURXv12.03-ELF/rx-elf/rx-elf/lib/gcc/rx-elf/4.7-GNURX_v12.03/no-fpu-libs" />
</Linker>
<ExtraCommands>
<Add after="rx-elf-objcopy -O binary -R fvectors $(TARGET_OUTPUT_FILE) $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).bin" />
<Add after="rx-elf-objcopy -O binary -j fvectors $(TARGET_OUTPUT_FILE) $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME)_vectors_0xFFFFFF80.bin" />
<Add after="rx-elf-size $(TARGET_OUTPUT_FILE)" />
<Mode after="always" />
</ExtraCommands>
</Target>
</Build>
<Compiler>
<Add option="-fomit-frame-pointer" />
<Add option="-O2" />
<Add option="-Wall" />
<Add option="-std=gnu99" />
<Add option="-funsigned-char" />
<Add option="-fshort-enums" />
<Add option="-Wswitch" />
<Add option="-Wunused-variable" />
<Add option="-Wno-pointer-sign" />
<Add option="-ffunction-sections" />
<Add option="-mcpu=rx600" />
<Add option="-mlittle-endian-data" />
<Add option="-D__RX_LITTLE_ENDIAN__=1" />
<Add directory="." />
<Add directory="../../os/kernel/include" />
<Add directory="../../os/ports/GCC/RX" />
<Add directory="../../os/ports/GCC/RX/RX62N" />
<Add directory="../../boards/RPBRX62N" />
<Add directory="../../os/hal/include" />
<Add directory="../../os/hal/platforms/RX62N" />
<Add directory="../../boards/RENESAS_RPBRX62N" />
<Add directory="../../test" />
<Add directory="../../os/various" />
<Add directory="../../ext/lwip/src/include" />
<Add directory="../../ext/lwip/src/include/ipv4" />
<Add directory="../../os/various/lwip_bindings" />
<Add directory="../../os/various/lwip_bindings/arch" />
</Compiler>
<Linker>
<Add option="-Wl,-Map=obj\map.txt" />
<Add option="-nostartfiles" />
<Add option="-Wl,--relax" />
<Add option="-Wl,--gc-sections" />
</Linker>
<Unit filename="../../boards/RENESAS_RPBRX62N/board.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../boards/RENESAS_RPBRX62N/board.h" />
<Unit filename="../../ext/lwip/src/api/api_lib.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/api/api_msg.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/api/err.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/api/netbuf.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/api/netdb.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/api/netifapi.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/api/sockets.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/api/tcpip.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/def.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/dhcp.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/dns.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/init.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/ipv4/autoip.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/ipv4/icmp.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/ipv4/igmp.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/ipv4/inet.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/ipv4/inet_chksum.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/ipv4/ip.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/ipv4/ip_addr.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/ipv4/ip_frag.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/mem.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/memp.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/netif.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/pbuf.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/raw.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/stats.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/sys.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/tcp.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/tcp_in.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/tcp_out.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/timers.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/core/udp.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/netif/etharp.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../ext/lwip/src/netif/ethernetif.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/include/hal.h" />
<Unit filename="../../os/hal/include/mac.h" />
<Unit filename="../../os/hal/include/mii.h" />
<Unit filename="../../os/hal/include/pal.h" />
<Unit filename="../../os/hal/platforms/Rx62n/hal_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/hal_lld.h" />
<Unit filename="../../os/hal/platforms/Rx62n/iodefine_gcc62n.h" />
<Unit filename="../../os/hal/platforms/Rx62n/mac_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/mac_lld.h" />
<Unit filename="../../os/hal/platforms/Rx62n/pal_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/pal_lld.h" />
<Unit filename="../../os/hal/platforms/Rx62n/rx62n_mii.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/rx62n_mii.h" />
<Unit filename="../../os/hal/platforms/Rx62n/serial_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/serial_lld.h" />
<Unit filename="../../os/hal/src/hal.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/src/mac.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/src/pal.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/src/serial.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/include/ch.h" />
<Unit filename="../../os/kernel/include/chbsem.h" />
<Unit filename="../../os/kernel/include/chcond.h" />
<Unit filename="../../os/kernel/include/chdebug.h" />
<Unit filename="../../os/kernel/include/chdynamic.h" />
<Unit filename="../../os/kernel/include/chevents.h" />
<Unit filename="../../os/kernel/include/chfiles.h" />
<Unit filename="../../os/kernel/include/chheap.h" />
<Unit filename="../../os/kernel/include/chinline.h" />
<Unit filename="../../os/kernel/include/chlists.h" />
<Unit filename="../../os/kernel/include/chmboxes.h" />
<Unit filename="../../os/kernel/include/chmemcore.h" />
<Unit filename="../../os/kernel/include/chmempools.h" />
<Unit filename="../../os/kernel/include/chmsg.h" />
<Unit filename="../../os/kernel/include/chmtx.h" />
<Unit filename="../../os/kernel/include/chqueues.h" />
<Unit filename="../../os/kernel/include/chregistry.h" />
<Unit filename="../../os/kernel/include/chschd.h" />
<Unit filename="../../os/kernel/include/chsem.h" />
<Unit filename="../../os/kernel/include/chstreams.h" />
<Unit filename="../../os/kernel/include/chsys.h" />
<Unit filename="../../os/kernel/include/chthreads.h" />
<Unit filename="../../os/kernel/include/chvt.h" />
<Unit filename="../../os/kernel/src/chcond.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chdebug.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chdynamic.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chevents.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chheap.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chlists.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmboxes.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmemcore.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmempools.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmsg.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmtx.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chqueues.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chregistry.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chschd.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chsem.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chsys.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chthreads.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chvt.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld" />
<Unit filename="../../os/ports/GCC/RX/RX62N/rxparams.h" />
<Unit filename="../../os/ports/GCC/RX/RX62N/vectors.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/ports/GCC/RX/chcore.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/ports/GCC/RX/chcore.h" />
<Unit filename="../../os/ports/GCC/RX/chtypes.h" />
<Unit filename="../../os/ports/GCC/RX/crt0.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/various/chprintf.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/various/chprintf.h" />
<Unit filename="../../os/various/evtimer.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/various/evtimer.h" />
<Unit filename="../../os/various/lwip_bindings/arch/cc.h" />
<Unit filename="../../os/various/lwip_bindings/arch/perf.h" />
<Unit filename="../../os/various/lwip_bindings/arch/sys_arch.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/various/lwip_bindings/arch/sys_arch.h" />
<Unit filename="../../os/various/lwip_bindings/lwipthread.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/various/lwip_bindings/lwipthread.h" />
<Unit filename="chconf.h" />
<Unit filename="halconf.h" />
<Unit filename="lwipopts.h" />
<Unit filename="main.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="mcuconf.h" />
<Unit filename="web/web.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="web/web.h" />
<Extensions>
<code_completion />
<envvars />
<debugger />
<lib_finder disable_auto="1" />
<DoxyBlocks>
<comment_style block="0" line="0" />
<doxyfile_project />
<doxyfile_build />
<doxyfile_warnings />
<doxyfile_output />
<doxyfile_dot />
<general />
</DoxyBlocks>
</Extensions>
</Project>
</CodeBlocks_project_file>

121
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@ -0,0 +1,121 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file is a modified version of the lwIP web server demo. The original
* author is unknown because the file didn't contain any license information.
*/
/**
* @file web.c
* @brief HTTP server wrapper thread code.
* @addtogroup WEB_THREAD
* @{
*/
#include "ch.h"
#include "lwip/opt.h"
#include "lwip/arch.h"
#include "lwip/api.h"
#include "web.h"
#if LWIP_NETCONN
static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
static const char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
static void http_server_serve(struct netconn *conn) {
struct netbuf *inbuf;
char *buf;
u16_t buflen;
err_t err;
/* Read the data from the port, blocking if nothing yet there.
We assume the request (the part we care about) is in one netbuf */
err = netconn_recv(conn, &inbuf);
if (err == ERR_OK) {
netbuf_data(inbuf, (void **)&buf, &buflen);
/* Is this an HTTP GET command? (only check the first 5 chars, since
there are other formats for GET, and we're keeping it very simple )*/
if (buflen>=5 &&
buf[0]=='G' &&
buf[1]=='E' &&
buf[2]=='T' &&
buf[3]==' ' &&
buf[4]=='/' ) {
/* Send the HTML header
* subtract 1 from the size, since we dont send the \0 in the string
* NETCONN_NOCOPY: our data is const static, so no need to copy it
*/
netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
/* Send our HTML page */
netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
}
}
/* Close the connection (server closes in HTTP) */
netconn_close(conn);
/* Delete the buffer (netconn_recv gives us ownership,
so we have to make sure to deallocate the buffer) */
netbuf_delete(inbuf);
}
/**
* Stack area for the http thread.
*/
WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
/**
* HTTP server thread.
*/
msg_t http_server(void *p) {
struct netconn *conn, *newconn;
err_t err;
(void)p;
/* Create a new TCP connection handle */
conn = netconn_new(NETCONN_TCP);
LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;);
/* Bind to port 80 (HTTP) with default IP address */
netconn_bind(conn, NULL, WEB_THREAD_PORT);
/* Put the connection into LISTEN state */
netconn_listen(conn);
/* Goes to the final priority after initialization.*/
chThdSetPriority(WEB_THREAD_PRIORITY);
while(1) {
err = netconn_accept(conn, &newconn);
if (err != ERR_OK)
continue;
http_server_serve(newconn);
netconn_delete(newconn);
}
return RDY_OK;
}
#endif /* LWIP_NETCONN */
/** @} */

51
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file web.h
* @brief HTTP server wrapper thread macros and structures.
* @addtogroup WEB_THREAD
* @{
*/
#ifndef _WEB_H_
#define _WEB_H_
#ifndef WEB_THREAD_STACK_SIZE
#define WEB_THREAD_STACK_SIZE 1024
#endif
#ifndef WEB_THREAD_PORT
#define WEB_THREAD_PORT 80
#endif
#ifndef WEB_THREAD_PRIORITY
#define WEB_THREAD_PRIORITY (LOWPRIO + 2)
#endif
extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
#ifdef __cplusplus
extern "C" {
#endif
msg_t http_server(void *p);
#ifdef __cplusplus
}
#endif
#endif /* _WEB_H_ */
/** @} */

3
demos/RX-RX62N-RPB-USB/bin/Release_ram/!prog.bat Normal file
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@ -0,0 +1,3 @@
@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V442a
jlink.exe r5f562n8bdfp_ram_wr.script

3
demos/RX-RX62N-RPB-USB/bin/Release_ram/!rd.bat Normal file
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@ -0,0 +1,3 @@
@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V442a
jlink.exe r5f562n8bdfp_rd.script

3
demos/RX-RX62N-RPB-USB/bin/Release_ram/!rst.bat Normal file
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@ -0,0 +1,3 @@
@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V432b
jlink.exe reset.script

3
demos/RX-RX62N-RPB-USB/bin/Release_ram/lss.bat Normal file
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@ -0,0 +1,3 @@
@echo off
set path="d:\Program Files\KPIT\GNURX\rx-elf\rx-elf\bin"
rx-elf-objdump -h -S rx62n_demo.exe >rx62n_demo.lss

6
demos/RX-RX62N-RPB-USB/bin/Release_ram/r5f562n8bdfp_ram_wr.script Normal file
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@ -0,0 +1,6 @@
exec device = RX62N
speed auto
loadbin rx62n_demo.bin, 0x00000000
r
g
q

6
demos/RX-RX62N-RPB-USB/bin/Release_ram/r5f562n8bdfp_rd.script Normal file
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@ -0,0 +1,6 @@
exec device = RX62N
speed auto
savebin ram_dump.bin, 0x00000000, 0x18000
r
g
q

5
demos/RX-RX62N-RPB-USB/bin/Release_ram/reset.script Normal file
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@ -0,0 +1,5 @@
exec device = RX62N
speed auto
r
g
q

BIN
demos/RX-RX62N-RPB-USB/bin/Release_ram/rx62n_demo_vectors_0xFFFFFF80.bin Normal file
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Binary file not shown.

531
demos/RX-RX62N-RPB-USB/chconf.h Normal file
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@ -0,0 +1,531 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB TRUE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB TRUE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 115200
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#include "test.h"
#include "shell.h"
#include "chprintf.h"
#include "usb_descriptors.h"
static WORKING_AREA(waThread1, 128);
static msg_t Thread1(void *arg) {
while (TRUE) {
palClearPad(GPIO10, PORTA_LED0);
chThdSleepMilliseconds(50);
palClearPad(GPIO10, PORTA_LED1);
chThdSleepMilliseconds(50);
palClearPad(GPIO10, PORTA_LED2);
palSetPad(GPIO10, PORTA_LED0);
chThdSleepMilliseconds(50);
palSetPad(GPIO10, PORTA_LED1);
chThdSleepMilliseconds(50);
palSetPad(GPIO10, PORTA_LED2);
chThdSleepMilliseconds(50);
chThdSleepMilliseconds(400);
}
return 0;
}
/*===========================================================================*/
/* Command line related. */
/*===========================================================================*/
#define SHELL_WA_SIZE THD_WA_SIZE(1024)
#define TEST_WA_SIZE THD_WA_SIZE(256)
static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
size_t n, size;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: mem\r\n");
return;
}
n = chHeapStatus(NULL, &size);
chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus());
chprintf(chp, "heap fragments : %u\r\n", n);
chprintf(chp, "heap free total : %u bytes\r\n", size);
}
static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
static const char *states[] = {THD_STATE_NAMES};
Thread *tp;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: threads\r\n");
return;
}
chprintf(chp, " addr stack prio refs state time\r\n");
tp = chRegFirstThread();
do {
chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n",
(uint32_t)tp, (uint32_t)tp->p_ctx.sp,
(uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
states[tp->p_state], (uint32_t)tp->p_time);
tp = chRegNextThread(tp);
} while (tp != NULL);
}
static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
Thread *tp;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: test\r\n");
return;
}
tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(),
TestThread, chp);
if (tp == NULL) {
chprintf(chp, "out of memory\r\n");
return;
}
chThdWait(tp);
}
static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
static uint8_t buf[] =
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef";
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: write\r\n");
return;
}
while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) {
chSequentialStreamWrite(&SDU1, buf, sizeof buf - 1);
}
chprintf(chp, "\r\n\nstopped\r\n");
}
static const ShellCommand commands[] = {
{"mem", cmd_mem},
{"threads", cmd_threads},
{"test", cmd_test},
{"write", cmd_write},
{NULL, NULL}
};
static const ShellConfig shell_cfg1 = {
/* (BaseSequentialStream *)&SD1,*/
(BaseSequentialStream *)&SDU1,
commands
};
/*===========================================================================*/
/* Main and generic code. */
/*===========================================================================*/
/*
* Application entry point.
*/
int main(void) {
Thread *shelltp = NULL;
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
/*
* Shell manager initialization.
*/
shellInit();
/*
* Starts the LED blinker thread.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
sduObjectInit(&SDU1);
sduStart(&SDU1, &serusbcfg);
usbStart(serusbcfg.usbp, &usbcfg);
usbDisconnectBus(serusbcfg.usbp);
chThdSleepMilliseconds(1000);
usbConnectBus(serusbcfg.usbp);
/*
* Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop and listen for events.
*/
while (TRUE) {
/* if (!shelltp) {*/
if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) {
/* chprintf((BaseSequentialStream *)&SD1, "USB Active\r\n");*/
shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
}
else if (chThdTerminated(shelltp)) {
chThdRelease(shelltp); /* Recovers memory of the previous shell. */
shelltp = NULL; /* Triggers spawning of a new shell. */
}
chThdSleepMilliseconds(100);
}
return 0;
}

65
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* RX62N drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the driver
* is enabled in halconf.h.
*/
/*
* HAL driver system settings.
*/
#define RX62N_ICLK_MUL 8
#define RX62N_PCLK_MUL 4
#define RX62N_BCLK_MUL 1
#define RX62N_SDCLK_OUTPUT_ENABLED FALSE
#define RX62N_BCLK_OUTPUT_ENABLED FALSE
/*
* ADC driver system settings.
*/
/*
* CAN driver system settings.
*/
/*
* MAC driver system settings.
*/
/*
* PWM driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define RX62N_SERIAL_USE_UART0 TRUE
#define RX62N_SERIAL_UART0_IRQ_PRIORITY 3
#define RX62N_SERIAL_USE_UART1 FALSE
/*
* SPI driver system settings.
*/
/*
* USB driver system settings.
*/
#define RX62N_USE_USB0 TRUE
#define RX62N_USB0_IRQ_PRIORITY 7

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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<CodeBlocks_project_file>
<FileVersion major="1" minor="6" />
<Project>
<Option title="rx62n_demo" />
<Option pch_mode="2" />
<Option compiler="kpit_rx_gcc_compiler" />
<Build>
<Target title="Release_ram">
<Option output="bin/Release_ram/rx62n_demo" prefix_auto="1" extension_auto="1" />
<Option object_output="obj/Release_ram/" />
<Option type="1" />
<Option compiler="kpit_rx_gcc_compiler" />
<Compiler>
<Add option="-Os" />
<Add option="-nofpu" />
<Add option="-DRAMRUN=1" />
</Compiler>
<Linker>
<Add option="-T../../os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld" />
<Add option="-nostdlib" />
<Add library="c" />
<Add library="m" />
<Add directory="d:/Program Files/KPIT/GNURXv12.03-ELF/rx-elf/rx-elf/rx-elf/lib/no-fpu-libs" />
<Add directory="d:/Program Files/KPIT/GNURXv12.03-ELF/rx-elf/rx-elf/lib/gcc/rx-elf/4.7-GNURX_v12.03/no-fpu-libs" />
</Linker>
<ExtraCommands>
<Add after="rx-elf-objcopy -O binary -R fvectors $(TARGET_OUTPUT_FILE) $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).bin" />
<Add after="rx-elf-objcopy -O binary -j fvectors $(TARGET_OUTPUT_FILE) $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME)_vectors_0xFFFFFF80.bin" />
<Add after="rx-elf-size $(TARGET_OUTPUT_FILE)" />
<Mode after="always" />
</ExtraCommands>
</Target>
</Build>
<Compiler>
<Add option="-fomit-frame-pointer" />
<Add option="-Wall" />
<Add option="-std=gnu99" />
<Add option="-funsigned-char" />
<Add option="-fshort-enums" />
<Add option="-Wswitch" />
<Add option="-Wunused-variable" />
<Add option="-Wno-pointer-sign" />
<Add option="-ffunction-sections" />
<Add option="-mcpu=rx600" />
<Add option="-mlittle-endian-data" />
<Add option="-D__RX_LITTLE_ENDIAN__=1" />
<Add directory="." />
<Add directory="../../os/kernel/include" />
<Add directory="../../os/ports/GCC/RX" />
<Add directory="../../os/ports/GCC/RX/RX62N" />
<Add directory="../../boards/RPBRX62N" />
<Add directory="../../os/hal/include" />
<Add directory="../../os/hal/platforms/RX62N" />
<Add directory="../../boards/RENESAS_RPBRX62N" />
<Add directory="../../test" />
<Add directory="../../os/various" />
</Compiler>
<Linker>
<Add option="-Wl,-Map=obj\map.txt" />
<Add option="-nostartfiles" />
<Add option="-Wl,--relax" />
<Add option="-Wl,--gc-sections" />
</Linker>
<Unit filename="../../boards/RENESAS_RPBRX62N/board.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../boards/RENESAS_RPBRX62N/board.h" />
<Unit filename="../../os/hal/include/hal.h" />
<Unit filename="../../os/hal/include/pal.h" />
<Unit filename="../../os/hal/include/serial.h" />
<Unit filename="../../os/hal/include/serial_usb.h" />
<Unit filename="../../os/hal/include/usb.h" />
<Unit filename="../../os/hal/platforms/Rx62n/hal_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/hal_lld.h" />
<Unit filename="../../os/hal/platforms/Rx62n/iodefine_gcc62n.h" />
<Unit filename="../../os/hal/platforms/Rx62n/pal_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/pal_lld.h" />
<Unit filename="../../os/hal/platforms/Rx62n/serial_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/serial_lld.h" />
<Unit filename="../../os/hal/platforms/Rx62n/usb_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/usb_lld.h" />
<Unit filename="../../os/hal/src/hal.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/src/pal.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/src/serial.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/src/serial_usb.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/src/usb.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/include/ch.h" />
<Unit filename="../../os/kernel/include/chbsem.h" />
<Unit filename="../../os/kernel/include/chcond.h" />
<Unit filename="../../os/kernel/include/chdebug.h" />
<Unit filename="../../os/kernel/include/chdynamic.h" />
<Unit filename="../../os/kernel/include/chevents.h" />
<Unit filename="../../os/kernel/include/chfiles.h" />
<Unit filename="../../os/kernel/include/chheap.h" />
<Unit filename="../../os/kernel/include/chinline.h" />
<Unit filename="../../os/kernel/include/chlists.h" />
<Unit filename="../../os/kernel/include/chmboxes.h" />
<Unit filename="../../os/kernel/include/chmemcore.h" />
<Unit filename="../../os/kernel/include/chmempools.h" />
<Unit filename="../../os/kernel/include/chmsg.h" />
<Unit filename="../../os/kernel/include/chmtx.h" />
<Unit filename="../../os/kernel/include/chqueues.h" />
<Unit filename="../../os/kernel/include/chregistry.h" />
<Unit filename="../../os/kernel/include/chschd.h" />
<Unit filename="../../os/kernel/include/chsem.h" />
<Unit filename="../../os/kernel/include/chstreams.h" />
<Unit filename="../../os/kernel/include/chsys.h" />
<Unit filename="../../os/kernel/include/chthreads.h" />
<Unit filename="../../os/kernel/include/chvt.h" />
<Unit filename="../../os/kernel/src/chcond.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chdebug.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chdynamic.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chevents.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chheap.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chlists.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmboxes.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmemcore.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmempools.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmsg.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chmtx.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chqueues.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chregistry.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chschd.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chsem.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chsys.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chthreads.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/kernel/src/chvt.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld" />
<Unit filename="../../os/ports/GCC/RX/RX62N/rxparams.h" />
<Unit filename="../../os/ports/GCC/RX/RX62N/vectors.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/ports/GCC/RX/chcore.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/ports/GCC/RX/chcore.h" />
<Unit filename="../../os/ports/GCC/RX/chtypes.h" />
<Unit filename="../../os/ports/GCC/RX/crt0.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/various/chprintf.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/various/chprintf.h" />
<Unit filename="../../os/various/shell.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/various/shell.h" />
<Unit filename="../../test/test.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/test.h" />
<Unit filename="../../test/testbmk.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testbmk.h" />
<Unit filename="../../test/testdyn.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testdyn.h" />
<Unit filename="../../test/testevt.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testevt.h" />
<Unit filename="../../test/testheap.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testheap.h" />
<Unit filename="../../test/testmbox.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testmbox.h" />
<Unit filename="../../test/testmsg.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testmsg.h" />
<Unit filename="../../test/testmtx.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testmtx.h" />
<Unit filename="../../test/testpools.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testpools.h" />
<Unit filename="../../test/testqueues.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testqueues.h" />
<Unit filename="../../test/testsem.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testsem.h" />
<Unit filename="../../test/testthd.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../test/testthd.h" />
<Unit filename="chconf.h" />
<Unit filename="halconf.h" />
<Unit filename="main.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="mcuconf.h" />
<Unit filename="usb_descriptors.h" />
<Extensions>
<code_completion />
<envvars />
<debugger />
<lib_finder disable_auto="1" />
<DoxyBlocks>
<comment_style block="0" line="0" />
<doxyfile_project />
<doxyfile_build />
<doxyfile_warnings />
<doxyfile_output />
<doxyfile_dot />
<general />
</DoxyBlocks>
</Extensions>
</Project>
</CodeBlocks_project_file>

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file usb_descriptors.h
* @brief USB descriptors.
* @addtogroup usb_descriptors
* @{
*/
#ifndef _USBDESCRIPTORS_H_
#define _USBDESCRIPTORS_H_
/*
* Endpoints to be used for USBD1.
*/
#define USBD1_DATA_REQUEST_EP 3
#define USBD1_DATA_AVAILABLE_EP 4
#define USBD1_INTERRUPT_REQUEST_EP 6
/*
* Serial over USB Driver structure.
*/
static SerialUSBDriver SDU1;
/*
* USB Device Descriptor.
*/
static const uint8_t vcom_device_descriptor_data[18] = {
USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
0x02, /* bDeviceClass (CDC). */
0x00, /* bDeviceSubClass. */
0x00, /* bDeviceProtocol. */
0x40, /* bMaxPacketSize. */
#if (USB_VENDOR_ID == USB_VENDOR_RENESAS)
0x0483, /* idVendor (ST). */
0x5740, /* idProduct. */
#else
0x045B, /* idVendor (RENESAS). */
0x2014, /* idProduct. */
#endif
0x0200, /* bcdDevice. */
1, /* iManufacturer. */
2, /* iProduct. */
3, /* iSerialNumber. */
1) /* bNumConfigurations. */
};
/*
* Device Descriptor wrapper.
*/
static const USBDescriptor vcom_device_descriptor = {
sizeof vcom_device_descriptor_data,
vcom_device_descriptor_data
};
/* Configuration Descriptor tree for a CDC.*/
static const uint8_t vcom_configuration_descriptor_data[67] = {
/* Configuration Descriptor.*/
USB_DESC_CONFIGURATION(67, /* wTotalLength. */
0x02, /* bNumInterfaces. */
0x01, /* bConfigurationValue. */
0, /* iConfiguration. */
0xC0, /* bmAttributes (self powered). */
50), /* bMaxPower (100mA). */
/* Interface Descriptor.*/
USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
0x00, /* bAlternateSetting. */
0x01, /* bNumEndpoints. */
0x02, /* bInterfaceClass (Communications
Interface Class, CDC section
4.2). */
0x02, /* bInterfaceSubClass (Abstract
Control Model, CDC section 4.3). */
0x01, /* bInterfaceProtocol (AT commands,
CDC section 4.4). */
0), /* iInterface. */
/* Header Functional Descriptor (CDC section 5.2.3).*/
USB_DESC_BYTE (5), /* bLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
Functional Descriptor. */
USB_DESC_BCD (0x0110), /* bcdCDC. */
/* Call Management Functional Descriptor. */
USB_DESC_BYTE (5), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
Functional Descriptor). */
USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
USB_DESC_BYTE (0x01), /* bDataInterface. */
/* ACM Functional Descriptor.*/
USB_DESC_BYTE (4), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
Control Management Descriptor). */
USB_DESC_BYTE (0x02), /* bmCapabilities. */
/* Union Functional Descriptor.*/
USB_DESC_BYTE (5), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
Functional Descriptor). */
USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
Class Interface). */
USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
Interface). */
/* Endpoint 3 Descriptor.*/
USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80,
0x03, /* bmAttributes (Interrupt). */
0x0008, /* wMaxPacketSize. */
0xFF), /* bInterval. */
/* Interface Descriptor.*/
USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
0x00, /* bAlternateSetting. */
0x02, /* bNumEndpoints. */
0x0A, /* bInterfaceClass (Data Class
Interface, CDC section 4.5). */
0x00, /* bInterfaceSubClass (CDC section
4.6). */
0x00, /* bInterfaceProtocol (CDC section
4.7). */
0x00), /* iInterface. */
/* Endpoint 1 out Descriptor.*/
USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
0x02, /* bmAttributes (Bulk). */
0x0040, /* wMaxPacketSize. */
0x00), /* bInterval. */
/* Endpoint 2 in Descriptor.*/
USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
0x02, /* bmAttributes (Bulk). */
0x0040, /* wMaxPacketSize. */
0x00) /* bInterval. */
};
/*
* Configuration Descriptor wrapper.
*/
static const USBDescriptor vcom_configuration_descriptor = {
sizeof vcom_configuration_descriptor_data,
vcom_configuration_descriptor_data
};
/*
* U.S. English language identifier.
*/
static const uint8_t vcom_string0[] = {
USB_DESC_BYTE(4), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
};
/*
* Vendor string.
*/
static const uint8_t vcom_string1[] = {
USB_DESC_BYTE(38), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
'c', 0, 's', 0
};
/*
* Device Description string.
*/
#if 1
static const uint8_t vcom_string2[] = {
USB_DESC_BYTE(56), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,
'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,
'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,
'o', 0, 'r', 0, 't', 0
};
#else
static const uint8_t vcom_string2[] = {
USB_DESC_BYTE(64), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,
'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,
'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,
'o', 0, 'r', 0, 't', 0, '.', 0, '.', 0, '.', 0, '.', 0
};
#endif
/*
* Serial Number string.
*/
static const uint8_t vcom_string3[] = {
USB_DESC_BYTE(8), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
'0' + CH_KERNEL_MAJOR, 0,
'0' + CH_KERNEL_MINOR, 0,
'0' + CH_KERNEL_PATCH, 0
};
/*
* Strings wrappers array.
*/
static const USBDescriptor vcom_strings[] = {
{sizeof vcom_string0, vcom_string0},
{sizeof vcom_string1, vcom_string1},
{sizeof vcom_string2, vcom_string2},
{sizeof vcom_string3, vcom_string3}
};
/*
* Handles the GET_DESCRIPTOR callback. All required descriptors must be
* handled here.
*/
static const USBDescriptor *get_descriptor(USBDriver *usbp,
uint8_t dtype,
uint8_t dindex,
uint16_t lang) {
(void)usbp;
(void)lang;
switch (dtype) {
case USB_DESCRIPTOR_DEVICE:
return &vcom_device_descriptor;
case USB_DESCRIPTOR_CONFIGURATION:
return &vcom_configuration_descriptor;
case USB_DESCRIPTOR_STRING:
if (dindex < 4)
return &vcom_strings[dindex];
}
return NULL;
}
/**
* @brief OUT EP1 state.
*/
static USBOutEndpointState ep1outstate;
/**
* @brief EP1 initialization structure (OUT only).
*/
static const USBEndpointConfig ep1config = {
USB_EP_MODE_TYPE_BULK,
NULL,
NULL,
sduDataReceived,
0x0000,
0x0040,
NULL,
&ep1outstate,
1,
NULL
};
/**
* @brief IN EP2 state.
*/
static USBInEndpointState ep2instate;
//void sduDataTransmitted1(USBDriver *usbp, usbep_t ep) {
//}
/**
* @brief EP2 initialization structure (IN only).
*/
static const USBEndpointConfig ep2config = {
USB_EP_MODE_TYPE_BULK,
NULL,
sduDataTransmitted,
NULL,
0x0040,
0x0000,
&ep2instate,
NULL,
1,
NULL
};
/**
* @brief IN EP3 state.
*/
static USBInEndpointState ep3instate;
/**
* @brief EP3 initialization structure (IN only).
*/
static const USBEndpointConfig ep3config = {
USB_EP_MODE_TYPE_INTR,
NULL,
sduInterruptTransmitted,
NULL,
0x0008,
0x0000,
&ep3instate,
NULL,
1,
NULL
};
/*
* Handles the USB driver global events.
*/
static void usb_event(USBDriver *usbp, usbevent_t event) {
switch (event) {
case USB_EVENT_RESET:
// myprintfI("*** usb reset\n");
return;
case USB_EVENT_ADDRESS:
return;
case USB_EVENT_CONFIGURED:
chSysLockFromIsr();
/* Enables the endpoints specified into the configuration.
Note, this callback is invoked from an ISR so I-Class functions
must be used.*/
usbInitEndpointI(usbp, USBD1_DATA_AVAILABLE_EP, &ep1config);
usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep2config);
usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep3config);
/* Resetting the state of the CDC subsystem.*/
sduConfigureHookI(&SDU1);
chSysUnlockFromIsr();
return;
case USB_EVENT_SUSPEND:
return;
case USB_EVENT_WAKEUP:
return;
case USB_EVENT_STALLED:
return;
}
return;
}
/*
* USB driver configuration.
*/
static const USBConfig usbcfg = {
usb_event,
get_descriptor,
sduRequestsHook,
NULL
};
/*
* Serial over USB driver configuration.
*/
static const SerialUSBConfig serusbcfg = {
&USBD1,
USBD1_DATA_REQUEST_EP,
USBD1_DATA_AVAILABLE_EP,
USBD1_INTERRUPT_REQUEST_EP
};
#endif /* _USBDESCRIPTORS_H_ */
/** @} */

3
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@ -0,0 +1,3 @@
@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V442a
jlink.exe r5f562n8bdfp_ram_wr.script

3
demos/RX-RX62N-RPB/bin/Release_ram/!rd.bat Normal file
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@ -0,0 +1,3 @@
@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V442a
jlink.exe r5f562n8bdfp_rd.script

3
demos/RX-RX62N-RPB/bin/Release_ram/!rst.bat Normal file
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@ -0,0 +1,3 @@
@echo off
set path=c:\Program Files (x86)\SEGGER\JLinkARM_V432b
jlink.exe reset.script

3
demos/RX-RX62N-RPB/bin/Release_ram/lss.bat Normal file
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@ -0,0 +1,3 @@
@echo off
set path="d:\Program Files\KPIT\GNURX\rx-elf\rx-elf\bin"
rx-elf-objdump -h -S rx62n_demo.exe >rx62n_demo.lss

6
demos/RX-RX62N-RPB/bin/Release_ram/r5f562n8bdfp_ram_wr.script Normal file
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@ -0,0 +1,6 @@
exec device = RX62N
speed auto
loadbin rx62n_demo.bin, 0x00000000
r
g
q

6
demos/RX-RX62N-RPB/bin/Release_ram/r5f562n8bdfp_rd.script Normal file
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@ -0,0 +1,6 @@
exec device = RX62N
speed auto
savebin ram_dump.bin, 0x00000000, 0x18000
r
g
q

5
demos/RX-RX62N-RPB/bin/Release_ram/reset.script Normal file
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@ -0,0 +1,5 @@
exec device = RX62N
speed auto
r
g
q

BIN
demos/RX-RX62N-RPB/bin/Release_ram/rx62n_demo_vectors_0xFFFFFF80.bin Normal file
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Binary file not shown.

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 115200
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#include "test.h"
#include "shell.h"
#include "chprintf.h"
static WORKING_AREA(waThread1, 128);
static msg_t Thread1(void *arg) {
while (TRUE) {
palClearPad(GPIO10, PORTA_LED0);
chThdSleepMilliseconds(50);
palClearPad(GPIO10, PORTA_LED1);
chThdSleepMilliseconds(50);
palClearPad(GPIO10, PORTA_LED2);
palSetPad(GPIO10, PORTA_LED0);
chThdSleepMilliseconds(50);
palSetPad(GPIO10, PORTA_LED1);
chThdSleepMilliseconds(50);
palSetPad(GPIO10, PORTA_LED2);
chThdSleepMilliseconds(50);
chThdSleepMilliseconds(400);
}
return 0;
}
/*===========================================================================*/
/* Command line related. */
/*===========================================================================*/
#define SHELL_WA_SIZE THD_WA_SIZE(1024)
#define TEST_WA_SIZE THD_WA_SIZE(256)
static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
size_t n, size;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: mem\r\n");
return;
}
n = chHeapStatus(NULL, &size);
chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus());
chprintf(chp, "heap fragments : %u\r\n", n);
chprintf(chp, "heap free total : %u bytes\r\n", size);
}
static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
static const char *states[] = {THD_STATE_NAMES};
Thread *tp;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: threads\r\n");
return;
}
chprintf(chp, " addr stack prio refs state time\r\n");
tp = chRegFirstThread();
do {
chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n",
(uint32_t)tp, (uint32_t)tp->p_ctx.sp,
(uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
states[tp->p_state], (uint32_t)tp->p_time);
tp = chRegNextThread(tp);
} while (tp != NULL);
}
static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
Thread *tp;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: test\r\n");
return;
}
tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(),
TestThread, chp);
if (tp == NULL) {
chprintf(chp, "out of memory\r\n");
return;
}
chThdWait(tp);
}
static const ShellCommand commands[] = {
{"mem", cmd_mem},
{"threads", cmd_threads},
{"test", cmd_test},
{NULL, NULL}
};
static const ShellConfig shell_cfg1 = {
(BaseSequentialStream *)&SD1,
commands
};
/*===========================================================================*/
/* Main and generic code. */
/*===========================================================================*/
/*
* Application entry point.
*/
int main(void) {
Thread *shelltp = NULL;
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Leds initialization.
*/
/*
PORTA.DDR.BYTE = 0x07;
PORTA.DR.BIT.B0 = 1;
PORTA.DR.BIT.B1 = 1;
PORTA.DR.BIT.B2 = 0;
*/
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
/*
* Shell manager initialization.
*/
shellInit();
/*
* Starts the LED blinker thread.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
/*
* Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop and listen for events.
*/
while (TRUE) {
if (!shelltp)
shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
else if (chThdTerminated(shelltp)) {
chThdRelease(shelltp); /* Recovers memory of the previous shell. */
shelltp = NULL; /* Triggers spawning of a new shell. */
}
chThdSleepMilliseconds(100);
}
return 0;
}

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* RX62N drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the driver
* is enabled in halconf.h.
*/
/*
* HAL driver system settings.
*/
#define RX62N_ICLK_MUL 8
#define RX62N_PCLK_MUL 4
#define RX62N_BCLK_MUL 1
#define RX62N_SDCLK_OUTPUT_ENABLED FALSE
#define RX62N_BCLK_OUTPUT_ENABLED FALSE
/*
* ADC driver system settings.
*/
/*
* CAN driver system settings.
*/
/*
* MAC driver system settings.
*/
/*
* PWM driver system settings.
*/
/*
* SERIAL driver system settings.
*/
#define RX62N_SERIAL_USE_UART0 TRUE
#define RX62N_SERIAL_UART0_IRQ_PRIORITY 3
#define RX62N_SERIAL_USE_UART1 FALSE
/*
* SPI driver system settings.
*/

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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<CodeBlocks_project_file>
<FileVersion major="1" minor="6" />
<Project>
<Option title="rx62n_demo" />
<Option pch_mode="2" />
<Option compiler="kpit_rx_gcc_compiler" />
<Build>
<Target title="Release_ram">
<Option output="bin/Release_ram/rx62n_demo" prefix_auto="1" extension_auto="1" />
<Option object_output="obj/Release_ram/" />
<Option type="1" />
<Option compiler="kpit_rx_gcc_compiler" />
<Compiler>
<Add option="-O2" />
<Add option="-nofpu" />
<Add option="-DRAMRUN=1" />
</Compiler>
<Linker>
<Add option="-T../../os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld" />
<Add option="-nostdlib" />
<Add library="c" />
<Add library="m" />
<Add directory="d:/Program Files/KPIT/GNURXv12.03-ELF/rx-elf/rx-elf/rx-elf/lib/no-fpu-libs" />
<Add directory="d:/Program Files/KPIT/GNURXv12.03-ELF/rx-elf/rx-elf/lib/gcc/rx-elf/4.7-GNURX_v12.03/no-fpu-libs" />
</Linker>
<ExtraCommands>
<Add after="rx-elf-objcopy -O binary -R fvectors $(TARGET_OUTPUT_FILE) $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME).bin" />
<Add after="rx-elf-objcopy -O binary -j fvectors $(TARGET_OUTPUT_FILE) $(TARGET_OUTPUT_DIR)$(TARGET_OUTPUT_BASENAME)_vectors_0xFFFFFF80.bin" />
<Add after="rx-elf-size $(TARGET_OUTPUT_FILE)" />
<Mode after="always" />
</ExtraCommands>
</Target>
</Build>
<Compiler>
<Add option="-fomit-frame-pointer" />
<Add option="-O2" />
<Add option="-Wall" />
<Add option="-std=gnu99" />
<Add option="-funsigned-char" />
<Add option="-fshort-enums" />
<Add option="-Wswitch" />
<Add option="-Wunused-variable" />
<Add option="-Wno-pointer-sign" />
<Add option="-ffunction-sections" />
<Add option="-mcpu=rx600" />
<Add option="-mlittle-endian-data" />
<Add option="-D__RX_LITTLE_ENDIAN__=1" />
<Add directory="." />
<Add directory="../../os/kernel/include" />
<Add directory="../../os/ports/GCC/RX" />
<Add directory="../../os/ports/GCC/RX/RX62N" />
<Add directory="../../boards/RPBRX62N" />
<Add directory="../../os/hal/include" />
<Add directory="../../os/hal/platforms/RX62N" />
<Add directory="../../boards/RENESAS_RPBRX62N" />
<Add directory="../../test" />
<Add directory="../../os/various" />
</Compiler>
<Linker>
<Add option="-Wl,-Map=obj\map.txt" />
<Add option="-nostartfiles" />
<Add option="-Wl,--relax" />
<Add option="-Wl,--gc-sections" />
</Linker>
<Unit filename="../../boards/RENESAS_RPBRX62N/board.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../boards/RENESAS_RPBRX62N/board.h" />
<Unit filename="../../os/hal/include/hal.h" />
<Unit filename="../../os/hal/include/pal.h" />
<Unit filename="../../os/hal/include/serial.h" />
<Unit filename="../../os/hal/platforms/Rx62n/hal_lld.c">
<Option compilerVar="CC" />
</Unit>
<Unit filename="../../os/hal/platforms/Rx62n/hal_lld.h" />
<Unit filename="../../os/hal/platforms/Rx62n/iodefine_gcc62n.h" />
<Unit filename="../../os/hal/platforms/Rx62n/pal_lld.c">
<Option compilerVar="CC" />
</Unit>
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<Unit filename="../../os/hal/platforms/Rx62n/serial_lld.c">
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<Unit filename="../../os/kernel/include/chbsem.h" />
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<Unit filename="../../os/kernel/include/chdebug.h" />
<Unit filename="../../os/kernel/include/chdynamic.h" />
<Unit filename="../../os/kernel/include/chevents.h" />
<Unit filename="../../os/kernel/include/chfiles.h" />
<Unit filename="../../os/kernel/include/chheap.h" />
<Unit filename="../../os/kernel/include/chinline.h" />
<Unit filename="../../os/kernel/include/chlists.h" />
<Unit filename="../../os/kernel/include/chmboxes.h" />
<Unit filename="../../os/kernel/include/chmemcore.h" />
<Unit filename="../../os/kernel/include/chmempools.h" />
<Unit filename="../../os/kernel/include/chmsg.h" />
<Unit filename="../../os/kernel/include/chmtx.h" />
<Unit filename="../../os/kernel/include/chqueues.h" />
<Unit filename="../../os/kernel/include/chregistry.h" />
<Unit filename="../../os/kernel/include/chschd.h" />
<Unit filename="../../os/kernel/include/chsem.h" />
<Unit filename="../../os/kernel/include/chstreams.h" />
<Unit filename="../../os/kernel/include/chsys.h" />
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<Unit filename="../../os/kernel/include/chvt.h" />
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<Unit filename="../../os/ports/GCC/RX/chtypes.h" />
<Unit filename="../../os/ports/GCC/RX/crt0.c">
<Option compilerVar="CC" />
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<Unit filename="../../os/various/shell.c">
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163
docs/reports/RX62N-96-GCC.txt Normal file
View File

@ -0,0 +1,163 @@
***************************************************************************
Options: -O2 -nofpu -fomit-frame-pointer -mlittle-endian-data
Settings: RX62N_SYSCLK=96000000, code executed in RAM
Compiler: KPIT GNURX v12.03 Windows Tool Chain
***************************************************************************
*** ChibiOS/RT test suite
***
*** Kernel: 2.6.0
*** Compiled: Jul 27 2013 - 16:33:27
*** Compiler: GCC 4.7-GNURX_v12.03
*** Architecture: RX
*** Platform: RX62N
*** Test Board: Renesas RPBRX62N
----------------------------------------------------------------------------
--- Test Case 1.1 (Threads, enqueuing test #1)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Threads, enqueuing test #2)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Threads, priority change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.4 (Threads, delays)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.1 (Semaphores, enqueuing)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Semaphores, timeout)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Semaphores, atomic signal-wait)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.4 (Binary Semaphores, functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.1 (Mutexes, priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Mutexes, priority inheritance, simple case)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.3 (Mutexes, priority inheritance, complex case)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.4 (Mutexes, priority return)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.5 (Mutexes, status)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.6 (CondVar, signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.7 (CondVar, broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.8 (CondVar, boost test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.1 (Messages, loop)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 5.1 (Mailboxes, queuing and timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.1 (Events, registration and dispatch)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Events, wait and broadcast)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events, timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.1 (Heap, allocation and fragmentation test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.1 (Memory Pools, queue/dequeue)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.1 (Dynamic APIs, threads creation from heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic APIs, registry and references)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.1 (Queues, input queues)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Queues, output queues)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
--- Score : 537180 msgs/S, 1074360 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
--- Score : 431186 msgs/S, 862372 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
--- Score : 431186 msgs/S, 862372 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
--- Score : 1698104 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
--- Score : 283641 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
--- Score : 418058 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
--- Score : 124233 reschedules/S, 745398 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
--- Score : 882140 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
--- Score : 1132072 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
--- Score : 1347534 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
--- Score : 2113292 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
--- Score : 1282060 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
--- System: 1828 bytes
--- Thread: 72 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- EventS: 4 bytes
--- EventL: 16 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- Queue : 36 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

9
os/hal/include/usb.h
View File

@ -78,6 +78,12 @@
#define USB_EARLY_SET_ADDRESS 0
#define USB_LATE_SET_ADDRESS 1
#define USB_EP0_STATUS_STAGE_SW 0
#define USB_EP0_STATUS_STAGE_HW 1
#define USB_SET_ADDRESS_ACK_SW 0
#define USB_SET_ADDRESS_ACK_HW 1
/**
* @name Helper macros for USB descriptors
* @{
@ -445,6 +451,9 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp,
(usbp)->ep0endcb = (endcb); \
}
#define usbSetupEnd(usbp, ep) \
usb_lld_end_transaction(usbp, ep)
/**
* @brief Reads a setup packet from the dedicated packet buffer.
* @details This function must be invoked in the context of the @p setup_cb

75
os/hal/platforms/Rx62n/hal_lld.c Normal file
View File

@ -0,0 +1,75 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/hal_lld.c
* @brief RX62N HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "ch.h"
#include "hal.h"
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
}
/**
* @brief RX62N clocks initialization.
* @note This function must be invoked only after the system reset.
*
* @special
*/
void rx62n_clock_init(void) {
SYSTEM.SCKCR.LONG = RX62N_SCKCR_ICK | RX62N_SCKCR_PCK | RX62N_SCKCR_BCK
#if RX62N_SDCLK_OUTPUT_ENABLED == FALSE
| (1 << 22)
#endif
#if RX62N_BCLK_OUTPUT_ENABLED == FALSE
| (1 << 23)
#endif
;
}
/** @} */

361
os/hal/platforms/Rx62n/hal_lld.h Normal file
View File

@ -0,0 +1,361 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/hal_lld.h
* @brief HAL subsystem low level driver header template.
*
* @addtogroup HAL
* @{
*/
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
#include "iodefine_gcc62n.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Defines the support for realtime counters in the HAL.
*/
#define HAL_IMPLEMENTS_COUNTERS FALSE
#define IWDTCLK 125000 /**< Watchdog internal clock */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief System PLL multiplier.
* @note The value is hardware fixed at 8.
*/
#if defined(__DOXYGEN__)
#define RX62N_SYSPLL_MUL 8
#endif
/**
* @brief System PLL divider.
* @note The value must be chosen between (1, 2, 4, 8).
*/
/*
#if defined(__DOXYGEN__)
#define RX62N_SYSPLL_DIV 1
#endif
*/
/**
* @brief Enables or disables the SDCLK clock output.
*/
#if !defined(RX62N_SDCLK_OUTPUT_ENABLED) || defined(__DOXYGEN__)
#define RX62N_SDCLK_OUTPUT_ENABLED FALSE
#endif
/**
* @brief Enables or disables the BCLK clock output.
*/
#if !defined(RX62N_BCLK_OUTPUT_ENABLED) || defined(__DOXYGEN__)
#define RX62N_BCLK_OUTPUT_ENABLED FALSE
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/**
* @brief ICK mask in SCKCR register.
*/
#if (RX62N_ICLK_MUL == 1) || defined(__DOXYGEN__)
#define RX62N_SCKCR_ICK (3 << 24)
#elif RX62N_ICLK_MUL == 2
#define RX62N_SCKCR_ICK (2 << 24)
#elif RX62N_ICLK_MUL == 4
#define RX62N_SCKCR_ICK (1 << 24)
#elif RX62N_ICLK_MUL == 8
#define RX62N_SCKCR_ICK (0 << 24)
#else
#error "invalid RX62N_ICLK_MUL value (1,2,4,8), check mcuconf.h"
#endif
/**
* @brief BCK mask in SCKCR register.
*/
#if (RX62N_BCLK_MUL == 1) || defined(__DOXYGEN__)
#define RX62N_SCKCR_BCK (3 << 16)
#elif RX62N_BCLK_MUL == 2
#define RX62N_SCKCR_BCK (2 << 16)
#elif RX62N_BCLK_MUL == 4
#define RX62N_SCKCR_BCK (1 << 16)
#elif RX62N_BCLK_MUL == 8
#define RX62N_SCKCR_BCK (0 << 16)
#else
#error "invalid RX62N_BCLK_MUL value (1,2,4,8), check mcuconf.h"
#endif
/**
* @brief PCK mask in SCKCR register.
*/
#if (RX62N_PCLK_MUL == 1) || defined(__DOXYGEN__)
#define RX62N_SCKCR_PCK (3 << 8)
#elif RX62N_PCLK_MUL == 2
#define RX62N_SCKCR_PCK (2 << 8)
#elif RX62N_PCLK_MUL == 4
#define RX62N_SCKCR_PCK (1 << 8)
#elif RX62N_PCLK_MUL == 8
#define RX62N_SCKCR_PCK (0 << 8)
#else
#error "invalid RX62N_PCLK_MUL value (1,2,4,8), check mcuconf.h"
#endif
/**
* @brief System clock.
*/
#define RX62N_SYSCLK (EXTALCLK * RX62N_ICLK_MUL)
#if (RX62N_SYSCLK < 8000000) || (RX62N_SYSCLK > 100000000)
#error "System clock frequency out of the acceptable range (8..100MHz max)"
#endif
/**
* @brief Peripheral clock.
*/
#define RX62N_PERCLK (EXTALCLK * RX62N_PCLK_MUL)
#if (RX62N_PERCLK < 8000000) || (RX62N_PERCLK > 100000000)
#error "Peripheral clock frequency out of the acceptable range (8..50MHz max)"
#endif
#if (RX62N_PERCLK > RX62N_SYSCLK)
#error "Peripheral clock frequency higher than system clock frequency"
#endif
#if (EXTALCLK < 8000000) || (EXTALCLK > 14000000)
#error "External crystal frequency out of the acceptable range (8..14MHz max)"
#endif
/*
* TODO: check SYSCLK (ICLK) when ethernet controller is used (SYSCLK > 12.5MHz)
* TODO: check UCLK when USB is used
* TODO: oscilation stop detection
*/
/*
Clock frequencies (from manual):
ICLK: 8..100MHz
PCLK: 8..50MHz
BCLK: 8..50MHz or 8..100MHz
BCLK_OUT: 8..25MHz or 8..50MHz
SDCLK: 8..50MHz
UCLK: 48MHz (only when EXTAL = 12MHz)
SUBCLK: 32768Hz
IWDTCLK: 125kHz
ICLK >= PCLK
ICLK >= BCLK
*/
#if defined(__DOXYGEN__)
/**
* @name Platform identification
* @{
*/
#define PLATFORM_NAME "RX62N"
/** @} */
#elif defined(RX62NXADBG) || defined(RX62NXBDBG) || \
defined(RX62NXADLE) || defined(RX62NXBDLE) || \
defined(RX62NXADFB) || defined(RX62NXBDFB) || \
defined(RX62NXADFP) || defined(RX62NXBDFP) || \
defined(RX62NXADLD) || defined(RX62NXBDLD) || \
defined(__DOXYGEN__)
#else
#error "unspecified, unsupported or invalid RX62N platform"
#endif
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
#if defined(RX62NXADBG) || defined (RX62NXBDBG) || defined(__DOXYGEN__)
/**
* @name RX62NXXDBG capabilities (LFBGA176)
* @{
*/
#error "unsupported RX62N platform"
/** @} */
#endif /* defined(RX62NXADBG) || defined(RX62NXBDBG) */
#if defined(RX62NXADLE) || defined (RX62NXBDLE) || defined(__DOXYGEN__)
/**
* @name RX62NXXDLE capabilities (TFLGA145)
* @{
*/
#error "unsupported RX62N platform"
/** @} */
#endif /* defined(RX62NXADLE) || defined(RX62NXBDLE) */
#if defined(RX62NXADFB) || defined (RX62NXBDFB) || defined(__DOXYGEN__)
/**
* @name RX62NXXDLE capabilities (LQFP144)
* @{
*/
#error "unsupported RX62N platform"
/** @} */
#endif /* defined(RX62NXADFB) || defined(RX62NXBDFB) */
#if defined(RX62NXADFP) || defined (RX62NXBDFP) || defined(__DOXYGEN__)
/**
* @name RX62NXXDFP capabilities (LQFP100)
* @{
*/
/* ADC attributes.*/
#define RX62N_HAS_ADC1 TRUE
/* CAN attributes.*/
#if defined (RX62NXADFP)
#define RX62N_HAS_CAN FALSE
#else
#define RX62N_HAS_CAN TRUE
#endif
/* DAC attributes.*/
#define RX62N_HAS_DAC TRUE
/* DMA attributes.*/
/* ETH attributes.*/
#define RX62N_HAS_ETH TRUE
/* EXTI attributes.*/
//#define RX62N_EXTI_NUM_CHANNELS 18
/* GPIO attributes.*/
#define RX62N_HAS_PORT0 TRUE
#define RX62N_HAS_PORT0_OD TRUE /* Open Drain */
#define RX62N_HAS_PORT1 TRUE
#define RX62N_HAS_PORT1_OD TRUE /* Open Drain */
#define RX62N_HAS_PORT2 TRUE
#define RX62N_HAS_PORT2_OD TRUE /* Open Drain */
#define RX62N_HAS_PORT3 TRUE
#define RX62N_HAS_PORT3_OD TRUE /* Open Drain (P30 to P34) */
#define RX62N_HAS_PORT4 TRUE
#define RX62N_HAS_PORT5 TRUE
#define RX62N_HAS_PORT6 FALSE
#undef PORT6
#define RX62N_HAS_PORT7 FALSE
#undef PORT7
#define RX62N_HAS_PORT8 FALSE
#undef PORT8
#define RX62N_HAS_PORT9 FALSE
#undef PORT9
#define RX62N_HAS_PORTA TRUE
#define RX62N_HAS_PORTA_PU TRUE /* pull-up */
#define RX62N_HAS_PORTB TRUE
#define RX62N_HAS_PORTB_PU TRUE /* pull-up */
#define RX62N_HAS_PORTC TRUE
#define RX62N_HAS_PORTC_OD TRUE /* Open Drain */
#define RX62N_HAS_PORTC_PU TRUE /* Pull-up */
#define RX62N_HAS_PORTD TRUE
#define RX62N_HAS_PORTD_PU TRUE /* pull-up */
#define RX62N_HAS_PORTE TRUE
#define RX62N_HAS_PORTE_PU TRUE /* pull-up */
#define RX62N_HAS_PORTF FALSE
#undef PORTF
#define RX62N_HAS_PORTG FALSE
#undef PORTG
/* I2C attributes.*/
#define RX62N_HAS_I2C1 TRUE
#define RX62N_HAS_I2C2 TRUE
/* SDIO attributes.*/
//#define RX62N_HAS_SDIO FALSE
/* SPI attributes.*/
#define RX62N_HAS_SPI1 TRUE
#define RX62N_HAS_SPI2 TRUE
/* TIM attributes.*/
#define RX62N_HAS_TIM1 TRUE
#define RX62N_HAS_TIM2 TRUE
#define RX62N_HAS_TIM3 TRUE
#define RX62N_HAS_TIM4 TRUE
#define RX62N_HAS_TIM5 TRUE
#define RX62N_HAS_TIM6 TRUE
#define RX62N_HAS_TIM7 TRUE
#define RX62N_HAS_TIM8 TRUE
#define RX62N_HAS_TIM9 TRUE
#define RX62N_HAS_TIM10 TRUE
#define RX62N_HAS_TIM11 TRUE
#define RX62N_HAS_TIM12 TRUE
/* USART attributes.*/
#define RX62N_HAS_USART1 TRUE
#define RX62N_HAS_USART2 TRUE
#define RX62N_HAS_USART3 TRUE
#define RX62N_HAS_USART4 TRUE
#define RX62N_HAS_USART6 TRUE
#define RX62N_HAS_USART7 TRUE
/* USB attributes.*/
/*#define RX62N_HAS_USB TRUE*/
/*#define RX62N_HAS_OTG1 TRUE*/
/** @} */
#endif /* defined(RX62NXADFP) || defined(RX62NXBDFP) */
#if defined(RX62NXADLD) || defined (RX62NXBDLD) || defined(__DOXYGEN__)
/**
* @name RX62NXXDLD capabilities (TFLGA85)
* @{
*/
#error "unsupported RX62N platform"
/** @} */
#endif /* defined(RX62NXADLD) || defined(RX62NXBDLD) */
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
void rx62n_clock_init(void);
#ifdef __cplusplus
}
#endif
#endif /* _HAL_LLD_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/mac_lld.c
* @brief RX62N low level MAC driver code.
*
* @addtogroup MAC
* @{
*/
#include <string.h>
#include "ch.h"
#include "hal.h"
#include "mii.h"
#include "rx62n_mii.h"
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief Ethernet driver 1.
*/
MACDriver ETHD1;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
0x37, 0x01, 0x10};
__attribute__((aligned(16)))
static rx62n_eth_rx_descriptor_t rd[EDMAC_RECEIVE_DESCRIPTORS];
__attribute__((aligned(16)))
static rx62n_eth_tx_descriptor_t td[EDMAC_TRANSMIT_DESCRIPTORS];
__attribute__((aligned(32)))
static uint8_t rb[EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE];
__attribute__((aligned(32)))
static uint8_t tb[EDMAC_TRANSMIT_DESCRIPTORS * EDMAC_TRANSMIT_BUFFERS_SIZE];
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#if !defined(BOARD_PHY_ADDRESS)
/**
* @brief PHY address detection.
*
* @param[in] macp pointer to the @p MACDriver object
*/
static void mii_find_phy(MACDriver *macp) {
uint32_t i;
#if RX62N_MAC_PHY_TIMEOUT > 0
halrtcnt_t start = halGetCounterValue();
halrtcnt_t timeout = start + MS2RTT(RX62N_MAC_PHY_TIMEOUT);
while (halIsCounterWithin(start, timeout)) {
#endif
for (i = 0; i < 31; i++) {
if ((miiGet(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
((miiGet(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
return;
}
}
#if RX62N_MAC_PHY_TIMEOUT > 0
}
#endif
/* Wrong or defective board.*/
chSysHalt();
}
#endif
/**
* @brief MAC address setup.
*
* @param[in] p pointer to a six bytes buffer containing the MAC
* address
*/
static void mac_lld_set_address(const uint8_t *p) {
/* MAC address configuration, only a single address comparator is used,
hash table not used.*/
ETHERC.MAHR = ((uint32_t)p[0] << 24) |
((uint32_t)p[1] << 16) |
((uint32_t)p[2] << 8) |
((uint32_t)p[3] << 0);
ETHERC.MALR.LONG = ((uint32_t)p[4] << 8) |
((uint32_t)p[5] << 0);
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
static void serve_interrupt_ether1(void) {
uint32_t eesr = EDMAC.EESR.LONG;
if (eesr & (1<<18)) {
/* Frame received.*/
chSysLockFromIsr();
chSemResetI(&ETHD1.rdsem, 0);
#if MAC_USE_EVENTS
chEvtBroadcastI(&ETHD1.rdevent);
#endif
chSysUnlockFromIsr();
}
if (eesr & (1<<21)) {
/* Frame transmitted.*/
chSysLockFromIsr();
chSemResetI(&ETHD1.tdsem, 0);
chSysUnlockFromIsr();
}
EDMAC.EESR.LONG = 0x47FF0F9F;
}
CH_IRQ_HANDLER(Excep_ETHER_EINT) {
CH_IRQ_PROLOGUE();
serve_interrupt_ether1();
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level MAC initialization.
*
* @notapi
*/
void mac_lld_init(void) {
macObjectInit(&ETHD1);
ETHD1.link_up = FALSE;
/* Selection of the RMII or MII mode based on info exported by board.h.*/
#if defined(BOARD_PHY_RMII)
IOPORT.PFENET.BYTE = (1<<7)|(0<<4)|(1<<1);
#else
IOPORT.PFENET.BYTE = (1<<7)|(1<<4)|(1<<1);
#endif
/* MAC clocks temporary activation.*/
MSTP(EDMAC) = 0;
/* Reset of the MAC core.*/
EDMAC.EDMR.BIT.SWR = 1;
/* TODO: wait 64 cycles, here is 1ms delay */
asm volatile ("mov.l #24000,r2 \n\t"
"1: \n\t"
"sub #1,r2 \n\t"
"bne.b 1b \n\t");
EDMAC.EDMR.BIT.DE = 1;
/* Clear registers not affected by reset */
EDMAC.RMFCR.LONG = 0;
EDMAC.TFUCR.LONG = 0;
EDMAC.RFOCR.LONG = 0;
/* PHY address setup.*/
#if defined(BOARD_PHY_ADDRESS)
ETHD1.phyaddr = BOARD_PHY_ADDRESS;
#else
mii_find_phy(&ETHD1);
#endif
#if defined(BOARD_PHY_RESET)
/* PHY board-specific reset procedure.*/
BOARD_PHY_RESET();
#else
/* PHY soft reset procedure.*/
miiPut(&ETHD1, MII_BMCR, BMCR_RESET);
#if defined(BOARD_PHY_RESET_DELAY)
halPolledDelay(BOARD_PHY_RESET_DELAY);
#endif
while (miiGet(&ETHD1, MII_BMCR) & BMCR_RESET)
;
#endif
#if RX62N_MAC_ETH1_CHANGE_PHY_STATE
/* PHY in power down mode until the driver will be started.*/
miiPut(&ETHD1, MII_BMCR, miiGet(&ETHD1, MII_BMCR) | BMCR_PDOWN);
#endif
/* MAC clocks stopped again.*/
MSTP(EDMAC) = 1;
}
/**
* @brief Configures and activates the MAC peripheral.
*
* @param[in] macp pointer to the @p MACDriver object
*
* @notapi
*/
void mac_lld_start(MACDriver *macp) {
unsigned i;
/* Resets the state of all descriptors.*/
for (i = 0; i < EDMAC_RECEIVE_DESCRIPTORS; i++) {
rd[i].rd0 = /*RX62N_RD0_RFP_ONE|*/RX62N_RD0_RACT;
rd[i].rd1 = EDMAC_RECEIVE_BUFFERS_SIZE<<16;
rd[i].rd2 = (uint32_t)&rb[i * EDMAC_RECEIVE_BUFFERS_SIZE];
}
rd[i-1].rd0 |= RX62N_RD0_RDLE;
macp->rxptr = (rx62n_eth_rx_descriptor_t *)rd;
for (i = 0; i < EDMAC_TRANSMIT_DESCRIPTORS; i++) {
td[i].td0 = RX62N_TD0_TFP_ONE;
td[i].td1 = EDMAC_TRANSMIT_BUFFERS_SIZE<<16;
td[i].td2 = (uint32_t)&tb[i * EDMAC_TRANSMIT_BUFFERS_SIZE];
}
td[i-1].td0 |= RX62N_TD0_TDLE;
macp->txptr = (rx62n_eth_tx_descriptor_t *)td;
/* MAC clocks activation.*/
MSTP(EDMAC) = 0;
#if RX62N_MAC_ETH1_CHANGE_PHY_STATE
/* PHY in power up mode.*/
miiPut(macp, MII_BMCR, miiGet(macp, MII_BMCR) & ~BMCR_PDOWN);
#endif
/* MAC configuration.*/
ETHERC.RFLR.LONG = RX62N_MAC_BUFFERS_SIZE;
/* Clear all status flags.*/
ETHERC.ECSR.LONG = 0x37;
ETHERC.ECSIPR.LONG = 0;
ETHERC.IPGR.LONG = 0x14; /* Initial value.*/
/* MAC address setup.*/
if (macp->config->mac_address == NULL)
mac_lld_set_address(default_mac_address);
else
mac_lld_set_address(macp->config->mac_address);
/* Transmitter and receiver enabled.
Note that the complete setup of the MAC is performed when the link
status is detected.*/
ETHERC.ECMR.LONG |= (ETHERC_ECMR_RE | ETHERC_ECMR_TE);
/* ISR vector enabled.*/
IEN(ETHER,EINT) = 1;
IPR(ETHER,EINT) = RX62N_MAC_ETH1_IRQ_PRIORITY;
/* DMA configuration:
Descriptor list pointers.*/
EDMAC.RDLAR = (void *)rd;
EDMAC.TDLAR = (void *)td;
/* Clear all status flags.*/
EDMAC.EESR.LONG = 0x47FF0F9F;
EDMAC.TFTR.LONG = 0;
/* Set FIFO size to 2048.*/
EDMAC.FDR.LONG = 0x707;
EDMAC.RMCR.LONG = 1;
EDMAC.RPADIR.LONG = 0;
EDMAC.EESIPR.LONG = (1<<21)|(1<<18);
EDMAC.EDRRR.BIT.RR = 1;
}
/**
* @brief Deactivates the MAC peripheral.
*
* @param[in] macp pointer to the @p MACDriver object
*
* @notapi
*/
void mac_lld_stop(MACDriver *macp) {
if (macp->state != MAC_STOP) {
#if RX62N_MAC_ETH1_CHANGE_PHY_STATE
/* PHY in power down mode until the driver will be restarted.*/
miiPut(macp, MII_BMCR, miiGet(macp, MII_BMCR) | BMCR_PDOWN);
#endif
/* MAC and DMA stopped.*/
ETHERC.ECMR.LONG = 0;
/* MAC clocks stopped.*/
MSTP(EDMAC) = 1;
/* ISR vector disabled.*/
IEN(ETHER,EINT) = 0;
}
}
/**
* @brief Returns a transmission descriptor.
* @details One of the available transmission descriptors is locked and
* returned.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[out] tdp pointer to a @p MACTransmitDescriptor structure
* @return The operation status.
* @retval RDY_OK the descriptor has been obtained.
* @retval RDY_TIMEOUT descriptor not available.
*
* @notapi
*/
msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
MACTransmitDescriptor *tdp) {
rx62n_eth_tx_descriptor_t *tdes;
if (!macp->link_up)
return RDY_TIMEOUT;
chSysLock();
/* Get Current TX descriptor.*/
tdes = macp->txptr;
/* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
another thread.*/
if ( (tdes->td0 & RX62N_TD0_TACT) || (tdes->td0 & RX62N_TD0_TLOCKED) ) {
chSysUnlock();
return RDY_TIMEOUT;
}
/* Marks the current descriptor as locked using a reserved bit.*/
tdes->td0 |= RX62N_TD0_TLOCKED;
/* Next TX descriptor to use.*/
if (++macp->txptr >= &td[RX62N_MAC_TRANSMIT_BUFFERS]) {
macp->txptr = &td[0];
}
chSysUnlock();
/* Set the buffer size and configuration.*/
tdp->offset = 0;
tdp->size = RX62N_MAC_BUFFERS_SIZE;
tdp->physdesc = tdes;
return RDY_OK;
}
/**
* @brief Releases a transmit descriptor and starts the transmission of the
* enqueued data as a single frame.
*
* @param[in] tdp the pointer to the @p MACTransmitDescriptor structure
*
* @notapi
*/
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
chSysLock();
/* Unlocks the descriptor and returns it to the DMA engine.*/
tdp->physdesc->td1 = tdp->offset<<16;
tdp->physdesc->td0 &= ~RX62N_TD0_TLOCKED;
tdp->physdesc->td0 |= RX62N_TD0_TACT;
if (EDMAC.EDTRR.BIT.TR == 0)
EDMAC.EDTRR.BIT.TR = 1;
chSysUnlock();
}
/**
* @brief Cleans an incomplete frame.
*
* @param[in] from the start position of the incomplete frame
*/
static void cleanup(MACDriver *macp, rx62n_eth_rx_descriptor_t *from) {
while (from != macp->rxptr) {
from->rd0 = (from->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT;
if (++from >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
from = rd;
}
}
/**
* @brief Returns a receive descriptor.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[out] rdp pointer to a @p MACReceiveDescriptor structure
* @return The operation status.
* @retval RDY_OK the descriptor has been obtained.
* @retval RDY_TIMEOUT descriptor not available.
*
* @notapi
*/
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp) {
unsigned n;
rx62n_eth_rx_descriptor_t *edp;
n = EDMAC_RECEIVE_DESCRIPTORS;
chSysLock();
/*
* Skips active buffers, if any.
*/
skip:
while ((n > 0) && (macp->rxptr->rd0 & RX62N_RD0_RACT)) {
if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
macp->rxptr = rd;
n--;
}
#if 0
/*
* Skips fragments, if any, cleaning them up.
*/
while ((n > 0) && !(macp->rxptr->rd0 & RX62N_RD0_RACT) &&
!(macp->rxptr->rd0 & RX62N_RD0_RFP_SOF)) {
macp->rxptr->rd0 = (macp->rxptr->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT;
if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
macp->rxptr = rd;
n--;
}
#endif
/*
* Now compute the total frame size skipping eventual incomplete frames
* or holes...
*/
restart:
edp = macp->rxptr;
while (n > 0) {
if (macp->rxptr->rd0 & RX62N_RD0_RACT) {
/* Empty buffer for some reason... cleaning up the incomplete frame.*/
cleanup(macp, edp);
goto skip;
}
if ( ( macp->rxptr->rd0 & (RX62N_RD0_RFP_EOF|RX62N_RD0_RFE) )
== (RX62N_RD0_RFP_EOF|RX62N_RD0_RFE) ) {
/* End Of Frame found, but erroneous, so cleaning.*/
if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
macp->rxptr = rd;
n++;
cleanup(macp, edp);
goto skip;
}
/*
* End Of Frame found.
*/
if (macp->rxptr->rd0 & RX62N_RD0_RFP_EOF) {
rdp->offset = 0;
rdp->size = macp->rxptr->rd1 & 0xFFFF;
rdp->physdesc = edp;
if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
macp->rxptr = rd;
if (EDMAC.EDRRR.BIT.RR == 0)
EDMAC.EDRRR.BIT.RR = 1;
chSysUnlock();
return RDY_OK;
}
if ( (macp->rxptr != edp) && (macp->rxptr->rd0 & RX62N_RD0_RFP_MASK) ) {
/* Found another start or ... cleaning up the incomplete frame.*/
cleanup(macp, edp);
goto restart; /* Another start buffer for some reason... */
}
if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
macp->rxptr = rd;
n--;
}
if (EDMAC.EDRRR.BIT.RR == 0)
EDMAC.EDRRR.BIT.RR = 1;
chSysUnlock();
return RDY_TIMEOUT;
}
/**
* @brief Releases a receive descriptor.
* @details The descriptor and its buffer are made available for more incoming
* frames.
*
* @param[in] rdp the pointer to the @p MACReceiveDescriptor structure
*
* @notapi
*/
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
bool_t done;
rx62n_eth_rx_descriptor_t *edp = rdp->physdesc;
unsigned n = EDMAC_RECEIVE_DESCRIPTORS;
chSysLock();
do {
done = ((edp->rd0 & RX62N_RD0_RFP_EOF) != 0);
edp->rd1 = EDMAC_RECEIVE_BUFFERS_SIZE<<16;
edp->rd0 = (edp->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT;
if (++edp >= &rd[EDMAC_RECEIVE_DESCRIPTORS])
edp = rd;
n--;
}
while ((n > 0) && !done);
chSysUnlock();
}
/**
* @brief Updates and returns the link status.
*
* @param[in] macp pointer to the @p MACDriver object
* @return The link status.
* @retval TRUE if the link is active.
* @retval FALSE if the link is down.
*
* @notapi
*/
bool_t mac_lld_poll_link_status(MACDriver *macp) {
uint32_t ecmr, bmsr, bmcr;
ecmr = ETHERC.ECMR.LONG;
/* PHY CR and SR registers read.*/
(void)miiGet(macp, MII_BMSR);
bmsr = miiGet(macp, MII_BMSR);
bmcr = miiGet(macp, MII_BMCR);
/* Check on auto-negotiation mode.*/
if (bmcr & BMCR_ANENABLE) {
uint32_t lpa;
/* Auto-negotiation must be finished without faults and link established.*/
if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
(BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
return macp->link_up = FALSE;
/* Auto-negotiation enabled, checks the LPA register.*/
lpa = miiGet(macp, MII_LPA);
/* Check on link speed.*/
if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
ecmr |= ETHERC_ECMR_RTM;
else
ecmr &= ~ETHERC_ECMR_RTM;
/* Check on link mode.*/
if (lpa & (LPA_10FULL | LPA_100FULL))
ecmr |= ETHERC_ECMR_DM;
else
ecmr &= ~ETHERC_ECMR_DM;
}
else {
/* Link must be established.*/
if (!(bmsr & BMSR_LSTATUS))
return macp->link_up = FALSE;
/* Check on link speed.*/
if (bmcr & BMCR_SPEED100)
ecmr |= ETHERC_ECMR_RTM;
else
ecmr &= ~ETHERC_ECMR_RTM;
/* Check on link mode.*/
if (bmcr & BMCR_FULLDPLX)
ecmr |= ETHERC_ECMR_DM;
else
ecmr &= ~ETHERC_ECMR_DM;
}
/* Changes the mode in the MAC.*/
ETHERC.ECMR.LONG = ecmr;
/* Returns the link status.*/
return macp->link_up = TRUE;
}
/**
* @brief Writes to a transmit descriptor's stream.
*
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
* @param[in] buf pointer to the buffer containing the data to be
* written
* @param[in] size number of bytes to be written
* @return The number of bytes written into the descriptor's
* stream, this value can be less than the amount
* specified in the parameter @p size if the maximum
* frame size is reached.
*
* @notapi
*/
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size) {
chDbgAssert(!(tdp->physdesc->td0 & RX62N_TD0_TACT),
"mac_lld_write_transmit_descriptor(), #1",
"attempt to write descriptor already owned by DMA");
if (size > tdp->size - tdp->offset)
size = tdp->size - tdp->offset;
if (size > 0) {
memcpy((uint8_t *)(tdp->physdesc->td2) + tdp->offset, buf, size);
tdp->offset += size;
}
return size;
}
/**
* @brief Reads from a receive descriptor's stream.
*
* @param[in] rdp pointer to a @p MACReceiveDescriptor structure
* @param[in] buf pointer to the buffer that will receive the read data
* @param[in] size number of bytes to be read
* @return The number of bytes read from the descriptor's
* stream, this value can be less than the amount
* specified in the parameter @p size if there are
* no more bytes to read.
*
* @notapi
*/
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
uint8_t *buf,
size_t size) {
/*
chDbgAssert(!(rdp->physdesc->rd0 & RX62N_RD0_RACT),
"mac_lld_read_receive_descriptor(), #1",
"attempt to read descriptor already owned by DMA");
*/
if (size > rdp->size - rdp->offset)
size = rdp->size - rdp->offset;
if (size > 0) {
uint8_t *src = (uint8_t *)(rdp->physdesc->rd2) +
rdp->offset;
uint8_t *limit = (uint8_t *)&rb[EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE];
if (src >= limit) {
src -= EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE;
}
if (src + size > limit ) {
memcpy(buf, src, (size_t)(limit - src));
memcpy(buf + (size_t)(limit - src), rb, size - (size_t)(limit - src));
}
else
memcpy(buf, src, size);
rdp->offset += size;
}
return size;
}
#endif /* HAL_USE_MAC */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/mac_lld.h
* @brief RX62N low level MAC driver header.
*
* @addtogroup MAC
* @{
*/
#ifndef _MAC_LLD_H_
#define _MAC_LLD_H_
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief This implementation supports the zero-copy mode API.
*/
#define MAC_SUPPORTS_ZERO_COPY FALSE
/**
* @brief Every receive buffer must by aligned on 32-bytes boundary
* if multiple buffers used.
*/
#define EDMAC_RECEIVE_BUFFERS_SIZE (256) /* Do not modify */
/**
* @brief Every transmit buffer must by aligned on 32-bytes boundary
* if multiple buffers used.
*/
#define EDMAC_TRANSMIT_BUFFERS_SIZE \
(((RX62N_MAC_BUFFERS_SIZE - 1) | (32 - 1)) + 1)
#define EDMAC_RECEIVE_DESCRIPTORS \
(((((RX62N_MAC_BUFFERS_SIZE - 1) | (EDMAC_RECEIVE_BUFFERS_SIZE - 1)) + 1) \
/ EDMAC_RECEIVE_BUFFERS_SIZE) * RX62N_MAC_RECEIVE_BUFFERS)
#define EDMAC_TRANSMIT_DESCRIPTORS RX62N_MAC_TRANSMIT_BUFFERS
/**
* @name RD0 constants
* @{
*/
#define RX62N_RD0_RFS_MASK ((1<<27)-1)
#define RX62N_RD0_RFE (1<<27)
#define RX62N_RD0_RFP_COF (0<<28)
#define RX62N_RD0_RFP_EOF (1<<28)
#define RX62N_RD0_RFP_SOF (2<<28)
#define RX62N_RD0_RFP_ONE (3<<28)
#define RX62N_RD0_RFP_MASK (3<<28)
#define RX62N_RD0_RDLE (1<<30)
#define RX62N_RD0_RACT (1<<31)
/** @} */
/**
* @name RD1 constants
* @{
*/
#define RX62N_RD1_RBL(x) (x>>16)
#define RX62N_RD1_RFL(x) (x&0xFFFF)
/** @} */
/**
* @name TD0 constants
* @{
*/
#define RX62N_TD0_TLOCKED (1<<9) /* Not an EDMAC flag.*/
#define RX62N_TD0_TFS_MASK ((1<<26)-1)
#define RX62N_TD0_TWBI (1<<26)
#define RX62N_TD0_TFE (1<<27)
#define RX62N_TD0_TFP_COF (0<<28)
#define RX62N_TD0_TFP_EOF (1<<28)
#define RX62N_TD0_TFP_SOF (2<<28)
#define RX62N_TD0_TFP_ONE (3<<28)
#define RX62N_TD0_TDLE (1<<30)
#define RX62N_TD0_TACT (1<<31)
/** @} */
/**
* @name TDES1 constants
* @{
*/
/** @} */
#define ETHERC_ECMR_RE (1<<6)
#define ETHERC_ECMR_TE (1<<5)
#define ETHERC_ECMR_ILB (1<<3)
#define ETHERC_ECMR_RTM (1<<2)
#define ETHERC_ECMR_DM (1<<1)
#define ETHERC_ECMR_PRM (1<<0)
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Number of available transmit buffers.
*/
#if !defined(RX62N_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
#define RX62N_MAC_TRANSMIT_BUFFERS 2
#endif
/**
* @brief Number of available receive buffers.
*/
#if !defined(RX62N_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
#define RX62N_MAC_RECEIVE_BUFFERS 2
#endif
/**
* @brief Maximum supported frame size.
*/
#if !defined(RX62N_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define RX62N_MAC_BUFFERS_SIZE 1536
#endif
/**
* @brief PHY detection timeout.
* @details Timeout, in milliseconds, for PHY address detection, if a PHY
* is not detected within the timeout then the driver halts during
* initialization. This setting applies only if the PHY address is
* not explicitly set in the board header file using
* @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
* single search path is performed.
*/
#if !defined(RX62N_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
#define RX62N_MAC_PHY_TIMEOUT 100
#endif
/**
* @brief Change the PHY power state inside the driver.
*/
#if !defined(RX62N_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
#define RX62N_MAC_ETH1_CHANGE_PHY_STATE TRUE
#endif
/**
* @brief ETHD1 interrupt priority level setting.
*/
#if !defined(RX62N_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define RX62N_MAC_ETH1_IRQ_PRIORITY 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (RX62N_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
#error "RX62N_MAC_PHY_TIMEOUT requires the realtime counter service"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of an RX62N Ethernet receive descriptor.
*/
typedef struct {
volatile uint32_t rd0;
volatile uint32_t rd1;
volatile uint32_t rd2;
volatile uint32_t pad;
} rx62n_eth_rx_descriptor_t;
/**
* @brief Type of an RX62N Ethernet transmit descriptor.
*/
typedef struct {
volatile uint32_t td0;
volatile uint32_t td1;
volatile uint32_t td2;
volatile uint32_t pad;
} rx62n_eth_tx_descriptor_t;
/**
* @brief Driver configuration structure.
*/
typedef struct {
/**
* @brief MAC address.
*/
uint8_t *mac_address;
/* End of the mandatory fields.*/
} MACConfig;
/**
* @brief Structure representing a MAC driver.
*/
struct MACDriver {
/**
* @brief Driver state.
*/
macstate_t state;
/**
* @brief Current configuration data.
*/
const MACConfig *config;
/**
* @brief Transmit semaphore.
*/
Semaphore tdsem;
/**
* @brief Receive semaphore.
*/
Semaphore rdsem;
#if MAC_USE_EVENTS || defined(__DOXYGEN__)
/**
* @brief Receive event.
*/
EventSource rdevent;
#endif
/* End of the mandatory fields.*/
/**
* @brief Link status flag.
*/
bool_t link_up;
/**
* @brief PHY address.
*/
uint8_t phyaddr;
/**
* @brief Receive next frame pointer.
*/
rx62n_eth_rx_descriptor_t *rxptr;
/**
* @brief Transmit next frame pointer.
*/
rx62n_eth_tx_descriptor_t *txptr;
};
/**
* @brief Structure representing a transmit descriptor.
*/
typedef struct {
/**
* @brief Current write offset.
*/
size_t offset;
/**
* @brief Available space size.
*/
size_t size;
/* End of the mandatory fields.*/
/**
* @brief Pointer to the physical descriptor.
*/
rx62n_eth_tx_descriptor_t *physdesc;
} MACTransmitDescriptor;
/**
* @brief Structure representing a receive descriptor.
*/
typedef struct {
/**
* @brief Current read offset.
*/
size_t offset;
/**
* @brief Available data size.
*/
size_t size;
/* End of the mandatory fields.*/
/**
* @brief Pointer to the physical descriptor.
*/
rx62n_eth_rx_descriptor_t *physdesc;
} MACReceiveDescriptor;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern MACDriver ETHD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void mac_lld_init(void);
void mac_lld_start(MACDriver *macp);
void mac_lld_stop(MACDriver *macp);
msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
MACTransmitDescriptor *tdp);
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp);
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
bool_t mac_lld_poll_link_status(MACDriver *macp);
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size);
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
uint8_t *buf,
size_t size);
#if MAC_USE_ZERO_COPY
uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
size_t size,
size_t *sizep);
const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
size_t *sizep);
#endif /* MAC_USE_ZERO_COPY */
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_MAC */
#endif /* _MAC_LLD_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/pal_lld.c
* @brief RX62N GPIO low level driver code.
*
* @addtogroup PAL
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void odrset(ioportid_t port, ioportmask_t mask) {
#if defined(RX62N_HAS_PORT0_OD)
if ( port == (ioportid_t)&PORT0 )
{
port->ODR |= mask;
return;
}
#endif
#if defined(RX62N_HAS_PORT1_OD)
if ( port == (ioportid_t)&PORT1 )
{
port->ODR |= mask;
return;
}
#endif
#if defined(RX62N_HAS_PORT2_OD)
if ( port == (ioportid_t)&PORT2 )
{
port->ODR |= mask;
return;
}
#endif
#if defined(RX62N_HAS_PORT3_OD)
if ( port == (ioportid_t)&PORT3 )
{
port->ODR |= mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTC_OD)
if ( port == (ioportid_t)&PORTC )
{
port->ODR |= mask;
return;
}
#endif
}
static void odrclear(ioportid_t port, ioportmask_t mask) {
#if defined(RX62N_HAS_PORT0_OD)
if ( port == (ioportid_t)&PORT0 )
{
port->ODR &= ~mask;
return;
}
#endif
#if defined(RX62N_HAS_PORT1_OD)
if ( port == (ioportid_t)&PORT1 )
{
port->ODR &= ~mask;
return;
}
#endif
#if defined(RX62N_HAS_PORT2_OD)
if ( port == (ioportid_t)&PORT2 )
{
port->ODR &= ~mask;
return;
}
#endif
#if defined(RX62N_HAS_PORT3_OD)
if ( port == (ioportid_t)&PORT3 )
{
port->ODR &= ~mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTC_OD)
if ( port == (ioportid_t)&PORTC )
{
port->ODR &= ~mask;
return;
}
#endif
}
static void pcrset(ioportid_t port, ioportmask_t mask) {
#if defined(RX62N_HAS_PORTA_PU)
if ( port == (ioportid_t)&PORTA )
{
port->PCR |= mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTB_PU)
if ( port == (ioportid_t)&PORTB )
{
port->PCR |= mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTC_PU)
if ( port == (ioportid_t)&PORTC )
{
port->PCR |= mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTD_PU)
if ( port == (ioportid_t)&PORTD )
{
port->PCR |= mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTE_PU)
if ( port == (ioportid_t)&PORTE )
{
port->PCR |= mask;
return;
}
#endif
}
static void pcrclear(ioportid_t port, ioportmask_t mask) {
#if defined(RX62N_HAS_PORTA_PU)
if ( port == (ioportid_t)&PORTA )
{
port->PCR &= ~mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTB_PU)
if ( port == (ioportid_t)&PORTB )
{
port->PCR &= ~mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTC_PU)
if ( port == (ioportid_t)&PORTC )
{
port->PCR &= ~mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTD_PU)
if ( port == (ioportid_t)&PORTD )
{
port->PCR &= ~mask;
return;
}
#endif
#if defined(RX62N_HAS_PORTE_PU)
if ( port == (ioportid_t)&PORTE )
{
port->PCR &= ~mask;
return;
}
#endif
}
static void initgpio(GPIO_TypeDef *gpiop, const rx62n_gpio_setup_t *config) {
gpiop->DDR = config->ddr;
gpiop->DR = config->dr;
gpiop->ICR = config->icr;
/*
gpiop->ODR = config->odr;
gpiop->PCR = config->pcr;
*/
odrset(gpiop, config->odr);
pcrset(gpiop, config->pcr);
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief RX62N I/O ports configuration.
* @param[in] config the RX62N ports configuration
*
* @notapi
*/
void _pal_lld_init(const PALConfig *config) {
/*
* Enables the GPIO related clocks (always enabled).
*/
/*
* Initial GPIO setup.
*/
initgpio((GPIO_TypeDef *)&PORT0, &config->P0Data);
initgpio((GPIO_TypeDef *)&PORT1, &config->P1Data);
initgpio((GPIO_TypeDef *)&PORT2, &config->P2Data);
initgpio((GPIO_TypeDef *)&PORT3, &config->P3Data);
initgpio((GPIO_TypeDef *)&PORT4, &config->P4Data);
initgpio((GPIO_TypeDef *)&PORT5, &config->P5Data);
#if RX62N_HAS_PORT6
initgpio((GPIO_TypeDef *)&PORT6, &config->P6Data);
#endif
#if RX62N_HAS_PORT7
initgpio((GPIO_TypeDef *)&PORT7, &config->P7Data);
#endif
#if RX62N_HAS_PORT8
initgpio((GPIO_TypeDef *)&PORT8, &config->P8Data);
#endif
#if RX62N_HAS_PORT9
initgpio((GPIO_TypeDef *)&PORT9, &config->P9Data);
#endif
initgpio((GPIO_TypeDef *)&PORTA, &config->PAData);
initgpio((GPIO_TypeDef *)&PORTB, &config->PBData);
initgpio((GPIO_TypeDef *)&PORTC, &config->PCData);
initgpio((GPIO_TypeDef *)&PORTD, &config->PDData);
#if RX62N_HAS_PORTE
initgpio((GPIO_TypeDef *)&PORTE, &config->PEData);
#endif
#if RX62N_HAS_PORTF
initgpio((GPIO_TypeDef *)&PORTF, &config->PFData);
#endif
#if RX62N_HAS_PORTG
initgpio((GPIO_TypeDef *)&PORTG, &config->PGData);
#endif
}
/**
* @brief Pads mode setup.
* @details This function programs a pads group belonging to the same port
* with the specified mode.
* @note @p PAL_MODE_UNCONNECTED is implemented as input (needs external
pull-up or pull-down resistor).
*
* @param[in] port the port identifier
* @param[in] mask the group mask
* @param[in] mode the mode
*
* @notapi
*/
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode) {
switch (mode) {
case PAL_MODE_RESET:
case PAL_MODE_INPUT:
case PAL_MODE_UNCONNECTED:
port->DDR &= ~mask;
pcrclear(port, mask);
break;
case PAL_MODE_INPUT_PULLUP:
port->DDR &= ~mask;
pcrset(port, mask);
break;
case PAL_MODE_OUTPUT_PUSHPULL:
port->DDR |= mask;
odrclear(port, mask);
break;
case PAL_MODE_OUTPUT_OPENDRAIN:
port->DDR |= mask;
odrset(port, mask);
break;
}
}
#endif /* HAL_USE_PAL */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/pal_lld.h
* @brief RX62N GPIO low level driver header.
*
* @addtogroup PAL
* @{
*/
#ifndef _PAL_LLD_H_
#define _PAL_LLD_H_
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Unsupported modes and specific modes */
/*===========================================================================*/
#undef PAL_MODE_INPUT_ANALOG
#undef PAL_MODE_INPUT_PULLDOWN
/*===========================================================================*/
/* I/O Ports Types and constants. */
/*===========================================================================*/
/**
* @brief RX62N GPIO registers block.
*/
typedef struct {
volatile uint8_t DDR;
uint8_t wk0[31];
union {
volatile uint8_t DR;
struct {
volatile unsigned char B0:1;
volatile unsigned char B1:1;
volatile unsigned char B2:1;
volatile unsigned char B3:1;
volatile unsigned char B4:1;
volatile unsigned char B5:1;
volatile unsigned char B6:1;
volatile unsigned char B7:1;
} BIT;
};
uint8_t wk1[31];
volatile uint8_t PORT;
uint8_t wk2[31];
volatile uint8_t ICR;
uint8_t wk3[31];
volatile uint8_t ODR;
uint8_t wk4[63];
volatile uint8_t PCR;
} GPIO_TypeDef;
/**
* @brief GPIO port setup info.
*/
typedef struct {
/** Initial value for DDR register.*/
uint8_t ddr;
/** Initial value for DR register.*/
uint8_t dr;
/** Initial value for ICR register.*/
uint8_t icr;
/** Initial value for ODR register.*/
uint8_t odr;
/** Initial value for PCR register.*/
uint8_t pcr;
} rx62n_gpio_setup_t;
/**
* @brief RX62N GPIO static initializer.
* @details An instance of this structure must be passed to @p palInit() at
* system startup time in order to initialize the digital I/O
* subsystem. This represents only the initial setup, specific pads
* or whole ports can be reprogrammed at later time.
*/
typedef struct {
/** @brief Port 0 setup data.*/
rx62n_gpio_setup_t P0Data;
/** @brief Port 1 setup data.*/
rx62n_gpio_setup_t P1Data;
/** @brief Port 2 setup data.*/
rx62n_gpio_setup_t P2Data;
/** @brief Port 3 setup data.*/
rx62n_gpio_setup_t P3Data;
/** @brief Port 4 setup data.*/
rx62n_gpio_setup_t P4Data;
/** @brief Port 5 setup data.*/
rx62n_gpio_setup_t P5Data;
#if RX62N_HAS_PORT6
/** @brief Port 6 setup data.*/
rx62n_gpio_setup_t P6Data;
#endif
#if RX62N_HAS_PORT7
/** @brief Port 7 setup data.*/
rx62n_gpio_setup_t P7Data;
#endif
#if RX62N_HAS_PORT8
/** @brief Port 8 setup data.*/
rx62n_gpio_setup_t P8Data;
#endif
#if RX62N_HAS_PORT9
/** @brief Port 9 setup data.*/
rx62n_gpio_setup_t P9Data;
#endif
/** @brief Port A setup data.*/
rx62n_gpio_setup_t PAData;
/** @brief Port B setup data.*/
rx62n_gpio_setup_t PBData;
/** @brief Port C setup data.*/
rx62n_gpio_setup_t PCData;
/** @brief Port D setup data.*/
rx62n_gpio_setup_t PDData;
#if RX62N_HAS_PORTE
/** @brief Port E setup data.*/
rx62n_gpio_setup_t PEData;
#endif
#if RX62N_HAS_PORTx
/** @brief Port x setup data.*/
/* rx62n_gpio_setup_t PxData;*/
#endif
} PALConfig;
/**
* @brief Width, in bits, of an I/O port.
*/
#define PAL_IOPORTS_WIDTH 8
/**
* @brief Whole port mask.
* @details This macro specifies all the valid bits into a port.
*/
#define PAL_WHOLE_PORT ( (ioportmask_t)( ( 1 << PAL_IOPORTS_WIDTH ) - 1 ) )
/**
* @brief Digital I/O port sized unsigned type.
*/
typedef uint8_t ioportmask_t;
/**
* @brief Digital I/O modes.
*/
typedef uint8_t iomode_t;
/**
* @brief Port Identifier.
* @details This type can be a scalar or some kind of pointer, do not make
* any assumption about it, use the provided macros when populating
* variables of this type.
*/
typedef GPIO_TypeDef * ioportid_t;
/*===========================================================================*/
/* I/O Ports Identifiers. */
/* The low level driver wraps the definitions already present in the RX62N */
/* iodefine_gcc62n.h. */
/*===========================================================================*/
/**
* @brief GPIO port 0 identifier.
*/
#if RX62N_HAS_PORT0 || defined(__DOXYGEN__)
#define GPIO0 ((GPIO_TypeDef *)(&PORT0))
#define IOPORT1 ((GPIO_TypeDef *)(&PORT0))
#endif
/**
* @brief GPIO port 1 identifier.
*/
#if RX62N_HAS_PORT1 || defined(__DOXYGEN__)
#define GPIO1 ((GPIO_TypeDef *)(&PORT1))
#define IOPORT2 ((GPIO_TypeDef *)(&PORT1))
#endif
/**
* @brief GPIO port 2 identifier.
*/
#if RX62N_HAS_PORT2 || defined(__DOXYGEN__)
#define GPIO2 ((GPIO_TypeDef *)(&PORT2))
#define IOPORT3 ((GPIO_TypeDef *)(&PORT2))
#endif
/**
* @brief GPIO port 3 identifier.
*/
#if RX62N_HAS_PORT3 || defined(__DOXYGEN__)
#define GPIO3 ((GPIO_TypeDef *)(&PORT3))
#define IOPORT4 ((GPIO_TypeDef *)(&PORT3))
#endif
/**
* @brief GPIO port 4 identifier.
*/
#if RX62N_HAS_PORT4 || defined(__DOXYGEN__)
#define GPIO4 ((GPIO_TypeDef *)(&PORT4))
#define IOPORT5 ((GPIO_TypeDef *)(&PORT4))
#endif
/**
* @brief GPIO port 5 identifier.
*/
#if RX62N_HAS_PORT5 || defined(__DOXYGEN__)
#define GPIO5 ((GPIO_TypeDef *)(&PORT5))
#define IOPORT6 ((GPIO_TypeDef *)(&PORT5))
#endif
/**
* @brief GPIO port 6 identifier.
*/
#if RX62N_HAS_PORT6 || defined(__DOXYGEN__)
#define GPIO6 ((GPIO_TypeDef *)(&PORT6))
#define IOPORT7 ((GPIO_TypeDef *)(&PORT6))
#endif
/**
* @brief GPIO port 7 identifier.
*/
#if RX62N_HAS_PORT7 || defined(__DOXYGEN__)
#define GPIO7 ((GPIO_TypeDef *)(&PORT7))
#define IOPORT8 ((GPIO_TypeDef *)(&PORT7))
#endif
/**
* @brief GPIO port 8 identifier.
*/
#if RX62N_HAS_PORT8 || defined(__DOXYGEN__)
#define GPIO8 ((GPIO_TypeDef *)(&PORT8))
#define IOPORT9 ((GPIO_TypeDef *)(&PORT8))
#endif
/**
* @brief GPIO port 9 identifier.
*/
#if RX62N_HAS_PORT9 || defined(__DOXYGEN__)
#define GPIO9 ((GPIO_TypeDef *)(&PORT9))
#define IOPORT10 ((GPIO_TypeDef *)(&PORT9))
#endif
/**
* @brief GPIO port 10 identifier.
*/
#if RX62N_HAS_PORTA || defined(__DOXYGEN__)
#define GPIO10 ((GPIO_TypeDef *)(&PORTA))
#define IOPORT11 ((GPIO_TypeDef *)(&PORTA))
#endif
/**
* @brief GPIO port 11 identifier.
*/
#if RX62N_HAS_PORTB || defined(__DOXYGEN__)
#define GPIO11 ((GPIO_TypeDef *)(&PORTB))
#define IOPORT12 ((GPIO_TypeDef *)(&PORTB))
#endif
/**
* @brief GPIO port 12 identifier.
*/
#if RX62N_HAS_PORTC || defined(__DOXYGEN__)
#define GPIO12 ((GPIO_TypeDef *)(&PORTC))
#define IOPORT13 ((GPIO_TypeDef *)(&PORTC))
#endif
/**
* @brief GPIO port 13 identifier.
*/
#if RX62N_HAS_PORTD || defined(__DOXYGEN__)
#define GPIO13 ((GPIO_TypeDef *)(&PORTD))
#define IOPORT14 ((GPIO_TypeDef *)(&PORTD))
#endif
/**
* @brief GPIO port 14 identifier.
*/
#if RX62N_HAS_PORTE || defined(__DOXYGEN__)
#define GPIO14 ((GPIO_TypeDef *)(&PORTE))
#define IOPORT15 ((GPIO_TypeDef *)(&PORTE))
#endif
/**
* @brief GPIO port 15 identifier.
*/
#if RX62N_HAS_PORTF || defined(__DOXYGEN__)
#define GPIO15 ((GPIO_TypeDef *)(&PORTF))
#define IOPORT16 ((GPIO_TypeDef *)(&PORTF))
#endif
/**
* @brief GPIO port 16 identifier.
*/
#if RX62N_HAS_PORTG || defined(__DOXYGEN__)
#define GPIO16 ((GPIO_TypeDef *)(&PORTG))
#define IOPORT17 ((GPIO_TypeDef *)(&PORTG))
#endif
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */
/*===========================================================================*/
/**
* @brief GPIO ports subsystem initialization.
*
* @notapi
*/
#define pal_lld_init(config) _pal_lld_init(config)
/**
* @brief Reads an I/O port.
* @details This function is implemented by reading the GPIO IDR register, the
* implementation has no side effects.
* @note This function is not meant to be invoked directly by the application
* code.
*
* @param[in] port port identifier
* @return The port bits.
*
* @notapi
*/
#define pal_lld_readport(port) ((port)->PORT)
/**
* @brief Reads the output latch.
* @details This function is implemented by reading the GPIO ODR register, the
* implementation has no side effects.
* @note This function is not meant to be invoked directly by the application
* code.
*
* @param[in] port port identifier
* @return The latched logical states.
*
* @notapi
*/
#define pal_lld_readlatch(port) ((port)->DR)
/**
* @brief Writes on a I/O port.
* @details This function is implemented by writing the GPIO ODR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be written on the specified port
*
* @notapi
*/
#define pal_lld_writeport(port, bits) ((port)->DR = (bits))
/**
* @brief Sets a bits mask on a I/O port.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be ORed on the specified port
*
* @notapi
*/
/*
#define pal_lld_setport(port, bits)
*/
/**
* @brief Clears a bits mask on a I/O port.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be cleared on the specified port
*
* @notapi
*/
/*
#define pal_lld_clearport(port, bits)
*/
/**
* @brief Writes a group of bits.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset the group bit offset within the port
* @param[in] bits bits to be written. Values exceeding the group
* width are masked.
*
* @notapi
*/
/*
#define pal_lld_writegroup(port, mask, offset, bits)
*/
/**
* @brief Pads group mode setup.
* @details This function programs a pads group belonging to the same port
* with the specified mode.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset group bit offset within the port
* @param[in] mode group mode
*
* @notapi
*/
#define pal_lld_setgroupmode(port, mask, offset, mode) \
_pal_lld_setgroupmode(port, mask << offset, mode)
/**
* @brief Writes a logical state on an output pad.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
* @param[in] bit logical value, the value must be @p PAL_LOW or
* @p PAL_HIGH
*
* @notapi
*/
#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
extern const PALConfig pal_default_config;
#ifdef __cplusplus
extern "C" {
#endif
void _pal_lld_init(const PALConfig *config);
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_PAL */
#endif /* _PAL_LLD_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/rx62n_mii.c
* @brief RX62N low level MII driver code.
*
* @addtogroup RX62N_MII
* @{
*/
#include "ch.h"
#include "hal.h"
#include "rx62n_mii.h"
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#if (RX62N_SYSCLK == 96000000)
__attribute__((always_inline))
static inline void delay200ns(void) {
asm volatile ("mov.l #5,r2 \n\t"
"1: \n\t"
"sub #1,r2 \n\t"
"bne.b 1b \n\t");
}
__attribute__((always_inline))
static inline void delay1ms(void) {
asm volatile ("mov.l #24000,r2 \n\t"
"1: \n\t"
"sub #1,r2 \n\t"
"bne.b 1b \n\t");
}
#else
#error Adjust delay200ns and delay1ms for RX62N_SYSCLK other than 96MHz.
#endif
/**
* @brief Write 1 bit to SMI bus.
*
* @param[in] b the bit value
*/
static void smi_bit_w(uint32_t b) {
uint32_t pir = PIR_MMD;
if (b)
pir |= PIR_MDO;
ETHERC.PIR.LONG = pir;
/* wait 10ns */
asm volatile("nop");
ETHERC.PIR.LONG = pir | PIR_MDC;
delay200ns();
ETHERC.PIR.LONG = pir;
delay200ns();
}
/**
* @brief Read 1 bit from SMI bus.
*
* @return The bit value.
*/
static uint32_t smi_bit_r(void) {
uint32_t pir = 0;
ETHERC.PIR.LONG = PIR_MDC;
delay200ns();
ETHERC.PIR.LONG = 0;
delay200ns();
if (ETHERC.PIR.LONG & PIR_MDI)
pir = 1;
return pir;
}
/**
* @brief Release SMI bus.
*/
static void smi_z0(void) {
ETHERC.PIR.LONG = PIR_MDC;
delay200ns();
ETHERC.PIR.LONG = 0;
delay200ns();
}
/**
* @brief Write up to 32 bits to SMI bus (MSB first).
*
* @note Writing starts from len-1 bit.
* @param[in] value value to write
* @param[in] len number of bits
*/
static void smi_write(uint32_t value, uint8_t len) {
while (len--)
smi_bit_w(value & (1<<len) );
}
/**
* @brief Read up to 16 bits from SMI bus (MSB first).
*
* @param[in] len number of bits
* @return The bits value.
*/
static phyreg_t smi_read(uint8_t len) {
phyreg_t value = 0;
while (len--) {
value <<= 1;
if (smi_bit_r())
value |= 1;
}
return value;
}
static phyreg_t mii_read_reg(uint8_t phyaddr, phyaddr_t regaddr) {
phyreg_t value;
/* preamble */
smi_write(0xFFFFFFFF, 32);
/* start of frame */
smi_write(1, 2);
/* opcode (read) */
smi_write(2, 2);
/* phy address */
smi_write(phyaddr, 5);
/* phy register */
smi_write(regaddr, 5);
/* turn around */
smi_z0();
/* phy register */
value = smi_read(16);
/* idle */
smi_z0();
return value;
}
static void mii_write_reg(uint8_t phyaddr, phyaddr_t regaddr, phyreg_t value) {
/* preamble */
smi_write(0xFFFFFFFF, 32);
/* start of frame */
smi_write(1, 2);
/* opcode (write) */
smi_write(1, 2);
/* phy address */
smi_write(phyaddr, 5);
/* phy register */
smi_write(regaddr, 5);
/* turn around */
smi_write(1, 2);
/* phy register */
smi_write(value, 16);
/* idle */
ETHERC.PIR.LONG = 0;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level MII driver initialization.
*
* @notapi
*/
void miiInit(void) {
}
/**
* @brief Resets a PHY device.
*
* @param[in] macp pointer to the @p MACDriver object
*
* @notapi
*/
void miiReset(MACDriver *macp) {
(void)macp;
/*
* PHY reset by pulsing the RESET_OUT pin.
*/
ETHERC.PIR.LONG = 0;
/* Release PHY pins */
IOPORT.PFENET.BYTE = 0;
/* Pulse RESET_OUT pin */
palClearPad(GPIO10, PORTA_ETH_RESETOUT);
delay1ms();
palSetPad(GPIO10, PORTA_ETH_RESETOUT);
delay1ms();
/* Enable Ethernet pins, set RMII mode */
IOPORT.PFENET.BYTE = (1<<7)|(0<<4)|(1<<1);
}
/**
* @brief Reads a PHY register through the MII interface.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[in] addr the register address
* @return The register value.
*
* @notapi
*/
phyreg_t miiGet(MACDriver *macp, phyaddr_t regaddr) {
(void)macp;
return mii_read_reg(macp->phyaddr, regaddr);
}
/**
* @brief Writes a PHY register through the MII interface.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[in] addr the register address
* @param[in] value the new register value
*
* @notapi
*/
void miiPut(MACDriver *macp, phyaddr_t regaddr, phyreg_t value) {
(void)macp;
mii_write_reg(macp->phyaddr, regaddr, value);
}
#endif /* HAL_USE_MAC */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/rx62n_mii.h
* @brief RX62N low level MII driver header.
*
* @addtogroup RX62N_MII
* @{
*/
#ifndef _RX62N_MII_H_
#define _RX62N_MII_H_
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* PIR bit definitions.
*/
#define PIR_MDC (1<<0)
#define PIR_MMD (1<<1)
#define PIR_MDO (1<<2)
#define PIR_MDI (1<<3)
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of a PHY register value.
*/
typedef uint16_t phyreg_t;
/**
* @brief Type of a PHY register address.
*/
typedef uint8_t phyaddr_t;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void miiInit(void);
void miiReset(MACDriver *macp);
phyreg_t miiGet(MACDriver *macp, phyaddr_t addr);
void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_MAC */
#endif /* _RX62N_MII_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/serial_lld.c
* @brief RX62N low level serial driver code.
*
* @addtogroup SERIAL
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__)
/** @brief UART0 serial driver identifier.*/
SerialDriver SD1;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/** @brief Driver default configuration.*/
static const SerialConfig default_config = {
.sc_speed = SERIAL_DEFAULT_BITRATE,
.sc_scr = 0, /* only bits 0-1 used */
.sc_smr = 0,
.sc_semr = 0,
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief UART initialization.
*
* @param[in] sdp communication channel associated to the UART
* @param[in] config the architecture-dependent serial driver configuration
* @todo Test all possible SMR and SEMR clock settings
*/
static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
volatile struct st_sci *u = sdp->uart;
uint32_t brr;
u->SCR.BYTE = config->sc_scr & 0x03;
u->SMR.BYTE = config->sc_smr;
u->SEMR.BYTE = config->sc_semr;
brr = ( 32 << ( 2 * ( config->sc_smr & 3 ) ) ) >> ( ( config->sc_semr & 0x10 ) ? 1 : 0 );
brr = RX62N_PERCLK / ( brr * config->sc_speed ) - 1;
u->BRR = brr;
/* TODO: delay 1-bit interval */
u->SCR.BYTE |= 0x70;
}
/**
* @brief UART de-initialization.
*
* @param[in] u pointer to an UART I/O block
*/
static void uart_deinit(volatile struct st_sci *u) {
u->SCR.BYTE = 0;
u->SMR.BYTE = 0;
u->SEMR.BYTE = 0;
u->BRR = 0;
}
/**
* @brief Error handling routine.
*
* @param[in] sdp communication channel associated to the UART
* @param[in] err UART LSR register value
*/
static void set_error(SerialDriver *sdp, uint32_t err) {
flagsmask_t sts = 0;
if (err & SSR_ORER)
sts |= SD_OVERRUN_ERROR;
if (err & SSR_PER)
sts |= SD_PARITY_ERROR;
if (err & SSR_FER)
sts |= SD_FRAMING_ERROR;
chSysLockFromIsr();
chnAddFlagsI(sdp, sts);
chSysUnlockFromIsr();
}
#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__)
/**
* @brief Error IRQ handler.
*
* @param[in] sdp communication channel associated to the UART
*/
static void serve_interrupt_eri(SerialDriver *sdp) {
volatile struct st_sci *u = sdp->uart;
set_error(sdp, u->SSR.BYTE);
u->SSR.BYTE &= ~((1<<3)|(1<<4)|(1<<5)); /* clear error flags */
}
/**
* @brief Receive IRQ handler.
*
* @param[in] sdp communication channel associated to the UART
*/
static void serve_interrupt_rxi(SerialDriver *sdp) {
volatile struct st_sci *u = sdp->uart;
chSysLockFromIsr();
sdIncomingDataI(sdp, u->RDR);
chSysUnlockFromIsr();
}
/**
* @brief Transmit IRQ handler.
*
* @param[in] sdp communication channel associated to the UART
*/
static void serve_interrupt_txi(SerialDriver *sdp) {
volatile struct st_sci *u = sdp->uart;
msg_t b;
chSysLockFromIsr();
if (!u->SSR.BIT.TDRE) {
/* forced by notify */
chSysUnlockFromIsr();
return;
}
b = chOQGetI(&sdp->oqueue);
chSysUnlockFromIsr();
if (b < Q_OK) {
u->SCR.BIT.TIE = 0;
chSysLockFromIsr();
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
chSysUnlockFromIsr();
return;
}
u->TDR = b;
}
/**
* @brief Transmission end IRQ handler.
*
* @param[in] sdp communication channel associated to the UART
*/
static void serve_interrupt_tei(SerialDriver *sdp) {
chSysLockFromIsr();
chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
chSysUnlockFromIsr();
}
/**
* @brief Driver SD1 output notification.
*/
static void notify1(GenericQueue *qp) {
(void)qp;
SD1.uart->SCR.BIT.TIE = 1;
IR(SCI0,TXI0) = 1; /* Set Interrupt Enable Register */
}
#endif
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief UART0 IRQ handler.
*
* @isr
*/
#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(Excep_SCI0_ERI0) {
CH_IRQ_PROLOGUE();
serve_interrupt_eri(&SD1);
CH_IRQ_EPILOGUE();
}
CH_IRQ_HANDLER(Excep_SCI0_RXI0) {
CH_IRQ_PROLOGUE();
serve_interrupt_rxi(&SD1);
CH_IRQ_EPILOGUE();
}
CH_IRQ_HANDLER(Excep_SCI0_TXI0) {
CH_IRQ_PROLOGUE();
serve_interrupt_txi(&SD1);
CH_IRQ_EPILOGUE();
}
CH_IRQ_HANDLER(Excep_SCI0_TEI0) {
CH_IRQ_PROLOGUE();
serve_interrupt_tei(&SD1);
CH_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level serial driver initialization.
*
* @notapi
*/
void sd_lld_init(void) {
#if RX62N_SERIAL_USE_UART0
sdObjectInit(&SD1, NULL, notify1);
SD1.uart = &SCI0;
PORT2.ICR.BIT.B1 = 1;
#endif
}
/**
* @brief Low level serial driver configuration and (re)start.
*
* @param[in] sdp pointer to a @p SerialDriver object
* @param[in] config the architecture-dependent serial driver configuration.
* If this parameter is set to @p NULL then a default
* configuration is used.
*
* @notapi
*/
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (config == NULL)
config = &default_config;
if (sdp->state == SD_STOP) {
#if RX62N_SERIAL_USE_UART0
if (&SD1 == sdp) {
MSTP(SCI0) = 0; /* Enable SCI0 (cancel module stop state) */
IEN(SCI0,RXI0) = 1;
IEN(SCI0,TXI0) = 1;
IEN(SCI0,ERI0) = 1;
IPR(SCI0,TXI0) = RX62N_SERIAL_UART0_IRQ_PRIORITY;
}
#endif
}
uart_init(sdp, config);
}
/**
* @brief Low level serial driver stop.
* @details De-initializes the UART, stops the associated clock, resets the
* interrupt vector.
*
* @param[in] sdp pointer to a @p SerialDriver object
*
* @notapi
*/
void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) {
uart_deinit(sdp->uart);
#if RX62N_SERIAL_USE_UART0
if (&SD1 == sdp) {
IEN(SCI0,RXI0) = 0;
IEN(SCI0,TXI0) = 0;
IEN(SCI0,ERI0) = 0;
MSTP(SCI0) = 1; /* Disable SCI0 (enter module stop state) */
return;
}
#endif
}
}
#endif /* HAL_USE_SERIAL */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/serial_lld.h
* @brief RX62N low level serial driver header.
*
* @addtogroup SERIAL
* @{
*/
#ifndef _SERIAL_LLD_H_
#define _SERIAL_LLD_H_
#if HAL_USE_SERIAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
#define SSR_ORER (1<<5)
#define SSR_FER (1<<4)
#define SSR_PER (1<<3)
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief UART0 driver enable switch.
* @details If set to @p TRUE the support for UART0 is included.
* @note The default is @p TRUE .
*/
#if !defined(RX62N_SERIAL_USE_UART0) || defined(__DOXYGEN__)
#define RX62N_SERIAL_USE_UART0 FALSE
#endif
/**
* @brief UART0 PCLK divider.
*/
#if !defined(RX62N_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__)
#define RX62N_SERIAL_UART0CLKDIV 1
#endif
/**
* @brief UART0 interrupt priority level setting.
*/
#if !defined(RX62N_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define RX62N_SERIAL_UART0_IRQ_PRIORITY 3
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief RX62N8 Serial Driver configuration structure.
* @details An instance of this structure must be passed to @p sdStart()
* in order to configure and start a serial driver operations.
*/
typedef struct {
/**
* @brief Bit rate.
*/
uint32_t sc_speed;
/**
* @brief Initialization value for the SCR register.
*/
uint8_t sc_scr;
/**
* @brief Initialization value for the SMR register.
*/
uint8_t sc_smr;
/**
* @brief Initialization value for the SEMR register.
*/
uint8_t sc_semr;
} SerialConfig;
/**
* @brief @p SerialDriver specific data.
*/
#define _serial_driver_data \
_base_asynchronous_channel_data \
/* Driver state.*/ \
sdstate_t state; \
/* Input queue.*/ \
InputQueue iqueue; \
/* Output queue.*/ \
OutputQueue oqueue; \
/* Input circular buffer.*/ \
uint8_t ib[SERIAL_BUFFERS_SIZE]; \
/* Output circular buffer.*/ \
uint8_t ob[SERIAL_BUFFERS_SIZE]; \
/* End of the mandatory fields.*/ \
/* Pointer to the USART registers block.*/ \
volatile struct st_sci *uart;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if RX62N_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
extern SerialDriver SD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void sd_lld_init(void);
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
void sd_lld_stop(SerialDriver *sdp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_SERIAL */
#endif /* _SERIAL_LLD_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/usb_lld.c
* @brief RX62N USB Driver subsystem low level driver source.
*
* @addtogroup USB
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_USB || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @brief PIPEnCTR register union.
*/
typedef union {
unsigned short WORD;
struct {
unsigned short PID:2;
unsigned short :3;
unsigned short PBUSY:1;
unsigned short SQMON:1;
unsigned short SQSET:1;
unsigned short SQCLR:1;
unsigned short ACLRM:1;
unsigned short ATREPM:1;
unsigned short :3;
unsigned short INBUFM:1;
unsigned short BSTS:1;
} BIT;
} pipectr_t;;
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief USB1 driver identifier.*/
#if RX62N_USE_USB0 || defined(__DOXYGEN__)
USBDriver USBD1;
#endif
/** @brief USB2 driver identifier.*/
#if RX62N_USE_USB1 || defined(__DOXYGEN__)
USBDriver USBD2;
#error "USBD2 is not supported yet"
#endif
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/**
* @brief EP0 state.
* @note It is an union because IN and OUT endpoints are never used at the
* same time for EP0.
*/
static union {
/**
* @brief IN EP0 state.
*/
USBInEndpointState in;
/**
* @brief OUT EP0 state.
*/
USBOutEndpointState out;
} ep0_state;
/**
* @brief Buffer for the EP0 setup packets.
*/
static uint8_t ep0setup_buffer[8];
/**
* @brief EP0 initialization structure.
*/
static const USBEndpointConfig ep0config = {
USB_EP_MODE_TYPE_CTRL,
_usb_ep0setup,
_usb_ep0in,
_usb_ep0out,
USB_EP0_PACKET_SIZE,
USB_EP0_PACKET_SIZE,
&ep0_state.in,
&ep0_state.out,
1,
ep0setup_buffer
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
pipectr_t usb_pipectr_read(USBDriver *usbp, usbep_t ep) {
volatile pipectr_t *pipe = (pipectr_t *)&usbp->usb->PIPE1CTR;
return pipe[ep-1];
}
void usb_pipectr_write(USBDriver *usbp, usbep_t ep, uint16_t p) {
volatile pipectr_t *pipe = (pipectr_t *)&usbp->usb->PIPE1CTR;
pipe[ep-1].WORD = p;
}
/**
* @brief Reads from a dedicated packet buffer.
*
* @param[in] udp pointer to a @p stm32_usb_descriptor_t
* @param[out] buf buffer where to copy the packet data
* @param[in] n maximum number of bytes to copy. This value must
* not exceed the maximum packet size for this endpoint.
*
* @notapi
*/
static void usb_packet_read_to_buffer(USBDriver *usbp, usbep_t ep,
uint8_t *buf, size_t n) {
uint32_t i;
usbp->epc[ep]->in_state->transmitted = n;
if (ep == 0) {
for (i = 0; i < n; i++)
usbp->epc[ep]->out_state->mode.linear.rxbuf[i] = usbp->usb->CFIFO.BYTE.L;
}
else {
for (i = 0; i < n; i++)
usbp->epc[ep]->out_state->mode.linear.rxbuf[i] = usbp->usb->D0FIFO.BYTE.L;
}
}
/**
* @brief Reads from a dedicated packet buffer.
*
* @param[in] udp pointer to a @p stm32_usb_descriptor_t
* @param[in] iqp pointer to an @p InputQueue object
* @param[in] n maximum number of bytes to copy. This value must
* not exceed the maximum packet size for this endpoint.
*
* @notapi
*/
static void usb_packet_read_to_queue(USBDriver *usbp, usbep_t ep, InputQueue *iqp, size_t n) {
size_t nhw = n;
uint8_t c;
while (nhw > 0) {
if (ep == 0) {
c = usbp->usb->CFIFO.BYTE.L;
}
else {
/* ep 1..9 */
c = usbp->usb->D0FIFO.BYTE.L;;
}
*iqp->q_wrptr++ = c;
if (iqp->q_wrptr >= iqp->q_top)
iqp->q_wrptr = iqp->q_buffer;
nhw--;
}
/* Updating queue.*/
chSysLockFromIsr();
iqp->q_counter += n;
while (notempty(&iqp->q_waiting))
chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK;
chSysUnlockFromIsr();
}
/**
* @brief Writes to a dedicated packet buffer.
*
* @param[in] buf buffer where to fetch the packet data
* @param[in] n maximum number of bytes to copy. This value must
* not exceed the maximum packet size for this endpoint.
*
* @notapi
*/
static void usb_packet_write_from_buffer(USBDriver *usbp, usbep_t ep,
const uint8_t *buf, size_t n) {
usbp->epc[ep]->in_state->transmitted = n;
if (ep == 0) {
while (n--) {
usbp->usb->CFIFO.BYTE.L = *buf++;
}
}
else {
/* ep 1..9 */
usbp->usb->D1FIFO.BYTE.L = *buf++;
}
}
/**
* @brief Writes to a dedicated packet buffer.
*
* @param[in] udp pointer to a @p stm32_usb_descriptor_t
* @param[in] buf buffer where to fetch the packet data
* @param[in] n maximum number of bytes to copy. This value must
* not exceed the maximum packet size for this endpoint.
*
* @notapi
*/
static void usb_packet_write_from_queue(USBDriver *usbp, usbep_t ep,
OutputQueue *oqp, size_t n) {
size_t nhw = n;
uint8_t c;
usbp->epc[ep]->in_state->transmitted = n;
while (nhw > 0) {
c = *oqp->q_rdptr++;;
if (ep == 0) {
usbp->usb->CFIFO.BYTE.L = c;
}
else {
/* ep 1..9 */
usbp->usb->D1FIFO.BYTE.L = c;
}
c = c;
if (oqp->q_rdptr >= oqp->q_top)
oqp->q_rdptr = oqp->q_buffer;
nhw--;
}
/* Updating queue. Note, the lock is done in this unusual way because this
function can be called from both ISR and thread context so the kind
of lock function to be invoked cannot be decided beforehand.*/
/*
TODO: port_lock() doesn't work.*/
if (port_enabled()) {
dbg_enter_lock();
chSysLock();
oqp->q_counter += n;
while (notempty(&oqp->q_waiting))
chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
chSysUnlock();
dbg_leave_lock();
}
else {
oqp->q_counter += n;
while (notempty(&oqp->q_waiting))
chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK;
}
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if RX62N_USE_USB0 || defined(__DOXYGEN__)
void usb_lld_serve_interrupt(USBDriver *usbp) {
uint16_t sts0, sts0clr;
uint16_t ep = 0;
sts0 = usbp->usb->INTSTS0.WORD;
sts0clr = (~(sts0 & usbp->usb->INTENB0.WORD))|
INTSTS0_VALID|INTSTS0_DVST|INTSTS0_CTRT;
if (sts0 & INTSTS0_RESM) {
/* _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESUME);*/
}
/* USB bus WAKEUP condition handling.*/
/*
if (isr & AT91C_UDP_WAKEUP) {
_usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP);
}
*/
/* SOF handling.*/
/*
if (isr & AT91C_UDP_SOFINT) {
_usb_isr_invoke_sof_cb(usbp);
}
*/
if (sts0 & INTSTS0_DVST) {
usbp->usb->INTSTS0.BIT.DVST = 0;
switch (INTSTS0_DVSQ(sts0)) {
case DVSQ_POWERED:
break;
case DVSQ_DEFAULT:
if ( !(sts0 & INTSTS0_RESM) && (usbp->last_dvst != DVSQ_ADDRESS) &&
(usbp->last_dvst != DVSQ_SUSPENDED_DEF)) {
_usb_reset(usbp);
_usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
}
break;
case DVSQ_ADDRESS:
break;
case DVSQ_CONFIGURED:
break;
default:
/* Default is suspened state */
_usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND);
break;
}
usbp->last_dvst = INTSTS0_DVSQ(sts0);
}
if (sts0 & INTSTS0_CTRT) {
switch (INTSTS0_CTSQ(sts0)) {
case CTSQ_IDLE_OR_SETUP:
if (usbp->last_ctsq == CTSQ_READ_STATUS) {
_usb_isr_invoke_out_cb(usbp, ep);
}
else if (usbp->last_ctsq == CTSQ_WRITE_STATUS) {
_usb_isr_invoke_in_cb(usbp, ep);
}
else if (usbp->last_ctsq == CTSQ_NODATA_STATUS) {
_usb_isr_invoke_in_cb(usbp, ep);
}
break;
default:
break;
}
usbp->last_ctsq = INTSTS0_CTSQ(sts0);
usbp->usb->INTSTS0.BIT.CTRT = 0;
}
if (sts0 & INTSTS0_VALID) {
usbp->usb->INTSTS0.BIT.VALID = 0;
_usb_isr_invoke_setup_cb(usbp, ep);
if (INTSTS0_CTSQ(sts0) == CTSQ_NODATA_STATUS) {
usbp->usb->DCPCTR.BIT.PID = PID_BUF;
usbp->usb->DCPCTR.BIT.CCPL = 1;
}
}
if (sts0 & INTSTS0_BRDY) {
/* BRDY */
uint16_t brdysts = usbp->usb->BRDYSTS.WORD;
const USBEndpointConfig *epcp;
size_t n;
for (ep=0; ep<USB_MAX_ENDPOINTS; ep++) {
if (brdysts & (1<<ep)) {
epcp = usbp->epc[ep];
if (ep == 0) {
n = usbp->usb->CFIFOCTR.BIT.DTLN;
}
else {
if (epcp->out_state) {
usbp->usb->PIPESEL.BIT.PIPESEL = ep;
do {
usbp->usb->D0FIFOSEL.WORD = ep;
} while (usbp->usb->D0FIFOSEL.WORD != ep);
while (!usbp->usb->D0FIFOCTR.BIT.FRDY);
n = usbp->usb->D0FIFOCTR.BIT.DTLN;
}
else {
/* in_state */
usbp->usb->PIPESEL.BIT.PIPESEL = ep;
do {
usbp->usb->D1FIFOSEL.WORD = ep;
} while (usbp->usb->D1FIFOSEL.WORD != ep);
while (!usbp->usb->D1FIFOCTR.BIT.FRDY);
n = 0; /* Omit compiler warning */
}
}
if (epcp->out_state) {
/* Reads the packet into the defined buffer.*/
if (epcp->out_state->rxqueued) {
usb_packet_read_to_queue(usbp, ep,
epcp->out_state->mode.queue.rxqueue, n);
}
else {
usb_packet_read_to_buffer(usbp, ep,
epcp->out_state->mode.linear.rxbuf, n);
epcp->out_state->mode.linear.rxbuf += n;
}
/* Transaction data updated.*/
epcp->out_state->rxcnt += n;
epcp->out_state->rxsize -= n;
epcp->out_state->rxpkts -= 1;
if (epcp->out_state->rxpkts > 0) {
/* Transfer not completed, there are more packets to receive.*/
}
else {
/* Transfer completed, invokes the callback.*/
/* Set pipe to NAK */
usb_pipectr_write(usbp, ep, PID_NAK);
_usb_isr_invoke_out_cb(usbp, ep);
}
}
else {
epcp->in_state->txcnt += epcp->in_state->transmitted;
epcp->in_state->txsize -= epcp->in_state->transmitted;
if (epcp->in_state->txsize > 0) {
/* Transfer not completed, there are more packets to send.*/
if (epcp->in_state->txsize > epcp->in_maxsize)
n = epcp->in_maxsize;
else
n = epcp->in_state->txsize;
if (epcp->in_state->txqueued) {
usb_packet_write_from_queue(usbp, ep,
epcp->in_state->mode.queue.txqueue, n);
}
else {
epcp->in_state->mode.linear.txbuf += epcp->in_state->transmitted;
usb_packet_write_from_buffer(usbp, ep,
epcp->in_state->mode.linear.txbuf, n);
}
chSysLockFromIsr();
usb_lld_start_in(usbp, ep);
chSysUnlockFromIsr();
}
else {
/* Transfer completed, invokes the callback.*/
_usb_isr_invoke_in_cb(usbp, ep);
}
}
}
}
usbp->usb->BRDYSTS.WORD = ~brdysts;
}
if (sts0 & INTSTS0_BEMP) {
/* BEMP */
uint16_t bempsts = usbp->usb->BEMPSTS.WORD;
const USBEndpointConfig *epcp;
size_t n;
ep = 0;
epcp = usbp->epc[ep];
epcp->in_state->txcnt += epcp->in_state->transmitted;
epcp->in_state->txsize -= epcp->in_state->transmitted;
if (epcp->in_state->txsize > 0) {
/* Transfer not completed, there are more packets to send.*/
if (epcp->in_state->txsize > epcp->in_maxsize)
n = epcp->in_maxsize;
else
n = epcp->in_state->txsize;
if (epcp->in_state->txqueued) {
usb_packet_write_from_queue(usbp, ep,
epcp->in_state->mode.queue.txqueue, n);
}
else {
epcp->in_state->mode.linear.txbuf += epcp->in_state->transmitted;
usb_packet_write_from_buffer(usbp, ep,
epcp->in_state->mode.linear.txbuf, n);
}
chSysLockFromIsr();
usb_lld_start_in(usbp, ep);
chSysUnlockFromIsr();
}
else {
/* Transfer completed, invokes the callback.*/
_usb_isr_invoke_in_cb(usbp, ep);
}
usbp->usb->BEMPSTS.WORD = ~bempsts;
}
usbp->usb->INTSTS0.WORD = sts0clr;
}
#endif
/**
* @brief USB interrupt handler.
*
* @isr
*/
#if RX62N_USE_USB0 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(Excep_USB0_USBI0) {
CH_IRQ_PROLOGUE();
usb_lld_serve_interrupt(&USBD1);
CH_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level USB driver initialization.
*
* @notapi
*/
void usb_lld_init(void) {
#if RX62N_USE_USB0 || defined(__DOXYGEN__)
usbObjectInit(&USBD1);
USBD1.usb = &USB0;
#endif
#if RX62N_USE_USB1 || defined(__DOXYGEN__)
usbObjectInit(&USBD2);
USBD2.usb = &USB1;
#endif
}
/**
* @brief Configures and activates the USB peripheral.
*
* @param[in] usbp pointer to the @p USBDriver object
*
* @notapi
*/
void usb_lld_start(USBDriver *usbp) {
if (usbp->state == USB_STOP) {
/* Enable USB peripheral. */
if (usbp == &USBD1) {
MSTP(USB0) = 0;
/* Enable GPIO Pull-up */
PORT1.DDR.BIT.B4 = 1;
/* Enable USB0 pins functions */
IOPORT.PFKUSB.BYTE = 0x14;
}
/* USB clock activation. */
usbp->usb->SYSCFG.BIT.SCKE = 1;
/* Select function. */
usbp->usb->SYSCFG.BIT.DCFM = 0;
/* Enable module operation. */
usbp->usb->SYSCFG.BIT.USBE = 1;
/* Default as powered state */
usbp->last_dvst = 0;
/* Default as idle stage */
usbp->last_ctsq = 0;
/* Current FIFO */
usbp->current_fifo = 0;
/* Reset procedure enforced on driver start.*/
_usb_reset(usbp);
}
/* Configuration.*/
}
/**
* @brief Deactivates the USB peripheral.
*
* @param[in] usbp pointer to the @p USBDriver object
*
* @notapi
*/
void usb_lld_stop(USBDriver *usbp) {
/* If in ready state then disables the USB clock.*/
if (usbp->state != USB_STOP) {
/* IEN(USB0,USBI0) = 0;*/
/* Disable module operation. */
usbp->usb->SYSCFG.BIT.USBE = 0;
/* Disable USB clock.*/
usbp->usb->SYSCFG.BIT.SCKE = 0;
/* Disable USB peripheral.*/
if (usbp == &USBD1) {
MSTP(USB0) = 1;
}
}
}
/**
* @brief USB low level reset routine.
*
* @param[in] usbp pointer to the @p USBDriver object
*
* @notapi
*/
void usb_lld_reset(USBDriver *usbp) {
uint16_t ien = 0;
if (usbp == &USBD1) {
IEN(USB0,USBI0) = 0;
}
/* Disable interrupts */
usbp->usb->INTENB0.WORD = 0;
usbp->usb->INTENB1.WORD = 0;
usbp->usb->BRDYENB.WORD = 0;
usbp->usb->NRDYENB.WORD = 0;
usbp->usb->BEMPENB.WORD = 0;
/* Clear interrupt status bits */
usbp->usb->INTSTS0.WORD = (uint16_t)(~(INTSTS0_VALID|INTSTS0_BRDY|
INTSTS0_BEMP|INTSTS0_CTRT|INTSTS0_DVST|INTSTS0_SOFR|INTSTS0_RESM|
INTSTS0_VBINT));
usbp->usb->INTSTS1.WORD = (uint16_t)(~((1<<4)|(1<<5)|(1<<6)|(1<<11)|(1<<12)|
(1<<14)|(1<<15)));
if (usbp->config->sof_cb != NULL) {
ien = INTENB0_SOFE;
}
/* EP0 initialization.*/
usbp->epc[0] = &ep0config;
usbp->usb->DCPCFG.WORD = 0;
usbp->usb->DCPMAXP.WORD = USB_EP0_PACKET_SIZE;
usbp->usb->CFIFOSEL.WORD = 0;
/* Enable the USB interrupts - other interrupts get enabled as the
enumeration process progresses. */
if (usbp == &USBD1) {
IEN(USB0,USBI0) = 1;
IPR(USB0,USBI0) = RX62N_USB0_IRQ_PRIORITY;
}
usbp->usb->INTENB0.WORD =
INTENB0_BRDYE|
INTENB0_BEMPE|
INTENB0_CTRE|
INTENB0_DVSE|
INTENB0_RSME|
ien|
0;
usbp->usb->BRDYENB.BIT.PIPE0BRDYE = 1;
usbp->usb->BEMPENB.BIT.PIPE0BEMPE = 1;
}
/**
* @brief Sets the USB address.
*
* @param[in] usbp pointer to the @p USBDriver object
*
* @notapi
*/
void usb_lld_set_address(USBDriver *usbp) {
(void)usbp;
}
/**
* @brief Finalizes the USB configuration process.
*
* @param[in] usbp pointer to the @p USBDriver object
*
* @notapi
*/
void usb_lld_end_configuration(USBDriver *usbp) {
(void)usbp;
}
/**
* @brief Enables an endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
uint16_t pipecfg;
const USBEndpointConfig *epcp = usbp->epc[ep];
chDbgAssert(ep > 0, "usb_lld_init_endpoint(), #1", "invalid endpoint");
if (ep == 0)
return;
/* usbp->usb->CFIFOSEL.BIT.CURPIPE = 0;*/
usbp->usb->PIPESEL.WORD = ep;
/* Set PID to NAK */
usb_pipectr_write(usbp, ep, 0);
while (usb_pipectr_read(usbp, ep).BIT.PBUSY);
usb_pipectr_write(usbp, ep, PIPECTR_SQCLR|PIPECTR_ACLRM);
usb_pipectr_write(usbp, ep, 0);
/*
if (epcp->out_cb != NULL)
epcp->out_state->currentBank = 0;
*/
/* Setting the endpoint type.*/
switch (epcp->ep_mode & USB_EP_MODE_TYPE) {
case USB_EP_MODE_TYPE_ISOC:
pipecfg = PIPECFG_TYPE_ISO;
break;
case USB_EP_MODE_TYPE_BULK:
pipecfg = PIPECFG_TYPE_BULK;
break;
case USB_EP_MODE_TYPE_INTR:
pipecfg = PIPECFG_TYPE_INT;
break;
default:
/* No control type allowed */
chDbgAssert((epcp->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_CTRL,
"usb_lld_init_endpoint(), #2", "invalid endpoint");
return;
}
/* Set direction */
if (epcp->in_cb != NULL) {
usbp->usb->PIPEMAXP.BIT.MXPS = epcp->in_maxsize;
pipecfg |= PIPECFG_DIR_IN;
}
else {
usbp->usb->PIPEMAXP.BIT.MXPS = epcp->out_maxsize;
pipecfg |= PIPECFG_DIR_OUT;
}
pipecfg |= ep;
usbp->usb->PIPECFG.WORD = pipecfg;
/* Clear interrupt status flag */
usbp->usb->BRDYSTS.WORD &= ~(1<<ep);
/* Enable interrupts */
usbp->usb->BRDYENB.WORD |= (1<<ep);
usbp->usb->PIPESEL.WORD = 0;
}
/**
* @brief Disables all the active endpoints except the endpoint zero.
*
* @param[in] usbp pointer to the @p USBDriver object
*
* @notapi
*/
void usb_lld_disable_endpoints(USBDriver *usbp) {
usbep_t i;
/* Disable endpoints interrupt */
usbp->usb->BRDYENB.WORD = 1;
usbp->usb->BRDYSTS.WORD = ~1;
/* Disable endpoints */
for (i=0; i<USB_MAX_ENDPOINTS; i++) {
usbp->usb->PIPESEL.WORD = i+1;
usbp->usb->PIPECFG.BIT.EPNUM = 0;
}
usbp->usb->PIPESEL.WORD = 0;
/* Clear FIFO */
}
/**
* @brief Returns the status of an OUT endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
* @return The endpoint status.
* @retval EP_STATUS_DISABLED The endpoint is not active.
* @retval EP_STATUS_STALLED The endpoint is stalled.
* @retval EP_STATUS_ACTIVE The endpoint is active.
*
* @notapi
*/
usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
usbep_t epPrev = usbp->usb->PIPESEL.BIT.PIPESEL;
if (ep == 0)
return EP_STATUS_ACTIVE;
usbp->usb->PIPESEL.BIT.PIPESEL = ep;
usbep_t epNum = usbp->usb->PIPECFG.BIT.EPNUM;
usbp->usb->PIPESEL.BIT.PIPESEL = epPrev;
if (epNum) {
if (usb_pipectr_read(usbp, ep).BIT.PID & 2)
return EP_STATUS_STALLED;
}
return EP_STATUS_DISABLED;
}
/**
* @brief Returns the status of an IN endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
* @return The endpoint status.
* @retval EP_STATUS_DISABLED The endpoint is not active.
* @retval EP_STATUS_STALLED The endpoint is stalled.
* @retval EP_STATUS_ACTIVE The endpoint is active.
*
* @notapi
*/
usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
return usb_lld_get_status_out(usbp, ep);
}
/**
* @brief Reads a setup packet from the dedicated packet buffer.
* @details This function must be invoked in the context of the @p setup_cb
* callback in order to read the received setup packet.
* @pre In order to use this function the endpoint must have been
* initialized as a control endpoint.
* @post The endpoint is ready to accept another packet.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
* @param[out] buf buffer where to copy the packet data
*
* @notapi
*/
void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
buf[0] = usbp->usb->USBREQ.WORD & 0xFF;
buf[1] = (usbp->usb->USBREQ.WORD >> 8) & 0xFF;
buf[2] = usbp->usb->USBVAL & 0xFF;
buf[3] = (usbp->usb->USBVAL >> 8) & 0xFF;
buf[4] = usbp->usb->USBINDX & 0xFF;
buf[5] = (usbp->usb->USBINDX >> 8) & 0xFF;
buf[6] = usbp->usb->USBLENG & 0xFF;
buf[7] = (usbp->usb->USBLENG >> 8) & 0xFF;
}
/**
* @brief Prepares for a receive operation.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) {
USBOutEndpointState *osp = usbp->epc[ep]->out_state;
/* Transfer initialization.*/
if (ep == 0) {
do {
usbp->usb->CFIFOSEL.BIT.ISEL = 0;
} while (usbp->usb->CFIFOSEL.BIT.ISEL);
usbp->usb->DCPCTR.BIT.PID = PID_BUF;
while (!usbp->usb->CFIFOCTR.BIT.FRDY);
}
if (osp->rxsize == 0) /* Special case for zero sized packets.*/
osp->rxpkts = 1;
else
osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
usbp->epc[ep]->out_maxsize);
}
/**
* @brief Prepares for a transmit operation.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) {
size_t n;
USBInEndpointState *isp = usbp->epc[ep]->in_state;
/* Transfer initialization.*/
n = isp->txsize;
if (n > (size_t)usbp->epc[ep]->in_maxsize)
n = (size_t)usbp->epc[ep]->in_maxsize;
if (ep == 0) {
do {
usbp->usb->CFIFOSEL.BIT.ISEL = 1;
} while (!usbp->usb->CFIFOSEL.BIT.ISEL);
usbp->usb->DCPCTR.BIT.PID = PID_BUF;
while (!usbp->usb->CFIFOCTR.BIT.FRDY);
if (n == 0)
usbp->usb->CFIFOCTR.BIT.BCLR = 1;
}
else {
usbp->usb->PIPESEL.BIT.PIPESEL = ep;
do {
usbp->usb->D1FIFOSEL.WORD = ep;
} while (usbp->usb->D1FIFOSEL.WORD != ep);
while (!usbp->usb->D1FIFOCTR.BIT.FRDY);
do {
usb_pipectr_write(usbp, ep, PID_BUF);
} while (usb_pipectr_read(usbp, ep).BIT.PID != PID_BUF);
}
if (isp->txqueued) {
usb_packet_write_from_queue(usbp, ep, isp->mode.queue.txqueue, n);
}
else {
usb_packet_write_from_buffer(usbp, ep, isp->mode.linear.txbuf, n);
}
}
/**
* @brief Starts a receive operation on an OUT endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
if (ep)
usb_pipectr_write(usbp, ep, PID_BUF);
}
/**
* @brief Starts a transmit operation on an IN endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
if (ep == 0) {
if (usbp->epc[ep]->in_state->transmitted < usbp->epc[ep]->in_maxsize)
usbp->usb->CFIFOCTR.BIT.BVAL = 1;
}
else {
if (usbp->epc[ep]->in_state->transmitted < usbp->epc[ep]->in_maxsize)
usbp->usb->D1FIFOCTR.BIT.BVAL = 1;
}
}
/**
* @brief Brings an OUT endpoint in the stalled state.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
if (ep == 0) {
if (usbp->usb->DCPCTR.BIT.PID == PID_NAK)
usbp->usb->DCPCTR.BIT.PID = PID_STALL10;
else
usbp->usb->DCPCTR.BIT.PID = PID_STALL11;
}
else {
if ( usb_pipectr_read(usbp, ep).BIT.PID == PID_NAK)
usb_pipectr_write(usbp, ep, PID_STALL10);
else
usb_pipectr_write(usbp, ep, PID_STALL11);
}
}
/**
* @brief Brings an IN endpoint in the stalled state.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
usb_lld_stall_out(usbp, ep);
}
/**
* @brief Brings an OUT endpoint in the active state.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
if (ep == 0) {
if (usbp->usb->DCPCTR.BIT.PID == PID_STALL11)
usbp->usb->DCPCTR.BIT.PID = PID_STALL10;
usbp->usb->DCPCTR.BIT.PID = PID_NAK;
}
else {
if ( usb_pipectr_read(usbp, ep).BIT.PID == PID_STALL11)
usb_pipectr_write(usbp, ep, PID_STALL10);
usb_pipectr_write(usbp, ep, PID_NAK);
}
}
/**
* @brief Brings an IN endpoint in the active state.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
usb_lld_clear_out(usbp, ep);
}
#endif /* HAL_USE_USB */
/** @} */

534
os/hal/platforms/Rx62n/usb_lld.h Normal file
View File

@ -0,0 +1,534 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RX62N/usb_lld.h
* @brief RX62N USB Driver subsystem low level driver header.
*
* @addtogroup USB
* @{
*/
#ifndef _USB_LLD_H_
#define _USB_LLD_H_
#if HAL_USE_USB || defined(__DOXYGEN__)
#include "iodefine_gcc62n.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Maximum endpoint address.
* @details This value does not include the endpoint 0 which is always present.
*/
#define USB_MAX_ENDPOINTS 9
/**
* @brief Maximum endpoint 0 size.
*/
#define USB_EP0_PACKET_SIZE 64 /* other values doesn't work ? */
/**
* @brief Status stage handling method.
*/
#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_HW
/**
* @brief SET_ADDRESS ack handling method.
*/
#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_HW
/**
* @brief This device requires the address change after the status packet.
*/
#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS
/**
* @brief INTSTS0 bit values.
*/
#define INTSTS0_VBINT (1<<15)
#define INTSTS0_RESM (1<<14)
#define INTSTS0_SOFR (1<<13)
#define INTSTS0_DVST (1<<12)
#define INTSTS0_CTRT (1<<11)
#define INTSTS0_BEMP (1<<10)
#define INTSTS0_NRDY (1<<9)
#define INTSTS0_BRDY (1<<8)
#define INTSTS0_VBSTS (1<<7)
#define INTSTS0_VALID (1<<3)
#define INTSTS0_DVSQ(x) ((x>>4)&7)
#define INTSTS0_CTSQ(x) (x&7)
/**
* @brief INTENB0 bit values.
*/
#define INTENB0_VBSE (1<<15)
#define INTENB0_RSME (1<<14)
#define INTENB0_SOFE (1<<13)
#define INTENB0_DVSE (1<<12)
#define INTENB0_CTRE (1<<11)
#define INTENB0_BEMPE (1<<10)
#define INTENB0_NRDYE (1<<9)
#define INTENB0_BRDYE (1<<8)
/**
* @brief PID values.
*/
#define PID_NAK 0
#define PID_BUF 1
#define PID_STALL10 2
#define PID_STALL11 3
#define PID_MASK 3
/**
* @brief CTSQ state values.
*/
#define CTSQ_IDLE_OR_SETUP 0
#define CTSQ_READ_DATA 1
#define CTSQ_READ_STATUS 2
#define CTSQ_WRITE_DATA 3
#define CTSQ_WRITE_STATUS 4
#define CTSQ_NODATA_STATUS 5
#define CTSQ_SEQ_ERROR 6
/**
* @brief DVSQ state values.
*/
#define DVSQ_POWERED 0
#define DVSQ_DEFAULT 1
#define DVSQ_ADDRESS 2
#define DVSQ_CONFIGURED 3
#define DVSQ_SUSPENDED_PWR 4
#define DVSQ_SUSPENDED_DEF 5
#define DVSQ_SUSPENDED_ADR 6
#define DVSQ_SUSPENDED_CFG 7
/**
* @brief PIPECFG bit values.
*/
#define PIPECFG_TYPE_BULK (1<<14)
#define PIPECFG_TYPE_INT (2<<14)
#define PIPECFG_TYPE_ISO (3<<14)
#define PIPECFG_DIR_OUT (0<<4)
#define PIPECFG_DIR_IN (1<<4)
/**
* @brief PIPEnCTR bit values.
*/
#define PIPECTR_SQSET (1<<7)
#define PIPECTR_SQCLR (1<<8)
#define PIPECTR_ACLRM (1<<9)
#define PIPECTR_ATREPM (1<<10)
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of an IN endpoint state structure.
*/
typedef struct {
/**
* @brief Buffer mode, queue or linear.
*/
bool_t txqueued;
/**
* @brief Requested transmit transfer size.
*/
size_t txsize;
/**
* @brief Transmitted bytes so far.
*/
size_t txcnt;
/**
* @brief Transmitted bytes in last transaction (interrupt).
*/
size_t transmitted;
union {
struct {
/**
* @brief Pointer to the transmission linear buffer.
*/
const uint8_t *txbuf;
} linear;
struct {
/**
* @brief Pointer to the output queue.
*/
OutputQueue *txqueue;
} queue;
/* End of the mandatory fields.*/
} mode;
} USBInEndpointState;
/**
* @brief Type of an OUT endpoint state structure.
*/
typedef struct {
/**
* @brief Buffer mode, queue or linear.
*/
bool_t rxqueued;
/**
* @brief Requested receive transfer size.
*/
size_t rxsize;
/**
* @brief Received bytes so far.
*/
size_t rxcnt;
union {
struct {
/**
* @brief Pointer to the receive linear buffer.
*/
uint8_t *rxbuf;
} linear;
struct {
/**
* @brief Pointer to the input queue.
*/
InputQueue *rxqueue;
} queue;
} mode;
/* End of the mandatory fields.*/
/**
* @brief Number of packets to receive.
*/
uint16_t rxpkts;
/**
* @brief Number of bytes last received.
*/
uint16_t rxlast;
} USBOutEndpointState;
/**
* @brief Type of an USB endpoint configuration structure.
* @note Platform specific restrictions may apply to endpoints.
*/
typedef struct {
/**
* @brief Type and mode of the endpoint.
*/
uint32_t ep_mode;
/**
* @brief Setup packet notification callback.
* @details This callback is invoked when a setup packet has been
* received.
* @post The application must immediately call @p usbReadPacket() in
* order to access the received packet.
* @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL
* endpoints, it should be set to @p NULL for other endpoint
* types.
*/
usbepcallback_t setup_cb;
/**
* @brief IN endpoint notification callback.
* @details This field must be set to @p NULL if the IN endpoint is not
* used.
*/
usbepcallback_t in_cb;
/**
* @brief OUT endpoint notification callback.
* @details This field must be set to @p NULL if the OUT endpoint is not
* used.
*/
usbepcallback_t out_cb;
/**
* @brief IN endpoint maximum packet size.
* @details This field must be set to zero if the IN endpoint is not
* used.
*/
uint16_t in_maxsize;
/**
* @brief OUT endpoint maximum packet size.
* @details This field must be set to zero if the OUT endpoint is not
* used.
*/
uint16_t out_maxsize;
/**
* @brief @p USBEndpointState associated to the IN endpoint.
* @details This structure maintains the state of the IN endpoint.
*/
USBInEndpointState *in_state;
/**
* @brief @p USBEndpointState associated to the OUT endpoint.
* @details This structure maintains the state of the OUT endpoint.
*/
USBOutEndpointState *out_state;
/* End of the mandatory fields.*/
/**
* @brief Reserved field, not currently used.
* @note Initialize this field to 1 in order to be forward compatible.
*/
uint16_t ep_buffers;
/**
* @brief Pointer to a buffer for setup packets.
* @details Setup packets require a dedicated 8-bytes buffer, set this
* field to @p NULL for non-control endpoints.
*/
uint8_t *setup_buf;
} USBEndpointConfig;
/**
* @brief Type of an USB driver configuration structure.
*/
typedef struct {
/**
* @brief USB events callback.
* @details This callback is invoked when an USB driver event is registered.
*/
usbeventcb_t event_cb;
/**
* @brief Device GET_DESCRIPTOR request callback.
* @note This callback is mandatory and cannot be set to @p NULL.
*/
usbgetdescriptor_t get_descriptor_cb;
/**
* @brief Requests hook callback.
* @details This hook allows to be notified of standard requests or to
* handle non standard requests.
*/
usbreqhandler_t requests_hook_cb;
/**
* @brief Start Of Frame callback.
*/
usbcallback_t sof_cb;
/* End of the mandatory fields.*/
} USBConfig;
/**
* @brief Structure representing an USB driver.
*/
struct USBDriver {
/**
* @brief Driver state.
*/
usbstate_t state;
/**
* @brief Current configuration data.
*/
const USBConfig *config;
/**
* @brief Field available to user, it can be used to associate an
* application-defined handler to the USB driver.
*/
void *param;
/**
* @brief Bit map of the transmitting IN endpoints.
*/
uint16_t transmitting;
/**
* @brief Bit map of the receiving OUT endpoints.
*/
uint16_t receiving;
/**
* @brief Active endpoints configurations.
*/
const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1];
/**
* @brief Fields available to user, it can be used to associate an
* application-defined handler to an IN endpoint.
* @note The base index is one, the endpoint zero does not have a
* reserved element in this array.
*/
void *in_params[USB_MAX_ENDPOINTS];
/**
* @brief Fields available to user, it can be used to associate an
* application-defined handler to an OUT endpoint.
* @note The base index is one, the endpoint zero does not have a
* reserved element in this array.
*/
void *out_params[USB_MAX_ENDPOINTS];
/**
* @brief Endpoint 0 state.
*/
usbep0state_t ep0state;
/**
* @brief Next position in the buffer to be transferred through endpoint 0.
*/
uint8_t *ep0next;
/**
* @brief Number of bytes yet to be transferred through endpoint 0.
*/
size_t ep0n;
/**
* @brief Endpoint 0 end transaction callback.
*/
usbcallback_t ep0endcb;
/**
* @brief Setup packet buffer.
*/
uint8_t setup[8];
/**
* @brief Current USB device status.
*/
uint16_t status;
/**
* @brief Assigned USB address.
*/
uint8_t address;
/**
* @brief Current USB device configuration.
*/
uint8_t configuration;
#if defined(USB_DRIVER_EXT_FIELDS)
USB_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
/**
* @brief USB hardware registers pointer.
*/
volatile struct st_usb0 *usb;
/**
* @brief Last USB device status.
*/
uint8_t last_dvst;
/**
* @brief Last USB control stage.
*/
uint8_t last_ctsq;
/**
* @brief Current FIFO number (D0 or D1).
*/
uint8_t current_fifo;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Returns the current frame number.
*
* @param[in] usbp pointer to the @p USBDriver object
* @return The current frame number.
*
* @notapi
*/
#define usb_lld_get_frame_number(usbp) ((usbp)->usb->FRMNUM.BIT.FRNM)
/**
* @brief Returns the exact size of a receive transaction.
* @details The received size can be different from the size specified in
* @p usbStartReceiveI() because the last packet could have a size
* different from the expected one.
* @pre The OUT endpoint must have been configured in transaction mode
* in order to use this function.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
* @return Received data size.
*
* @notapi
*/
#define usb_lld_get_transaction_size(usbp, ep) \
((usbp)->epc[ep]->out_state->rxcnt)
/**
* @brief Triggers status stage for control endpoint.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
*
* @notapi
*/
#define usb_lld_end_transaction(usbp, ep) \
((usbp)->usb->DCPCTR.BIT.CCPL=1)
/**
* @brief Returns the exact size of a received packet.
* @pre The OUT endpoint must have been configured in packet mode
* in order to use this function.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
* @return Received data size.
*
* @notapi
*/
#define usb_lld_get_packet_size(usbp, ep) \
((size_t)((usbp)->epc[ep]->out_state->rxlast)
/**
* @brief Connects the USB device.
*
* @api
*/
#define usb_lld_connect_bus(usbp) ((usbp)->usb->SYSCFG.BIT.DPRPU=1)
/**
* @brief Disconnect the USB device.
*
* @api
*/
#define usb_lld_disconnect_bus(usbp) ((usbp)->usb->SYSCFG.BIT.DPRPU=0)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if RX62N_USE_USB0 || defined(__DOXYGEN__)
extern USBDriver USBD1;
#endif
#if RX62N_USE_USB1 || defined(__DOXYGEN__)
extern USBDriver USBD2;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void usb_lld_init(void);
void usb_lld_start(USBDriver *usbp);
void usb_lld_stop(USBDriver *usbp);
void usb_lld_reset(USBDriver *usbp);
void usb_lld_set_address(USBDriver *usbp);
void usb_lld_end_configuration(USBDriver *usbp);
void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
void usb_lld_disable_endpoints(USBDriver *usbp);
usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_USB */
#endif /* _USB_LLD_H_ */
/** @} */

26
os/hal/src/usb.c
View File

@ -627,7 +627,13 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
return;
}
}
#if (USB_SET_ADDRESS_ACK_HANDLING == USB_SET_ADDRESS_ACK_HW)
if (usbp->setup[1] == USB_REQ_SET_ADDRESS)
{
/* Zero-length packet sent by hardware */
return;
}
#endif
/* Transfer preparation. The request handler must have populated
correctly the fields ep0next, ep0n and ep0endcb using the macro
usbSetupTransfer().*/
@ -649,10 +655,14 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
/* No transmission phase, directly receiving the zero sized status
packet.*/
usbp->ep0state = USB_EP0_WAITING_STS;
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
usbPrepareReceive(usbp, 0, NULL, 0);
chSysLockFromIsr();
usbStartReceiveI(usbp, 0);
chSysUnlockFromIsr();
#else
usbSetupEnd(usbp, ep);
#endif
}
}
else {
@ -669,10 +679,14 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
/* No receive phase, directly sending the zero sized status
packet.*/
usbp->ep0state = USB_EP0_SENDING_STS;
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
usbPrepareTransmit(usbp, 0, NULL, 0);
chSysLockFromIsr();
usbStartTransmitI(usbp, 0);
chSysUnlockFromIsr();
#else
usbSetupEnd(usbp, ep);
#endif
}
}
}
@ -709,10 +723,14 @@ void _usb_ep0in(USBDriver *usbp, usbep_t ep) {
case USB_EP0_WAITING_TX0:
/* Transmit phase over, receiving the zero sized status packet.*/
usbp->ep0state = USB_EP0_WAITING_STS;
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
usbPrepareReceive(usbp, 0, NULL, 0);
chSysLockFromIsr();
usbStartReceiveI(usbp, 0);
chSysUnlockFromIsr();
#else
usbSetupEnd(usbp, ep);
#endif
return;
case USB_EP0_SENDING_STS:
/* Status packet sent, invoking the callback if defined.*/
@ -749,16 +767,22 @@ void _usb_ep0out(USBDriver *usbp, usbep_t ep) {
case USB_EP0_RX:
/* Receive phase over, sending the zero sized status packet.*/
usbp->ep0state = USB_EP0_SENDING_STS;
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
usbPrepareTransmit(usbp, 0, NULL, 0);
chSysLockFromIsr();
usbStartTransmitI(usbp, 0);
chSysUnlockFromIsr();
#else
usbSetupEnd(usbp, ep);
#endif
return;
case USB_EP0_WAITING_STS:
/* Status packet received, it must be zero sized, invoking the callback
if defined.*/
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
if (usbGetReceiveTransactionSizeI(usbp, 0) != 0)
break;
#endif
if (usbp->ep0endcb != NULL)
usbp->ep0endcb(usbp);
usbp->ep0state = USB_EP0_WAITING_SETUP;

167
os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld Normal file
View File

@ -0,0 +1,167 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/*
* R5F562N8xxxx memory setup (code executed from RAM)
*/
__user_stack_size__ = 0x0; /* not used */
__irq_stack_size__ = 0x0400;
MEMORY
{
ramjumps : org = 0x00000000, len = 0x20
flash : org = 0x00000020, len = 64k-0x20
ram : org = 0x00010000, len = 32k
fvectors : org = 0xFFFFFF80, len = 0x80
}
__ram_start__ = ORIGIN(ram);
__ram_size__ = LENGTH(ram);
__ram_end__ = __ram_start__ + __ram_size__;
__flash_start__ = ORIGIN(flash);
__flash_size__ = LENGTH(flash);
SECTIONS
{
. = 0;
_text = .;
ramjumps : ALIGN(4)
{
KEEP(*(.ramjumps))
} > ramjumps
rvectors : ALIGN(4)
{
KEEP(*(.rvectors))
} > flash
constructors : ALIGN(4) SUBALIGN(4)
{
PROVIDE(__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__init_array_end = .);
} > flash
destructors : ALIGN(4) SUBALIGN(4)
{
PROVIDE(__fini_array_start = .);
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
PROVIDE(__fini_array_end = .);
} > flash
.text : ALIGN(4)
{
/* KEEP(*(.text.startup.*))*/
*(.text P .stub .text.* .gnu.linkonce.t.*)
*(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
} > flash
/*
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} > flash
.eh_frame : ONLY_IF_RO
{
*(.eh_frame)
} > flash
.textalign : ONLY_IF_RO
{
. = ALIGN(8);
} > flash
*/
. = ALIGN(4);
_etext = .;
_textdata = _etext;
.noinit (NOLOAD) :
{
} > ram
.stacks :
{
. = ALIGN(4);
__user_stack_base__ = .;
. += __user_stack_size__;
. = ALIGN(4);
__user_stack_end__ = .;
__irq_stack_base__ = .;
__main_thread_stack_base__ = .;
. += __irq_stack_size__;
. = ALIGN(4);
__main_thread_stack_end__ = .;
PROVIDE(__irq_stack_end__ = .);
} > ram
.data :
{
. = ALIGN(4);
PROVIDE(_data = .);
*(.data D .data.* .gnu.linkonce.d.*)
. = ALIGN(4);
*(.data1)
. = ALIGN(4);
*(.ramtext)
. = ALIGN(4);
*(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)
. = ALIGN(4);
PROVIDE(_edata = .);
/* } > flash*/
} > ram AT > flash
.bss :
{
. = ALIGN(4);
PROVIDE(_bss_start = .);
*(.sbss .sbss.*)
*(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)
. = ALIGN(4);
*(COMMON)
. = ALIGN(4);
. = ALIGN(32);
*(.etherdesc)
PROVIDE(_bss_end = .);
} > ram
PROVIDE(end = .);
_end = .;
___heap_base__ = _end;
___heap_end__ = __ram_end__;
fvectors : ALIGN(4)
{
KEEP(*(.fvectors))
} > fvectors
}

59
os/ports/GCC/RX/RX62N/rxparams.h Normal file
View File

@ -0,0 +1,59 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file GCC/RX/RX62N/rxparams.h
* @brief Renesas RX parameters for the RX62N.
*
* @defgroup RX_RX62N Specific Parameters
* @ingroup RX_SPECIFIC
* @details This file contains the RX specific parameters for the
* RX62N platform.
* @{
*/
#ifndef _RXPARAMS_H_
#define _RXPARAMS_H_
/**
* @brief RX core model.
*/
#define RX_MODEL RX62N
/**
* @brief Memory Protection unit presence.
*/
#define RX_HAS_MPU TRUE
/**
* @brief Floating Point unit presence.
*/
#define RX_HAS_FPU TRUE
#endif /* _RXPARAMS_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file GCC/RX/RX62N/vectors.c
* @brief Interrupt vectors for the RX family.
*
* @defgroup RX_RX62N_VECTORS RX62N Interrupt Vectors
* @ingroup RX_SPECIFIC
* @details Interrupt vectors for the RX family.
* @{
*/
#include "ch.h"
#include "hal.h"
/**
* @brief Unhandled exceptions handler.
* @details Any undefined exception vector points to this function by default.
* This function simply stops the system into an infinite loop.
*
* @notapi
*/
#if !defined(__DOXYGEN__)
__attribute__ ((naked))
#endif
void _unhandled_exception(void) {
while (1);
}
#if !defined(__DOXYGEN__)
/* hardware vectors */
extern void ResetHandler(void);
void NMIHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void UndefHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void FPUHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void SVHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
/* relocatable vectors */
void Excep_BRK(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_BUSERR(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_FCU_FCUERR(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_FCU_FRDYI(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_ICU_SWINT(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CMTU0_CMT0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CMTU0_CMT1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CMTU1_CMT2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CMTU1_CMT3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_ETHER_EINT(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_USB0_D0FIFO0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_USB0_D1FIFO0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_USB0_USBI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_USB1_D0FIFO1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_USB1_D1FIFO1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_USB1_USBI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RSPI0_SPEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RSPI0_SPRI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RSPI0_SPTI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RSPI0_SPII0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RSPI1_SPEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RSPI1_SPRI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RSPI1_SPTI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RSPI1_SPII1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CAN0_ERS0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CAN0_RXF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CAN0_TXF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CAN0_RXM0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_CAN0_TXM0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RTC_PRD(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RTC_CUP(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ11(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ12(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ13(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ14(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_IRQ15(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_USB_USBR0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_USB_USBR1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RTC_ALM(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_WDT_WOVI(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_AD0_ADI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_AD1_ADI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_S12AD_ADI12(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU0_TGIA0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU0_TGIB0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU0_TGIC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU0_TGID0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU0_TCIV0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU0_TGIE0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU0_TGIF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU1_TGIA1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU1_TGIB1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU1_TCIV1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU1_TCIU1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU2_TGIA2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU2_TGIB2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU2_TCIV2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU2_TCIU2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU3_TGIA3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU3_TGIB3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU3_TGIC3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU3_TGID3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU3_TCIV3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU4_TGIA4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU4_TGIB4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU4_TGIC4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU4_TGID4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU4_TCIV4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU5_TCIU5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU5_TCIV5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU5_TCIW5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU6_TGIA6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU6_TGIB6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU6_TGIC6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU6_TGID6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU6_TCIV6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU6_TGIE6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU6_TGIF6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU7_TGIA7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU7_TGIB7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU7_TCIV7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU7_TCIU7(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU8_TGIA8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU8_TGIB8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU8_TCIV8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU8_TCIU8(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU9_TGIA9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU9_TGIB9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU9_TGIC9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU9_TGID9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU9_TCIV9(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU10_TGIA10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU10_TGIB10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU10_TGIC10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU10_TGID10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU10_TCIV10(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU11_TCIU11(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU11_TCIV11(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_MTU11_TCIW11(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_POE_OEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_POE_OEI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_POE_OEI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_POE_OEI4(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR0_CMI0A(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR0_CMI0B(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR0_OV0I(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR1_CMI1A(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR1_CMI1B(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR1_OV1I(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR2_CMI2A(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR2_CMI2B(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR2_OV2I(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR3_CMI3A(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR3_CMI3B(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_TMR3_OV3I(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_DMACA_DMAC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_DMACA_DMAC1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_DMACA_DMAC2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_DMACA_DMAC3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_EXDMAC_DMAC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_EXDMAC_DMAC1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI0_ERI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI0_RXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI0_TXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI0_TEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI1_ERI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI1_RXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI1_TXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI1_TEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI2_ERI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI2_RXI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI2_TXI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI2_TEI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI3_ERI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI3_RXI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI3_TXI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI3_TEI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI5_ERI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI5_RXI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI5_TXI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI5_TEI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI6_ERI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI6_RXI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI6_TXI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_SCI6_TEI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RIIC0_EEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RIIC0_RXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RIIC0_TXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RIIC0_TEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RIIC1_EEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RIIC1_RXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RIIC1_TXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
void Excep_RIIC1_TEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception")));
#endif
#if defined(RAMRUN)
__attribute__((naked,section(".ramjumps")))
void ramjumps(void)
{
asm volatile ("bra.a _ResetHandler\n\t\
bra.a _NMIHandler\n\t\
bra.a _UndefHandler\n\t\
bra.a _FPUHandler\n\t\
bra.a _SVHandler\n\t");
}
#endif
const unsigned long _hardwareVectors[] __attribute__ ((section (".fvectors"))) = {
/* 0xFFFFFF80 - reserved */
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/* 0xFFFFFFD0 - Supervisor Instruction */
16,
/* 0xFFFFFFD4 - reserved */
0, 0,
/* 0xFFFFFFDC Undefined Instruction */
8,
/* 0xFFFFFFE0 - reserved */
0,
/* 0xFFFFFFE4 - Floating Point */
12,
/* 0xFFFFFFE8 - reserved */
0, 0, 0, 0,
/* 0xFFFFFFF8 - NMI */
4,
/* 0xFFFFFFFC - RESET */
0
};
void (*_relocatableVectors[256])(void) __attribute__ ((section (".rvectors"))) = {
Excep_BRK, // 0
_unhandled_exception, // 1
_unhandled_exception, // 2
_unhandled_exception, // 3
_unhandled_exception, // 4
_unhandled_exception, // 5
_unhandled_exception, // 6
_unhandled_exception, // 7
_unhandled_exception, // 8
_unhandled_exception, // 9
_unhandled_exception, // 10
_unhandled_exception, // 11
_unhandled_exception, // 12
_unhandled_exception, // 13
_unhandled_exception, // 14
_unhandled_exception, // 15
Excep_BUSERR, // 16
_unhandled_exception, // 17
_unhandled_exception, // 18
_unhandled_exception, // 19
_unhandled_exception, // 20
Excep_FCU_FCUERR, // 21
_unhandled_exception, // 22
Excep_FCU_FRDYI, // 23
_unhandled_exception, // 24
_unhandled_exception, // 25
_unhandled_exception, // 26
Excep_ICU_SWINT, // 27
Excep_CMTU0_CMT0, // 28
Excep_CMTU0_CMT1, // 29
Excep_CMTU1_CMT2, // 30
Excep_CMTU1_CMT3, // 31
Excep_ETHER_EINT, // 32
_unhandled_exception, // 33
_unhandled_exception, // 34
_unhandled_exception, // 35
Excep_USB0_D0FIFO0, // 36
Excep_USB0_D1FIFO0, // 37
Excep_USB0_USBI0, // 38
_unhandled_exception, // 39
Excep_USB1_D0FIFO1, // 40
Excep_USB1_D1FIFO1, // 41
Excep_USB1_USBI1, // 42
_unhandled_exception, // 43
Excep_RSPI0_SPEI0, // 44
Excep_RSPI0_SPRI0, // 45
Excep_RSPI0_SPTI0, // 46
Excep_RSPI0_SPII0, // 47
Excep_RSPI1_SPEI1, // 48
Excep_RSPI1_SPRI1, // 49
Excep_RSPI1_SPTI1, // 50
Excep_RSPI1_SPII1, // 51
_unhandled_exception, // 52
_unhandled_exception, // 53
_unhandled_exception, // 54
_unhandled_exception, // 55
Excep_CAN0_ERS0, // 56
Excep_CAN0_RXF0, // 57
Excep_CAN0_TXF0, // 58
Excep_CAN0_RXM0, // 59
Excep_CAN0_TXM0, // 60
_unhandled_exception, // 61
Excep_RTC_PRD, // 62
Excep_RTC_CUP, // 63
Excep_IRQ0, // 64
Excep_IRQ1, // 65
Excep_IRQ2, // 66
Excep_IRQ3, // 67
Excep_IRQ4, // 68
Excep_IRQ5, // 69
Excep_IRQ6, // 70
Excep_IRQ7, // 71
Excep_IRQ8, // 72
Excep_IRQ9, // 73
Excep_IRQ10, // 74
Excep_IRQ11, // 75
Excep_IRQ12, // 76
Excep_IRQ13, // 77
Excep_IRQ14, // 78
Excep_IRQ15, // 79
_unhandled_exception, // 80
_unhandled_exception, // 81
_unhandled_exception, // 82
_unhandled_exception, // 83
_unhandled_exception, // 84
_unhandled_exception, // 85
_unhandled_exception, // 86
_unhandled_exception, // 87
_unhandled_exception, // 88
_unhandled_exception, // 89
Excep_USB_USBR0, // 90
Excep_USB_USBR1, // 91
Excep_RTC_ALM, // 92
_unhandled_exception, // 93
_unhandled_exception, // 94
_unhandled_exception, // 95
Excep_WDT_WOVI, // 96
_unhandled_exception, // 97
Excep_AD0_ADI0, // 98
Excep_AD1_ADI1, // 99
_unhandled_exception, // 100
_unhandled_exception, // 101
Excep_S12AD_ADI12, // 102
_unhandled_exception, // 103
_unhandled_exception, // 104
_unhandled_exception, // 105
_unhandled_exception, // 106
_unhandled_exception, // 107
_unhandled_exception, // 108
_unhandled_exception, // 109
_unhandled_exception, // 110
_unhandled_exception, // 111
_unhandled_exception, // 112
_unhandled_exception, // 113
Excep_MTU0_TGIA0, // 114
Excep_MTU0_TGIB0, // 115
Excep_MTU0_TGIC0, // 116
Excep_MTU0_TGID0, // 117
Excep_MTU0_TCIV0, // 118
Excep_MTU0_TGIE0, // 119
Excep_MTU0_TGIF0, // 120
Excep_MTU1_TGIA1, // 121
Excep_MTU1_TGIB1, // 122
Excep_MTU1_TCIV1, // 123
Excep_MTU1_TCIU1, // 124
Excep_MTU2_TGIA2, // 125
Excep_MTU2_TGIB2, // 126
Excep_MTU2_TCIV2, // 127
Excep_MTU2_TCIU2, // 128
Excep_MTU3_TGIA3, // 129
Excep_MTU3_TGIB3, // 130
Excep_MTU3_TGIC3, // 131
Excep_MTU3_TGID3, // 132
Excep_MTU3_TCIV3, // 133
Excep_MTU4_TGIA4, // 134
Excep_MTU4_TGIB4, // 135
Excep_MTU4_TGIC4, // 136
Excep_MTU4_TGID4, // 137
Excep_MTU4_TCIV4, // 138
Excep_MTU5_TCIU5, // 139
Excep_MTU5_TCIV5, // 140
Excep_MTU5_TCIW5, // 141
Excep_MTU6_TGIA6, // 142
Excep_MTU6_TGIB6, // 143
Excep_MTU6_TGIC6, // 144
Excep_MTU6_TGID6, // 145
Excep_MTU6_TCIV6, // 146
Excep_MTU6_TGIE6, // 147
Excep_MTU6_TGIF6, // 148
Excep_MTU7_TGIA7, // 149
Excep_MTU7_TGIB7, // 150
Excep_MTU7_TCIV7, // 151
Excep_MTU7_TCIU7, // 152
Excep_MTU8_TGIA8, // 153
Excep_MTU8_TGIB8, // 154
Excep_MTU8_TCIV8, // 155
Excep_MTU8_TCIU8, // 156
Excep_MTU9_TGIA9, // 157
Excep_MTU9_TGIB9, // 158
Excep_MTU9_TGIC9, // 159
Excep_MTU9_TGID9, // 160
Excep_MTU9_TCIV9, // 161
Excep_MTU10_TGIA10, // 162
Excep_MTU10_TGIB10, // 163
Excep_MTU10_TGIC10, // 164
Excep_MTU10_TGID10, // 165
Excep_MTU10_TCIV10, // 166
Excep_MTU11_TCIU11, // 167
Excep_MTU11_TCIV11, // 168
Excep_MTU11_TCIW11, // 169
Excep_POE_OEI1, // 170
Excep_POE_OEI2, // 171
Excep_POE_OEI3, // 172
Excep_POE_OEI4, // 173
Excep_TMR0_CMI0A, // 174
Excep_TMR0_CMI0B, // 175
Excep_TMR0_OV0I, // 176
Excep_TMR1_CMI1A, // 177
Excep_TMR1_CMI1B, // 178
Excep_TMR1_OV1I, // 179
Excep_TMR2_CMI2A, // 180
Excep_TMR2_CMI2B, // 181
Excep_TMR2_OV2I, // 182
Excep_TMR3_CMI3A, // 183
Excep_TMR3_CMI3B, // 184
Excep_TMR3_OV3I, // 185
_unhandled_exception, // 186
_unhandled_exception, // 187
_unhandled_exception, // 188
_unhandled_exception, // 189
_unhandled_exception, // 190
_unhandled_exception, // 191
_unhandled_exception, // 192
_unhandled_exception, // 193
_unhandled_exception, // 194
_unhandled_exception, // 195
_unhandled_exception, // 196
_unhandled_exception, // 197
Excep_DMACA_DMAC0, // 198
Excep_DMACA_DMAC1, // 199
Excep_DMACA_DMAC2, // 200
Excep_DMACA_DMAC3, // 201
Excep_EXDMAC_DMAC0, // 202
Excep_EXDMAC_DMAC1, // 203
_unhandled_exception, // 204
_unhandled_exception, // 205
_unhandled_exception, // 206
_unhandled_exception, // 207
_unhandled_exception, // 208
_unhandled_exception, // 209
_unhandled_exception, // 210
_unhandled_exception, // 211
_unhandled_exception, // 212
_unhandled_exception, // 213
Excep_SCI0_ERI0, // 214
Excep_SCI0_RXI0, // 215
Excep_SCI0_TXI0, // 216
Excep_SCI0_TEI0, // 217
Excep_SCI1_ERI1, // 218
Excep_SCI1_RXI1, // 219
Excep_SCI1_TXI1, // 220
Excep_SCI1_TEI1, // 221
Excep_SCI2_ERI2, // 222
Excep_SCI2_RXI2, // 223
Excep_SCI2_TXI2, // 224
Excep_SCI2_TEI2, // 225
Excep_SCI3_ERI3, // 226
Excep_SCI3_RXI3, // 227
Excep_SCI3_TXI3, // 228
Excep_SCI3_TEI3, // 229
_unhandled_exception, // 230
_unhandled_exception, // 231
_unhandled_exception, // 232
_unhandled_exception, // 233
Excep_SCI5_ERI5, // 234
Excep_SCI5_RXI5, // 235
Excep_SCI5_TXI5, // 236
Excep_SCI5_TEI5, // 237
Excep_SCI6_ERI6, // 238
Excep_SCI6_RXI6, // 239
Excep_SCI6_TXI6, // 240
Excep_SCI6_TEI6, // 241
_unhandled_exception, // 242
_unhandled_exception, // 243
_unhandled_exception, // 244
_unhandled_exception, // 245
Excep_RIIC0_EEI0, // 246
Excep_RIIC0_RXI0, // 247
Excep_RIIC0_TXI0, // 248
Excep_RIIC0_TEI0, // 249
Excep_RIIC1_EEI1, // 250
Excep_RIIC1_RXI1, // 251
Excep_RIIC1_TXI1, // 252
Excep_RIIC1_TEI1, // 253
_unhandled_exception, // 254
_unhandled_exception, // 255
};
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file GCC/RX/chcore.c
* @brief Renesas RX architecture port code.
*
* @addtogroup RX_CORE
* @{
*/
#include "ch.h"
/**
* @brief RX initialization code.
*
* @note This function is usually empty.
*/
void port_init(void){
}
/**
* @brief Disables all the interrupt sources.
*
* @note Of course non maskable interrupt sources are not included.
*/
void port_disable() {
asm volatile ("clrpsw I \n\t");
}
/**
* @brief Disables the interrupt sources that are not supposed to preempt the kernel.
*/
void port_suspend(void) {
asm volatile ("clrpsw I \n\t");
}
/**
* @brief Enables all the interrupt sources.
*/
void port_enable(void) {
asm volatile ("setpsw I \n\t");
}
/**
* @brief Check if interrupts are enabled.
*/
bool_t port_enabled(void) {
uint32_t psw;
asm volatile("mvfc PSW,%0 \n\t"
: "=r" (psw) : : );
return psw & (1<<16) ? true : false;
}
/**
* @brief Halts the system.
* @details This function is invoked by the operating system when an
* unrecoverable error is detected (for example because a programming
* error in the application code that triggers an assertion while in
* debug mode).
* @note The function is declared as a weak symbol, it is possible to
* redefine it in your application code.
*/
#if !defined(__DOXYGEN__)
__attribute__((weak))
#endif
void port_halt(void) {
port_disable();
while (TRUE) {
}
}
/**
* @brief Performs a context switch between two threads.
* @details This is the most critical code in any port, this function
* is responsible for the context switch between 2 threads.
*
* @param ntp the thread to be switched in
* @param otp the thread to be switched out
* @note The implementation of this code affects <b>directly</b> the context
* switch performance so optimize here as much as you can.
*/
#if !defined(__DOXYGEN__)
__attribute__((naked, weak))
#endif
void port_switch(Thread *ntp, Thread *otp) {
/*
register struct intctx *sp asm ("sp");
asm volatile ("pushm r6-r13 \n\t");
otp->p_ctx.sp = sp;
sp = ntp->p_ctx.sp;
asm volatile ("popm r6-r13 \n\t");
*/
#if !defined(CH_CURRP_REGISTER_CACHE)
asm volatile ("pushm r6-r13 \n\t"
"mov.l r0,12[r2] \n\t"
"mov.l 12[r1],r0 \n\t"
"popm r6-r13 \n\t");
#else
asm volatile ("pushm r6-r12 \n\t"
"mov r0,12[r2] \n\t"
"mov 12[r1],r0 \n\t"
"popm r6-r12 \n\t");
#endif
asm volatile ("rts \n\t");
}
/**
* @brief Start a thread by invoking its work function.
* @details If the work function returns @p chThdExit() is automatically
* invoked.
*/
void _port_thread_start(void) {
chSysUnlock();
asm volatile ("mov.l r11,r1 \n\t"
"jsr r12 \n\t"
"bsr _chThdExit \n\t");
}
/** @} */

356
os/ports/GCC/RX/chcore.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file RX/chcore.h
* @brief Renesas RX port macros and structures.
*
* @addtogroup RX_CORE
* @{
*/
#ifndef _CHCORE_H_
#define _CHCORE_H_
/*===========================================================================*/
/* Port constants. */
/*===========================================================================*/
/* Inclusion of the RX implementation specific parameters.*/
#include "rxparams.h"
/* RX model check, only RX62N is supported right now.*/
#if (RX_MODEL == RX62N)
#else
#error "unknown or unsupported RX model"
#endif
/*===========================================================================*/
/* Port statically derived parameters. */
/*===========================================================================*/
/*===========================================================================*/
/* Port macros. */
/*===========================================================================*/
/*===========================================================================*/
/* Port configurable parameters. */
/*===========================================================================*/
/**
* If enabled allows the idle thread to enter a low power mode.
*/
#ifndef RX_ENABLE_WFI_IDLE
#define RX_ENABLE_WFI_IDLE FALSE
#endif
/*===========================================================================*/
/* Port exported info. */
/*===========================================================================*/
/**
* Macro defining a generic RX architecture.
*/
#define CH_ARCHITECTURE_RX
/**
* @brief Name of the implemented architecture.
* @note The value is for documentation only, the real value changes
* depending on the selected architecture, the possible values are:
* - "ARM7".
* - "ARM9".
* .
*/
#define CH_ARCHITECTURE_NAME "RX"
/**
* @brief Name of the compiler supported by this port.
*/
#define CH_COMPILER_NAME "GCC " __VERSION__
/*===========================================================================*/
/* Port implementation part (common). */
/*===========================================================================*/
/**
* @brief 32 bits stack and memory alignment enforcement.
*/
typedef uint32_t stkalign_t;
/**
* @brief Generic RX register.
*/
typedef void *regrx_t;
/**
* @brief Interrupt saved context.
* @details This structure represents the stack frame saved during a
* preemption-capable interrupt handler. These registers are caller-saved in GCC.
*/
struct extctx {
#if defined(RX_USE_FPU)
regrx_t fpsw;
#endif
regrx_t acc_hi;
regrx_t acc_lo;
regrx_t r1;
regrx_t r2;
regrx_t r3;
regrx_t r4;
regrx_t r5;
regrx_t r14;
regrx_t r15;
regrx_t psw;
regrx_t pc;
};
/**
* @brief System saved context.
* @details This structure represents the inner stack frame during a context
* switching. These registers are callee-saved in GCC.
*/
struct intctx {
regrx_t r6;
regrx_t r7;
regrx_t r8;
regrx_t r9;
regrx_t r10;
regrx_t r11;
regrx_t r12;
#ifndef CH_CURRP_REGISTER_CACHE
/* -mint-register=1 - reserves R13 */
regrx_t r13;
#else
#warning CH_CURRP_REGISTER_CACHE feature is not tested.
#endif
regrx_t pc;
};
/**
* @brief Platform dependent part of the @p Thread structure.
* @details In this port the structure just holds a pointer to the @p intctx
* structure representing the stack pointer at context switch time.
*/
struct context {
struct intctx *sp;
};
/**
* @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
* by an @p intctx structure.
*/
#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace + \
wsize - sizeof(struct intctx)); \
tp->p_ctx.sp->r11 = arg; \
tp->p_ctx.sp->r12 = pf; \
tp->p_ctx.sp->pc = _port_thread_start; \
}
/**
* @brief Stack size for the system idle thread.
* @details This size depends on the idle thread implementation, usually
* the idle thread should take no more space than those reserved
* by @p PORT_INT_REQUIRED_STACK.
*/
#ifndef PORT_IDLE_THREAD_STACK_SIZE
#define PORT_IDLE_THREAD_STACK_SIZE 20
#endif
/**
* @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
* This value can be zero on those architecture where there is a
* separate interrupt stack and the stack space between @p intctx and
* @p extctx is known to be zero.
*/
#ifndef PORT_INT_REQUIRED_STACK
/*#define PORT_INT_REQUIRED_STACK 64*/
#define PORT_INT_REQUIRED_STACK 256
#endif
/**
* @brief Enforces a correct alignment for a stack area size value.
*/
#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
/**
* @brief Computes the thread working area global size.
*/
#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
sizeof(struct intctx) + \
sizeof(struct extctx) + \
(n) + (PORT_INT_REQUIRED_STACK))
/**
* @brief Static working area allocation.
* @details This macro is used to allocate a static thread working area
* aligned as both position and size.
*/
#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
#if !defined(RX_USE_FPU)
#define PORT_IRQ_PROLOGUE() { \
asm volatile ("pushm r14-r15 \n\t" \
"pushm r1-r5 \n\t" \
"mvfaclo r1 \n\t" \
"push r1 \n\t" \
"mvfachi r1 \n\t" \
"push r1 \n\t"); \
}
#else
#define PORT_IRQ_PROLOGUE() { \
asm volatile ("pushm r14-r15 \n\t" \
"pushm r1-r5 \n\t" \
"mvfaclo r1 \n\t" \
"push r1 \n\t" \
"mvfachi r1 \n\t" \
"push r1 \n\t" \
"pushc FPSW \n\t"); \
}
#endif
/* #define PORT_IRQ_PROLOGUE() */
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
#if !defined(RX_USE_FPU)
#define PORT_IRQ_EPILOGUE() { \
dbg_check_lock(); \
if (chSchIsPreemptionRequired()) { \
asm volatile ("mvtipl #0 \n\t"); \
chSchDoReschedule(); \
} \
dbg_check_unlock(); \
asm volatile ("pop r1 \n\t" \
"mvtachi r1 \n\t" \
"pop r1 \n\t" \
"mvtaclo r1 \n\t" \
"popm r1-r5 \n\t" \
"popm r14-r15 \n\t" \
"rte \n\t"); \
}
#else
#define PORT_IRQ_EPILOGUE() { \
dbg_check_lock(); \
if (chSchIsPreemptionRequired()) { \
asm volatile ("mvtipl #0 \n\t"); \
chSchDoReschedule(); \
} \
asm volatile ("popc FPSW \n\t" \
"pop r1 \n\t" \
"mvtachi r1 \n\t" \
"pop r1 \n\t" \
"mvtaclo r1 \n\t" \
"popm r1-r5 \n\t" \
"popm r14-r15 \n\t" \
"rte \n\t"); \
}
#endif
/**
* IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#define PORT_IRQ_HANDLER(id) void __attribute__((naked)) id(void)
/**
* @brief Kernel-unlock action.
* @details Usually this function just disables interrupts but may perform more
* actions.
*/
#define port_lock() asm volatile ("clrpsw I \n\t")
/**
* @brief Kernel-unlock action.
* @details Usually this function just disables interrupts but may perform more
* actions.
*/
#define port_unlock() asm volatile ("setpsw I \n\t")
/**
* @brief Kernel-lock action from an interrupt handler.
* @details This function is invoked before invoking I-class APIs from
* interrupt handlers. The implementation is architecture dependent, in its
* simplest form it is void.
*/
#define port_lock_from_isr()
/**
* @brief Kernel-unlock action from an interrupt handler.
* @details This function is invoked after invoking I-class APIs from interrupt
* handlers. The implementation is architecture dependent, in its simplest form
* it is void.
*/
#define port_unlock_from_isr()
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
* @details The function is meant to return when an interrupt becomes pending.
* The simplest implementation is an empty function or macro but this
* would not take advantage of architecture-specific power saving
* modes.
* @note This port function is implemented as inlined code for performance
* reasons.
*/
#if RX_ENABLE_WFI_IDLE == TRUE
#define port_wait_for_interrupt() { \
asm volatile ("wait"); \
}
#else
#define port_wait_for_interrupt()
#endif
#ifdef __cplusplus
extern "C" {
#endif
void port_init(void);
void port_disable(void);
void port_suspend(void);
void port_enable(void);
bool_t port_enabled(void);
void port_halt(void);
void port_switch(Thread *ntp, Thread *otp);
void _port_thread_start(void);
#ifdef __cplusplus
}
#endif
#endif /* _CHCORE_H_ */
/** @} */

87
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file RX/chtypes.h
* @brief RX architecture port system types.
*
* @addtogroup RX_CORE
* @{
*/
#ifndef _CHTYPES_H_
#define _CHTYPES_H_
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
typedef bool bool_t; /**< Fast boolean type. */
typedef uint8_t tmode_t; /**< Thread flags. */
typedef uint8_t tstate_t; /**< Thread state. */
typedef uint8_t trefs_t; /**< Thread references counter. */
typedef uint8_t tslices_t; /**< Thread time slices counter. */
typedef uint32_t tprio_t; /**< Thread priority. */
typedef int32_t msg_t; /**< Inter-thread message. */
typedef int32_t eventid_t; /**< Event Id. */
typedef uint32_t eventmask_t; /**< Event mask. */
typedef uint32_t flagsmask_t; /**< Event flags. */
typedef uint32_t systime_t; /**< System time. */
typedef int32_t cnt_t; /**< Resources counter. */
/**
* @brief Inline function modifier.
*/
#define INLINE inline
/**
* @brief ROM constant modifier.
* @note It is set to use the "const" keyword in this port.
*/
#define ROMCONST const
/**
* @brief Packed structure modifier (within).
* @note It uses the "packed" GCC attribute.
*/
#define PACK_STRUCT_STRUCT __attribute__((packed))
/**
* @brief Packed structure modifier (before).
* @note Empty in this port.
*/
#define PACK_STRUCT_BEGIN
/**
* @brief Packed structure modifier (after).
* @note Empty in this port.
*/
#define PACK_STRUCT_END
#endif /* _CHTYPES_H_ */
/** @} */

302
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file RX/crt0.c
* @brief Generic RX600 startup file for ChibiOS/RT.
*
* @addtogroup RX_STARTUP
* @{
*/
#include "ch.h"
typedef void (*funcp_t)(void);
typedef funcp_t * funcpp_t;
extern void (*_relocatableVectors[256])(void) __attribute__ ((section (".rvectors")));
extern void __early_init(void);
#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
/*===========================================================================*/
/**
* @name Startup settings
* @{
*/
/*===========================================================================*/
/**
* @brief Stack segments initialization switch.
*/
#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
#define CRT0_STACKS_FILL_PATTERN 0x55555555
#endif
/**
* @brief Stack segments initialization switch.
*/
#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
#define CRT0_INIT_STACKS TRUE
#endif
/**
* @brief DATA segment initialization switch.
*/
#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
#define CRT0_INIT_DATA TRUE
#endif
/**
* @brief BSS segment initialization switch.
*/
#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
#define CRT0_INIT_BSS TRUE
#endif
/**
* @brief Constructors invocation switch.
*/
#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
#define CRT0_CALL_CONSTRUCTORS FALSE
#endif
/**
* @brief Destructors invocation switch.
*/
#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
#define CRT0_CALL_DESTRUCTORS FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Symbols from the scatter file
*/
/*===========================================================================*/
/**
* @brief Main stack lower boundary.
* @details This symbol must be exported by the linker script and represents
* the main stack lower boundary.
*/
extern uint32_t __user_stack_base__;
/**
*
* @brief Main stack initial position.
* @details This symbol must be exported by the linker script and represents
* the main stack initial position.
*/
extern uint32_t __user_stack_end__;
/**
* @brief Process stack lower boundary.
* @details This symbol must be exported by the linker script and represents
* the process stack lower boundary.
*/
extern uint32_t __irq_stack_base__;
/**
* @brief Process stack initial position.
* @details This symbol must be exported by the linker script and represents
* the process stack initial position.
*/
extern uint32_t __irq_stack_end__;
/**
* @brief ROM image of the data segment start.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern uint32_t _textdata;
/**
* @brief Data segment start.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern uint32_t _data;
/**
* @brief Data segment end.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern uint32_t _edata;
/**
* @brief BSS segment start.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern uint32_t _bss_start;
/**
* @brief BSS segment end.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern uint32_t _bss_end;
/**
* @brief Constructors table start.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern funcp_t __init_array_start;
/**
* @brief Constructors table end.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern funcp_t __init_array_end;
/**
* @brief Destructors table start.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern funcp_t __fini_array_start;
/**
* @brief Destructors table end.
* @pre The symbol must be aligned to a 32 bits boundary.
*/
extern funcp_t __fini_array_end;
/** @} */
/**
* @brief Application @p main() function.
*/
extern void main(void);
/**
* @brief Early initialization.
* @details This hook is invoked immediately after the stack initialization
* and before the DATA and BSS segments initialization. The
* default behavior is to do nothing.
* @note This function is a weak symbol.
*/
#if !defined(__DOXYGEN__)
__attribute__((weak))
#endif
void __early_init(void) {}
/**
* @brief Late initialization.
* @details This hook is invoked after the DATA and BSS segments
* initialization and before any static constructor. The
* default behavior is to do nothing.
* @note This function is a weak symbol.
*/
#if !defined(__DOXYGEN__)
__attribute__((weak))
#endif
void __late_init(void) {}
/**
* @brief Default @p main() function exit handler.
* @details This handler is invoked or the @p main() function exit. The
* default behavior is to enter an infinite loop.
* @note This function is a weak symbol.
*/
#if !defined(__DOXYGEN__)
__attribute__((weak, naked))
#endif
void _default_exit(void) {
while (1)
;
}
/**
* @brief Reset vector.
*/
#if !defined(__DOXYGEN__)
__attribute__((naked))
#endif
void ResetHandler(void) {
/* Disable interrupts, ipl=0, supervisor mode, select USP stack */
asm volatile ("mvtc #0x00000000, PSW");
/* Set interrupt stack pointer */
asm volatile ("mvtc #__irq_stack_end__, ISP");
/* Set relocatable vectors base */
asm volatile ("mvtc #__relocatableVectors, INTB");
__early_init();
#if RX_USE_FPU
asm volatile ("mvtc #0x100, FPSW");
#endif
#if defined(CRT0_INIT_STACKS)
/* Stack initialization.*/
asm volatile ("mov %0, R2" : : "i" (CRT0_STACKS_FILL_PATTERN));
asm volatile ("mov #__irq_stack_base__, R1");
asm volatile ("mov #__irq_stack_end__-__irq_stack_base__, R3");
asm volatile ("sstr.b");
#endif
/* copy initialized data */
#if defined(CRT0_INIT_DATA)
asm volatile ("mov #_data, R1");
asm volatile ("mov #_textdata, R2");
asm volatile ("mov #_edata-_data, R3");
asm volatile ("smovf");
#endif
#if defined(CRT0_INIT_BSS)
/* clear bss section */
asm volatile ("mov #0, R2");
asm volatile ("mov #_bss_start, R1");
asm volatile ("mov #_bss_end-_bss_start, R3");
asm volatile ("sstr.b");
#endif
#if CRT0_CALL_CONSTRUCTORS
/* Constructors invocation.*/
{
funcpp_t fpp = &__init_array_start;
while (fpp < &__init_array_end) {
(*fpp)();
fpp++;
}
}
#endif
/* Enable interrupts */
asm volatile ("setpsw I");
/* Invoking application main() function.*/
main();
#if CRT0_CALL_DESTRUCTORS
/* Destructors invocation.*/
{
funcpp_t fpp = &__fini_array_start;
while (fpp < &__fini_array_end) {
(*fpp)();
fpp++;
}
}
#endif
/* Invoking the exit handler.*/
_default_exit();
}
/** @} */