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ChibiOS
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Mass update. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14404 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-20 12:38:36 +00:00
parent 202a3421aa
commit 5837785e87
13 changed files with 13 additions and 0 deletions
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1
demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/SDMMC/cfg/stm32l4r9ai_discovery/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_BOOST TRUE
#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
#define STM32_PWR_CR3 (PWR_CR3_EIWF)
#define STM32_PWR_CR4 (0U)

1
tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
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@ -56,6 +56,7 @@
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
#define STM32_CLOCK_DYNAMIC ${doc.STM32_CLOCK_DYNAMIC!"FALSE"}
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
#define STM32_PWR_BOOST ${doc.STM32_PWR_BOOST!"TRUE"}
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)"}
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}