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Fixed Bug #744 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_16.1.x@9517 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-05-24 19:34:52 +00:00
parent fe8c9f5277
commit 58dc7080ed
2 changed files with 14 additions and 7 deletions
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20
os/hal/ports/STM32/STM32F4xx/hal_lld.h
View File

@ -371,13 +371,6 @@
#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
@ -406,6 +399,19 @@
#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
/** @} */
/**
* @name RCC_PLLSAICFGR register bits definitions
* @{
*/
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
/** @} */
/**
* @name RCC_BDCR register bits definitions
* @{

1
readme.txt
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@ -73,6 +73,7 @@
*****************************************************************************
*** 16.1.5 ***
- HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744).
- HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).
- HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742).
- HAL: Fixed Doxygen related macros in STM32F7xx, STM32L0xx and STM32L4xx