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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13249 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2020-01-08 11:05:27 +00:00
parent a94748555c
commit 59da0d7e33
17 changed files with 2035 additions and 13 deletions
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2
os/hal/ports/STM32/STM32F0xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32F0xx/stm32_isr.h
* @file STM32F0xx/stm32_isr.c
* @brief STM32F0xx ISR handler code.
*
* @addtogroup STM32F0xx_ISR

2
os/hal/ports/STM32/STM32F1xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32F1xx/stm32_isr.h
* @file STM32F1xx/stm32_isr.c
* @brief STM32F1xx ISR handler code.
*
* @addtogroup STM32F1xx_ISR

2
os/hal/ports/STM32/STM32F37x/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32F3xx/stm32_isr.h
* @file STM32F3xx/stm32_isr.c
* @brief STM32F3xx ISR handler code.
*
* @addtogroup STM32F3xx_ISR

2
os/hal/ports/STM32/STM32F3xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32F3xx/stm32_isr.h
* @file STM32F3xx/stm32_isr.c
* @brief STM32F3xx ISR handler code.
*
* @addtogroup STM32F3xx_ISR

2
os/hal/ports/STM32/STM32F4xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32F4xx/stm32_isr.h
* @file STM32F4xx/stm32_isr.c
* @brief STM32F4xx ISR handler code.
*
* @addtogroup STM32F4xx_ISR

2
os/hal/ports/STM32/STM32F7xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32F7xx/stm32_isr.h
* @file STM32F7xx/stm32_isr.c
* @brief STM32F7xx ISR handler code.
*
* @addtogroup STM32F7xx_ISR

2
os/hal/ports/STM32/STM32G0xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32G0xx/stm32_isr.h
* @file STM32G0xx/stm32_isr.c
* @brief STM32G0xx ISR handler code.
*
* @addtogroup STM32G0xx_ISR

2
os/hal/ports/STM32/STM32G4xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32G4xx/stm32_isr.h
* @file STM32G4xx/stm32_isr.c
* @brief STM32G4xx ISR handler code.
*
* @addtogroup STM32G4xx_ISR

2
os/hal/ports/STM32/STM32H7xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32H7xx/stm32_isr.h
* @file STM32H7xx/stm32_isr.c
* @brief STM32H7xx ISR handler code.
*
* @addtogroup STM32H7xx_ISR

2
os/hal/ports/STM32/STM32L0xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32L0xx/stm32_isr.h
* @file STM32L0xx/stm32_isr.c
* @brief STM32L0xx ISR handler code.
*
* @addtogroup SRM32L0xx_ISR

2
os/hal/ports/STM32/STM32L1xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32L1xx/stm32_isr.h
* @file STM32L1xx/stm32_isr.c
* @brief STM32L1xx ISR handler code.
*
* @addtogroup STM32L1xx_ISR

2
os/hal/ports/STM32/STM32L4xx+/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32L4xx+/stm32_isr.h
* @file STM32L4xx+/stm32_isr.c
* @brief STM32L4xx+ ISR handler code.
*
* @addtogroup STM32L4xxp_ISR

2
os/hal/ports/STM32/STM32L4xx/stm32_isr.c
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@ -15,7 +15,7 @@
*/
/**
* @file STM32L4xx/stm32_isr.h
* @file STM32L4xx/stm32_isr.c
* @brief STM32L4xx ISR handler code.
*
* @addtogroup STM32L4xx_ISR

192
os/hal/ports/STM32/STM32L5xx/stm32_isr.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32L5xx/stm32_isr.c
* @brief STM32L5xx ISR handler code.
*
* @addtogroup STM32L5xx_ISR
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#define exti_serve_irq(pr, channel) { \
\
if ((pr) & (1U << (channel))) { \
_pal_isr_code(channel); \
} \
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#include "stm32_exti0.inc"
#include "stm32_exti1.inc"
#include "stm32_exti2.inc"
#include "stm32_exti3.inc"
#include "stm32_exti4.inc"
#include "stm32_exti5.inc"
#include "stm32_exti6.inc"
#include "stm32_exti7.inc"
#include "stm32_exti8.inc"
#include "stm32_exti9.inc"
#include "stm32_exti10.inc"
#include "stm32_exti11.inc"
#include "stm32_exti12.inc"
#include "stm32_exti13.inc"
#include "stm32_exti14.inc"
#include "stm32_exti15.inc"
#include "stm32_exti16-35_38.inc"
#include "stm32_exti17.inc"
#include "stm32_exti18.inc"
#include "stm32_exti19.inc"
#include "stm32_exti20.inc"
#include "stm32_exti21_22.inc"
#include "stm32_usart1.inc"
#include "stm32_usart2.inc"
#include "stm32_usart3.inc"
#include "stm32_uart4.inc"
#include "stm32_uart5.inc"
#include "stm32_lpuart1.inc"
#include "stm32_tim1.inc"
#include "stm32_tim2.inc"
#include "stm32_tim3.inc"
#include "stm32_tim4.inc"
#include "stm32_tim5.inc"
#include "stm32_tim6.inc"
#include "stm32_tim7.inc"
#include "stm32_tim8.inc"
#include "stm32_tim15.inc"
#include "stm32_tim16.inc"
#include "stm32_tim17.inc"
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables IRQ sources.
*
* @notapi
*/
void irqInit(void) {
exti0_irq_init();
exti1_irq_init();
exti2_irq_init();
exti3_irq_init();
exti4_irq_init();
exti5_irq_init();
exti6_irq_init();
exti7_irq_init();
exti8_irq_init();
exti9_irq_init();
exti10_irq_init();
exti11_irq_init();
exti12_irq_init();
exti13_irq_init();
exti14_irq_init();
exti15_irq_init();
exti16_exti35_38_irq_init();
exti17_irq_init();
exti18_irq_init();
exti19_irq_init();
exti21_22_irq_init();
tim1_tim15_tim16_tim17_irq_init();
tim2_irq_init();
tim3_irq_init();
tim4_irq_init();
tim5_irq_init();
tim6_irq_init();
tim7_irq_init();
tim8_irq_init();
usart1_irq_init();
usart2_irq_init();
usart3_irq_init();
uart4_irq_init();
uart5_irq_init();
lpuart1_irq_init();
}
/**
* @brief Disables IRQ sources.
*
* @notapi
*/
void irqDeinit(void) {
exti0_irq_deinit();
exti1_irq_deinit();
exti2_irq_deinit();
exti3_irq_deinit();
exti4_irq_deinit();
exti5_irq_deinit();
exti6_irq_deinit();
exti7_irq_deinit();
exti8_irq_deinit();
exti9_irq_deinit();
exti10_irq_deinit();
exti11_irq_deinit();
exti12_irq_deinit();
exti13_irq_deinit();
exti14_irq_deinit();
exti15_irq_deinit();
exti16_exti35_38_irq_deinit();
exti17_irq_deinit();
exti18_irq_deinit();
exti19_irq_deinit();
exti21_22_irq_deinit();
tim1_tim15_tim16_tim17_irq_deinit();
tim2_irq_deinit();
tim3_irq_deinit();
tim4_irq_deinit();
tim5_irq_deinit();
tim6_irq_deinit();
tim7_irq_deinit();
tim8_irq_deinit();
usart1_irq_deinit();
usart2_irq_deinit();
usart3_irq_deinit();
uart4_irq_deinit();
uart5_irq_deinit();
lpuart1_irq_deinit();
}
/** @} */

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os/hal/ports/STM32/STM32L5xx/stm32_isr.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32L5xx/stm32_isr.h
* @brief STM32L5xx ISR handler header.
*
* @addtogroup STM32L5xx_ISR
* @{
*/
#ifndef STM32_ISR_H
#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISRs suppressed in standard drivers
* @{
*/
#define STM32_TIM1_SUPPRESS_ISR
#define STM32_TIM2_SUPPRESS_ISR
#define STM32_TIM3_SUPPRESS_ISR
#define STM32_TIM4_SUPPRESS_ISR
#define STM32_TIM5_SUPPRESS_ISR
#define STM32_TIM6_SUPPRESS_ISR
#define STM32_TIM7_SUPPRESS_ISR
#define STM32_TIM8_SUPPRESS_ISR
#define STM32_TIM15_SUPPRESS_ISR
#define STM32_TIM16_SUPPRESS_ISR
#define STM32_TIM17_SUPPRESS_ISR
#define STM32_USART1_SUPPRESS_ISR
#define STM32_USART2_SUPPRESS_ISR
#define STM32_USART3_SUPPRESS_ISR
#define STM32_UART4_SUPPRESS_ISR
#define STM32_UART5_SUPPRESS_ISR
#define STM32_LPUART1_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers
* @{
*/
/*
* ADC unit.
*/
#define STM32_ADC12_HANDLER VectorD4
#define STM32_ADC12_NUMBER 37
/*
* FDCAN unit.
*/
#define STM32_FDCAN1_IT0_HANDLER VectorDC
#define STM32_FDCAN1_IT1_HANDLER VectorE0
#define STM32_FDCAN1_IT0_NUMBER 39
#define STM32_FDCAN1_IT1_NUMBER 40
/*
* DMA unit.
*/
#define STM32_DMA1_CH1_HANDLER VectorB4
#define STM32_DMA1_CH2_HANDLER VectorB8
#define STM32_DMA1_CH3_HANDLER VectorBC
#define STM32_DMA1_CH4_HANDLER VectorC0
#define STM32_DMA1_CH5_HANDLER VectorC4
#define STM32_DMA1_CH6_HANDLER VectorC8
#define STM32_DMA1_CH7_HANDLER VectorCC
#define STM32_DMA1_CH8_HANDLER VectorD0
#define STM32_DMA2_CH1_HANDLER Vector180
#define STM32_DMA2_CH2_HANDLER Vector184
#define STM32_DMA2_CH3_HANDLER Vector188
#define STM32_DMA2_CH4_HANDLER Vector18C
#define STM32_DMA2_CH5_HANDLER Vector190
#define STM32_DMA2_CH6_HANDLER Vector194
#define STM32_DMA2_CH7_HANDLER Vector198
#define STM32_DMA2_CH8_HANDLER Vector19C
#define STM32_DMA1_CH1_NUMBER 29
#define STM32_DMA1_CH2_NUMBER 30
#define STM32_DMA1_CH3_NUMBER 31
#define STM32_DMA1_CH4_NUMBER 32
#define STM32_DMA1_CH5_NUMBER 33
#define STM32_DMA1_CH6_NUMBER 34
#define STM32_DMA1_CH7_NUMBER 35
#define STM32_DMA1_CH8_NUMBER 36
#define STM32_DMA2_CH1_NUMBER 80
#define STM32_DMA2_CH2_NUMBER 81
#define STM32_DMA2_CH3_NUMBER 82
#define STM32_DMA2_CH4_NUMBER 83
#define STM32_DMA2_CH5_NUMBER 84
#define STM32_DMA2_CH6_NUMBER 85
#define STM32_DMA2_CH7_NUMBER 86
#define STM32_DMA2_CH8_NUMBER 87
/*
* EXTI unit.
*/
#define STM32_EXTI0_HANDLER Vector58
#define STM32_EXTI1_HANDLER Vector5C
#define STM32_EXTI2_HANDLER Vector60
#define STM32_EXTI3_HANDLER Vector64
#define STM32_EXTI4_HANDLER Vector68
#define STM32_EXTI5_HANDLER Vector9C
#define STM32_EXTI6_HANDLER Vector9C
#define STM32_EXTI7_HANDLER Vector9C
#define STM32_EXTI8_HANDLER Vector9C
#define STM32_EXTI9_HANDLER Vector9C
#define STM32_EXTI10_HANDLER VectorE0
#define STM32_EXTI11_HANDLER VectorE0
#define STM32_EXTI12_HANDLER VectorE0
#define STM32_EXTI13_HANDLER VectorE0
#define STM32_EXTI14_HANDLER VectorE0
#define STM32_EXTI15_HANDLER VectorE0
#define STM32_EXTI1635_38_HANDLER Vector44 /* PVD PVM1..PVM4 */
#define STM32_EXTI17_HANDLER Vector48 /* RTC */
#define STM32_EXTI18_HANDLER Vector4C /* RTC (secure) */
#define STM32_EXTI19_HANDLER Vector50 /* TAMP */
#define STM32_EXTI20_HANDLER Vector54 /* TAMP (secure) */
#define STM32_EXTI21_22_HANDLER Vector160 /* COMP1..2 */
#define STM32_EXTI0_NUMBER 11
#define STM32_EXTI1_NUMBER 12
#define STM32_EXTI2_NUMBER 13
#define STM32_EXTI3_NUMBER 14
#define STM32_EXTI4_NUMBER 15
#define STM32_EXTI5_NUMBER 16
#define STM32_EXTI6_NUMBER 17
#define STM32_EXTI7_NUMBER 18
#define STM32_EXTI8_NUMBER 19
#define STM32_EXTI9_NUMBER 20
#define STM32_EXTI10_NUMBER 21
#define STM32_EXTI11_NUMBER 22
#define STM32_EXTI12_NUMBER 23
#define STM32_EXTI13_NUMBER 24
#define STM32_EXTI14_NUMBER 25
#define STM32_EXTI15_NUMBER 26
#define STM32_EXTI1635_38_NUMBER 1
#define STM32_EXTI17_NUMBER 2
#define STM32_EXTI18_NUMBER 3
#define STM32_EXTI19_NUMBER 4
#define STM32_EXTI20_NUMBER 5
#define STM32_EXTI21_22_NUMBER 72
/*
* I2C units.
*/
#define STM32_I2C1_EVENT_HANDLER Vector11C
#define STM32_I2C1_ERROR_HANDLER Vector120
#define STM32_I2C2_EVENT_HANDLER Vector124
#define STM32_I2C2_ERROR_HANDLER Vector138
#define STM32_I2C3_EVENT_HANDLER Vector188
#define STM32_I2C3_ERROR_HANDLER Vector18C
#define STM32_I2C4_EVENT_HANDLER Vector1B8
#define STM32_I2C4_ERROR_HANDLER Vector1BC
#define STM32_I2C1_EVENT_NUMBER 55
#define STM32_I2C1_ERROR_NUMBER 56
#define STM32_I2C2_EVENT_NUMBER 57
#define STM32_I2C2_ERROR_NUMBER 58
#define STM32_I2C3_EVENT_NUMBER 88
#define STM32_I2C3_ERROR_NUMBER 89
#define STM32_I2C4_EVENT_NUMBER 100
#define STM32_I2C4_ERROR_NUMBER 101
/*
* OCTOSPI unit.
*/
#define STM32_OCTOSPI1_HANDLER Vector170
#define STM32_OCTOSPI1_NUMBER 76
/*
* SDMMC unit.
*/
#define STM32_SDMMC1_HANDLER Vector178
#define STM32_SDMMC1_NUMBER 78
/*
* TIM units.
*/
#define STM32_TIM1_BRK_HANDLER VectorE4
#define STM32_TIM1_UP_HANDLER VectorE8
#define STM32_TIM1_TRGCO_HANDLER VectorEC
#define STM32_TIM1_CC_HANDLER VectorF0
#define STM32_TIM2_HANDLER VectorF4
#define STM32_TIM3_HANDLER VectorF8
#define STM32_TIM4_HANDLER VectorFC
#define STM32_TIM5_HANDLER Vector100
#define STM32_TIM6_HANDLER Vector104
#define STM32_TIM7_HANDLER Vector108
#define STM32_TIM8_BRK_HANDLER Vector10C
#define STM32_TIM8_UP_HANDLER Vector110
#define STM32_TIM8_TRGCO_HANDLER Vector114
#define STM32_TIM8_CC_HANDLER Vector118
#define STM32_TIM15_HANDLER Vector154
#define STM32_TIM16_HANDLER Vector158
#define STM32_TIM17_HANDLER Vector15C
#define STM32_TIM1_BRK_NUMBER 41
#define STM32_TIM1_UP_NUMBER 42
#define STM32_TIM1_TRGCO_NUMBER 43
#define STM32_TIM1_CC_NUMBER 44
#define STM32_TIM2_NUMBER 45
#define STM32_TIM3_NUMBER 46
#define STM32_TIM4_NUMBER 47
#define STM32_TIM5_NUMBER 48
#define STM32_TIM6_NUMBER 49
#define STM32_TIM7_NUMBER 50
#define STM32_TIM8_BRK_NUMBER 51
#define STM32_TIM8_UP_NUMBER 52
#define STM32_TIM8_TRGCO_NUMBER 53
#define STM32_TIM8_CC_NUMBER 54
#define STM32_TIM15_NUMBER 69
#define STM32_TIM16_NUMBER 70
#define STM32_TIM17_NUMBER 71
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER Vector134
#define STM32_USART2_HANDLER Vector138
#define STM32_USART3_HANDLER Vector13C
#define STM32_UART4_HANDLER Vector140
#define STM32_UART5_HANDLER Vector144
#define STM32_LPUART1_HANDLER Vector148
#define STM32_USART1_NUMBER 61
#define STM32_USART2_NUMBER 62
#define STM32_USART3_NUMBER 63
#define STM32_UART4_NUMBER 64
#define STM32_UART5_NUMBER 65
#define STM32_LPUART1_NUMBER 66
/*
* USB/OTG units.
*/
#define STM32_USB_FS_HANDLER Vector164
#define STM32_USB_FS_NUMBER 73
/*
* FSMC unit.
*/
#define STM32_FSMC_HANDLER Vector16C
#define STM32_FSMC_NUMBER 75
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void irqInit(void);
void irqDeinit(void);
#ifdef __cplusplus
}
#endif
#endif /* STM32_ISR_H */
/** @} */

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os/hal/ports/STM32/STM32L5xx/stm32_rcc.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32L5xx/stm32_registry.h
* @brief STM32L5xx capabilities registry.
*
* @addtogroup HAL
* @{
*/
#ifndef STM32_REGISTRY_H
#define STM32_REGISTRY_H
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
* @name STM32L5xx capabilities
* @{
*/
/*===========================================================================*/
/* Common. */
/*===========================================================================*/
/* RNG attributes.*/
#define STM32_HAS_RNG1 TRUE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_STORAGE_SIZE 128
#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
#define STM32_RTC_WKUP_HANDLER Vector4C
#define STM32_RTC_ALARM_HANDLER VectorE4
#define STM32_RTC_TAMP_STAMP_NUMBER 2
#define STM32_RTC_WKUP_NUMBER 3
#define STM32_RTC_ALARM_NUMBER 41
#define STM32_RTC_ALARM_EXTI 18
#define STM32_RTC_TAMP_STAMP_EXTI 19
#define STM32_RTC_WKUP_EXTI 20
#define STM32_RTC_IRQ_ENABLE() do { \
nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
} while (false)
#if defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \
defined(__DOXYGEN__)
#define STM32_HAS_HASH1 TRUE
#define STM32_HAS_CRYP1 TRUE
#else
#define STM32_HAS_HASH1 FALSE
#define STM32_HAS_CRYP1 FALSE
#endif
/*===========================================================================*/
/* STM32L4yyxx+. */
/*===========================================================================*/
#if defined(STM32L552xx) || defined(__DOXYGEN__)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
/* CAN attributes.*/
#define STM32_HAS_CAN1 FALSE
#define STM32_HAS_CAN2 FALSE
#define STM32_HAS_CAN3 FALSE
/* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 TRUE
#define STM32_HAS_DAC1_CH2 TRUE
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_DMAMUX TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 8
#define STM32_DMA2_NUM_CHANNELS 8
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 43
#define STM32_EXTI_IMR1_MASK 0xFF9E0000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
/* FDCAN attributes.*/
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE
#define STM32_HAS_GPIOD TRUE
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOH TRUE
#define STM32_HAS_GPIOI FALSE
#define STM32_HAS_GPIOJ FALSE
#define STM32_HAS_GPIOK FALSE
#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
RCC_AHB2ENR_GPIOBEN | \
RCC_AHB2ENR_GPIOCEN | \
RCC_AHB2ENR_GPIODEN | \
RCC_AHB2ENR_GPIOEEN | \
RCC_AHB2ENR_GPIOFEN | \
RCC_AHB2ENR_GPIOGEN | \
RCC_AHB2ENR_GPIOHEN)
/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
#define STM32_HAS_I2C3 TRUE
#define STM32_HAS_I2C4 TRUE
/* OCTOSPI attributes.*/
#define STM32_HAS_OCTOSPI1 TRUE
#define STM32_HAS_OCTOSPI2 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 TRUE
#define STM32_HAS_SDMMC2 FALSE
/* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S FALSE
#define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S FALSE
#define STM32_HAS_SPI4 FALSE
#define STM32_HAS_SPI5 FALSE
#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 6
#define STM32_HAS_TIM1 TRUE
#define STM32_TIM1_IS_32BITS FALSE
#define STM32_TIM1_CHANNELS 6
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS TRUE
#define STM32_TIM2_CHANNELS 4
#define STM32_HAS_TIM3 TRUE
#define STM32_TIM3_IS_32BITS FALSE
#define STM32_TIM3_CHANNELS 4
#define STM32_HAS_TIM4 TRUE
#define STM32_TIM4_IS_32BITS FALSE
#define STM32_TIM4_CHANNELS 4
#define STM32_HAS_TIM5 TRUE
#define STM32_TIM5_IS_32BITS TRUE
#define STM32_TIM5_CHANNELS 4
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
#define STM32_HAS_TIM7 TRUE
#define STM32_TIM7_IS_32BITS FALSE
#define STM32_TIM7_CHANNELS 0
#define STM32_HAS_TIM8 TRUE
#define STM32_TIM8_IS_32BITS FALSE
#define STM32_TIM8_CHANNELS 6
#define STM32_HAS_TIM15 TRUE
#define STM32_TIM15_IS_32BITS FALSE
#define STM32_TIM15_CHANNELS 2
#define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
#define STM32_TIM16_CHANNELS 2
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
#define STM32_TIM17_CHANNELS 2
#define STM32_HAS_TIM9 FALSE
#define STM32_HAS_TIM10 FALSE
#define STM32_HAS_TIM11 FALSE
#define STM32_HAS_TIM12 FALSE
#define STM32_HAS_TIM13 FALSE
#define STM32_HAS_TIM14 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
#define STM32_HAS_TIM20 FALSE
#define STM32_HAS_TIM21 FALSE
#define STM32_HAS_TIM22 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_HAS_USART2 TRUE
#define STM32_HAS_USART3 TRUE
#define STM32_HAS_UART4 TRUE
#define STM32_HAS_UART5 TRUE
#define STM32_HAS_LPUART1 TRUE
#define STM32_HAS_USART6 FALSE
#define STM32_HAS_UART7 FALSE
#define STM32_HAS_UART8 FALSE
/* USB attributes.*/
#define STM32_HAS_USB TRUE
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
#define STM32_USB_PMA_SIZE 1024
#define STM32_USB_HAS_BCDR FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
/* IWDG attributes.*/
#define STM32_HAS_IWDG TRUE
#define STM32_IWDG_IS_WINDOWED TRUE
/* LTDC attributes.*/
#define STM32_HAS_LTDC FALSE
/* DMA2D attributes.*/
#define STM32_HAS_DMA2D FALSE
/* FSMC attributes.*/
#define STM32_HAS_FSMC TRUE
#define STM32_FSMC_IS_FMC FALSE
/* CRC attributes.*/
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE
/* DCMI attributes.*/
#define STM32_HAS_DCMI TRUE
#endif /* defined(STM32L4R5xx) || defined(STM32L4R7xx) ||
defined(STM32L4R9xx) || defined(STM32L4S5xx) ||
defined(STM32L4S7xx) || defined(STM32L4S9xx) */
/** @} */
#endif /* STM32_REGISTRY_H */
/** @} */