From 5afc304e5afac82f2bce2837804019a21c259761 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Oct 2013 10:49:37 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6369 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/NONSTANDARD_STM32F4_BARTHESS1/board.h | 4 +- boards/OLIMEX_STM32_E407/board.c | 36 +- boards/OLIMEX_STM32_E407/board.h | 28 +- boards/OLIMEX_STM32_E407/cfg/board.chcfg | 1 + boards/OLIMEX_STM32_H407/board.c | 36 +- boards/OLIMEX_STM32_H407/board.h | 126 +- boards/OLIMEX_STM32_H407/cfg/board.chcfg | 1 + boards/OLIMEX_STM32_P407/board.h | 4 +- boards/ST_STM32F4_DISCOVERY/board.c | 24 +- boards/ST_STM32F4_DISCOVERY/board.h | 28 +- boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg | 1 + .../ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h | 2 +- os/hal/platforms/STM32/stm32.h | 3 +- os/hal/platforms/STM32F4xx/hal_lld.c | 2 +- os/hal/platforms/STM32F4xx/hal_lld.h | 128 +- os/hal/platforms/STM32F4xx/stm32f4xx.h | 3120 ++++++++++++++--- 16 files changed, 2911 insertions(+), 633 deletions(-) diff --git a/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h b/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h index 78ae3bd0e..a51044f61 100644 --- a/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h +++ b/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h @@ -41,9 +41,9 @@ #define STM32_VDD 300 /* - * MCU type as defined in the ST header file stm32f4xx.h. + * MCU type as defined in the ST header. */ -#define STM32F4XX +#define STM32F40_41xxx /* * IO pins assignments. diff --git a/boards/OLIMEX_STM32_E407/board.c b/boards/OLIMEX_STM32_E407/board.c index a4152433a..fc9d1aab9 100644 --- a/boards/OLIMEX_STM32_E407/board.c +++ b/boards/OLIMEX_STM32_E407/board.c @@ -1,17 +1,21 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at + This file is part of ChibiOS/RT. - http://www.apache.org/licenses/LICENSE-2.0 + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ #include "ch.h" @@ -61,10 +65,10 @@ void __early_init(void) { * @brief SDC card detection. */ bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { - static bool_t last_status = FALSE; - - if (blkIsTransferring(sdcp)) - return last_status; + static bool_t last_status = FALSE; + + if (blkIsTransferring(sdcp)) + return last_status; return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3); } @@ -72,8 +76,8 @@ bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { * @brief SDC card write protection detection. */ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; + + (void)sdcp; return FALSE; } #endif /* HAL_USE_SDC */ diff --git a/boards/OLIMEX_STM32_E407/board.h b/boards/OLIMEX_STM32_E407/board.h index 505f30f7d..638ac5561 100644 --- a/boards/OLIMEX_STM32_E407/board.h +++ b/boards/OLIMEX_STM32_E407/board.h @@ -1,17 +1,21 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at + This file is part of ChibiOS/RT. - http://www.apache.org/licenses/LICENSE-2.0 + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ #ifndef _BOARD_H_ @@ -52,9 +56,9 @@ #define STM32_VDD 330 /* - * MCU type as defined in the ST header file stm32f4xx.h. + * MCU type as defined in the ST header. */ -#define STM32F4XX +#define STM32F401xx /* * IO pins assignments. diff --git a/boards/OLIMEX_STM32_E407/cfg/board.chcfg b/boards/OLIMEX_STM32_E407/cfg/board.chcfg index 4d4abeb04..f55bd1471 100644 --- a/boards/OLIMEX_STM32_E407/cfg/board.chcfg +++ b/boards/OLIMEX_STM32_E407/cfg/board.chcfg @@ -22,6 +22,7 @@ MII_KS8721_ID RMII + STM32F40_41xxx diff --git a/boards/OLIMEX_STM32_H407/board.c b/boards/OLIMEX_STM32_H407/board.c index a4152433a..fc9d1aab9 100644 --- a/boards/OLIMEX_STM32_H407/board.c +++ b/boards/OLIMEX_STM32_H407/board.c @@ -1,17 +1,21 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at + This file is part of ChibiOS/RT. - http://www.apache.org/licenses/LICENSE-2.0 + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ #include "ch.h" @@ -61,10 +65,10 @@ void __early_init(void) { * @brief SDC card detection. */ bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { - static bool_t last_status = FALSE; - - if (blkIsTransferring(sdcp)) - return last_status; + static bool_t last_status = FALSE; + + if (blkIsTransferring(sdcp)) + return last_status; return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3); } @@ -72,8 +76,8 @@ bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { * @brief SDC card write protection detection. */ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; + + (void)sdcp; return FALSE; } #endif /* HAL_USE_SDC */ diff --git a/boards/OLIMEX_STM32_H407/board.h b/boards/OLIMEX_STM32_H407/board.h index a53712db0..902ff19e8 100644 --- a/boards/OLIMEX_STM32_H407/board.h +++ b/boards/OLIMEX_STM32_H407/board.h @@ -1,24 +1,28 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at + This file is part of ChibiOS/RT. - http://www.apache.org/licenses/LICENSE-2.0 + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ #ifndef _BOARD_H_ #define _BOARD_H_ /* - * Setup for Olimex STM32-E407 board. + * Setup for Olimex STM32-H407 board. */ /* @@ -52,9 +56,9 @@ #define STM32_VDD 330 /* - * MCU type as defined in the ST header file stm32f4xx.h. + * MCU type as defined in the ST header. */ -#define STM32F4XX +#define STM32F40_41xxx /* * IO pins assignments. @@ -69,20 +73,20 @@ #define GPIOA_ETH_RMII_CRS_DV 7 #define GPIOA_USB_HS_BUSON 8 #define GPIOA_OTG_FS_VBUS 9 -#define GPIOA_USB_FS_BUSON 10 +#define GPIOA_OTG_FS_ID 10 #define GPIOA_OTG_FS_DM 11 #define GPIOA_OTG_FS_DP 12 #define GPIOA_JTAG_TMS 13 #define GPIOA_JTAG_TCK 14 #define GPIOA_JTAG_TDI 15 -#define GPIOB_PIN0 0 -#define GPIOB_PIN1 1 +#define GPIOB_USB_FS_BUSON 0 +#define GPIOB_USB_HS_FAULT 1 #define GPIOB_BOOT1 2 #define GPIOB_JTAG_TDO 3 #define GPIOB_JTAG_TRST 4 -#define GPIOB_USB_HS_FAULT 5 -#define GPIOB_USB_FS_FAULT 6 +#define GPIOB_PIN5 5 +#define GPIOB_PIN6 6 #define GPIOB_PIN7 7 #define GPIOB_I2C1_SCL 8 #define GPIOB_I2C1_SDA 9 @@ -155,7 +159,7 @@ #define GPIOF_PIN8 8 #define GPIOF_PIN9 9 #define GPIOF_PIN10 10 -#define GPIOF_PIN11 11 +#define GPIOF_USB_FS_FAULT 11 #define GPIOF_PIN12 12 #define GPIOF_PIN13 13 #define GPIOF_PIN14 14 @@ -247,7 +251,7 @@ * PA7 - ETH_RMII_CRS_DV (alternate 11). * PA8 - USB_HS_BUSON (output pushpull maximum). * PA9 - OTG_FS_VBUS (input pulldown). - * PA10 - USB_FS_BUSON (output pushpull maximum). + * PA10 - OTG_FS_ID (alternate 10). * PA11 - OTG_FS_DM (alternate 10). * PA12 - OTG_FS_DP (alternate 10). * PA13 - JTAG_TMS (alternate 0). @@ -264,7 +268,7 @@ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\ PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \ PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \ - PIN_MODE_OUTPUT(GPIOA_USB_FS_BUSON) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \ @@ -280,7 +284,7 @@ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\ PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\ - PIN_OTYPE_PUSHPULL(GPIOA_USB_FS_BUSON) |\ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \ @@ -296,7 +300,7 @@ PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\ PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) | \ PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) | \ - PIN_OSPEED_100M(GPIOA_USB_FS_BUSON) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ PIN_OSPEED_100M(GPIOA_JTAG_TMS) | \ @@ -312,7 +316,7 @@ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\ PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\ PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\ - PIN_PUPDR_FLOATING(GPIOA_USB_FS_BUSON) |\ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) | \ @@ -328,7 +332,7 @@ PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \ PIN_ODR_HIGH(GPIOA_USB_HS_BUSON) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \ - PIN_ODR_HIGH(GPIOA_USB_FS_BUSON) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \ @@ -344,7 +348,7 @@ PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11)) #define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) | \ PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \ - PIN_AFIO_AF(GPIOA_USB_FS_BUSON, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \ @@ -354,13 +358,13 @@ /* * GPIOB setup: * - * PB0 - PIN0 (input pullup). - * PB1 - PIN1 (input pullup). + * PB0 - USB_FS_BUSON (output pushpull maximum). + * PB1 - USB_HS_FAULT (input floating). * PB2 - BOOT1 (input floating). * PB3 - JTAG_TDO (alternate 0). * PB4 - JTAG_TRST (alternate 0). - * PB5 - USB_HS_FAULT (input floating). - * PB6 - USB_FS_FAULT (input floating). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). * PB7 - PIN7 (input pullup). * PB8 - I2C1_SCL (alternate 4). * PB9 - I2C1_SDA (alternate 4). @@ -371,13 +375,13 @@ * PB14 - OTG_HS_DM (alternate 12). * PB15 - OTG_HS_DP (alternate 12). */ -#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ - PIN_MODE_INPUT(GPIOB_PIN1) | \ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) | \ + PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \ PIN_MODE_INPUT(GPIOB_BOOT1) | \ PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \ PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \ - PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \ - PIN_MODE_INPUT(GPIOB_USB_FS_FAULT) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ PIN_MODE_INPUT(GPIOB_PIN7) | \ PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ @@ -387,13 +391,13 @@ PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\ + PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\ PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \ PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \ - PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\ - PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_FAULT) |\ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ @@ -403,13 +407,13 @@ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \ - PIN_OSPEED_100M(GPIOB_PIN1) | \ +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_USB_FS_BUSON) | \ + PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) | \ PIN_OSPEED_100M(GPIOB_BOOT1) | \ PIN_OSPEED_100M(GPIOB_JTAG_TDO) | \ PIN_OSPEED_100M(GPIOB_JTAG_TRST) | \ - PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) | \ - PIN_OSPEED_100M(GPIOB_USB_FS_FAULT) | \ + PIN_OSPEED_100M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_PIN6) | \ PIN_OSPEED_100M(GPIOB_PIN7) | \ PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ @@ -419,13 +423,13 @@ PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) | \ PIN_OSPEED_100M(GPIOB_OTG_HS_DM) | \ PIN_OSPEED_100M(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\ + PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\ PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \ PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) | \ - PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\ - PIN_PUPDR_FLOATING(GPIOB_USB_FS_FAULT) |\ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ @@ -435,13 +439,13 @@ PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\ PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ - PIN_ODR_HIGH(GPIOB_PIN1) | \ +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_USB_FS_BUSON) | \ + PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \ PIN_ODR_HIGH(GPIOB_BOOT1) | \ PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \ PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \ - PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \ - PIN_ODR_HIGH(GPIOB_USB_FS_FAULT) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ PIN_ODR_HIGH(GPIOB_PIN7) | \ PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ @@ -451,13 +455,13 @@ PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \ PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \ PIN_ODR_HIGH(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ - PIN_AFIO_AF(GPIOB_PIN1, 0) | \ +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) | \ + PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) | \ PIN_AFIO_AF(GPIOB_BOOT1, 0) | \ PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \ PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \ - PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) | \ - PIN_AFIO_AF(GPIOB_USB_FS_FAULT, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0) | \ PIN_AFIO_AF(GPIOB_PIN7, 0)) #define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \ @@ -833,7 +837,7 @@ * PF8 - PIN8 (input pullup). * PF9 - PIN9 (input pullup). * PF10 - PIN10 (input pullup). - * PF11 - PIN11 (input pullup). + * PF11 - USB_FS_FAULT (input floating). * PF12 - PIN12 (input pullup). * PF13 - PIN13 (input pullup). * PF14 - PIN14 (input pullup). @@ -850,7 +854,7 @@ PIN_MODE_INPUT(GPIOF_PIN8) | \ PIN_MODE_INPUT(GPIOF_PIN9) | \ PIN_MODE_INPUT(GPIOF_PIN10) | \ - PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) | \ PIN_MODE_INPUT(GPIOF_PIN12) | \ PIN_MODE_INPUT(GPIOF_PIN13) | \ PIN_MODE_INPUT(GPIOF_PIN14) | \ @@ -866,7 +870,7 @@ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ @@ -882,7 +886,7 @@ PIN_OSPEED_100M(GPIOF_PIN8) | \ PIN_OSPEED_100M(GPIOF_PIN9) | \ PIN_OSPEED_100M(GPIOF_PIN10) | \ - PIN_OSPEED_100M(GPIOF_PIN11) | \ + PIN_OSPEED_100M(GPIOF_USB_FS_FAULT) | \ PIN_OSPEED_100M(GPIOF_PIN12) | \ PIN_OSPEED_100M(GPIOF_PIN13) | \ PIN_OSPEED_100M(GPIOF_PIN14) | \ @@ -898,7 +902,7 @@ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ @@ -914,7 +918,7 @@ PIN_ODR_HIGH(GPIOF_PIN8) | \ PIN_ODR_HIGH(GPIOF_PIN9) | \ PIN_ODR_HIGH(GPIOF_PIN10) | \ - PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) | \ PIN_ODR_HIGH(GPIOF_PIN12) | \ PIN_ODR_HIGH(GPIOF_PIN13) | \ PIN_ODR_HIGH(GPIOF_PIN14) | \ @@ -930,7 +934,7 @@ #define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ PIN_AFIO_AF(GPIOF_PIN9, 0) | \ PIN_AFIO_AF(GPIOF_PIN10, 0) | \ - PIN_AFIO_AF(GPIOF_PIN11, 0) | \ + PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0) | \ PIN_AFIO_AF(GPIOF_PIN12, 0) | \ PIN_AFIO_AF(GPIOF_PIN13, 0) | \ PIN_AFIO_AF(GPIOF_PIN14, 0) | \ diff --git a/boards/OLIMEX_STM32_H407/cfg/board.chcfg b/boards/OLIMEX_STM32_H407/cfg/board.chcfg index 485c5db4c..edf298a2e 100644 --- a/boards/OLIMEX_STM32_H407/cfg/board.chcfg +++ b/boards/OLIMEX_STM32_H407/cfg/board.chcfg @@ -22,6 +22,7 @@ MII_KS8721_ID RMII + STM32F40_41xxx diff --git a/boards/OLIMEX_STM32_P407/board.h b/boards/OLIMEX_STM32_P407/board.h index 66279a8f9..c43368dfd 100644 --- a/boards/OLIMEX_STM32_P407/board.h +++ b/boards/OLIMEX_STM32_P407/board.h @@ -49,9 +49,9 @@ #define STM32_VDD 330 /* - * MCU type as defined in the ST header file stm32f4xx.h. + * MCU type as defined in the ST header. */ -#define STM32F4XX +#define STM32F40_41xxx /* * IO pins assignments. diff --git a/boards/ST_STM32F4_DISCOVERY/board.c b/boards/ST_STM32F4_DISCOVERY/board.c index 99569f695..7891db97a 100644 --- a/boards/ST_STM32F4_DISCOVERY/board.c +++ b/boards/ST_STM32F4_DISCOVERY/board.c @@ -1,17 +1,21 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at + This file is part of ChibiOS/RT. - http://www.apache.org/licenses/LICENSE-2.0 + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ #include "ch.h" diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h index 6e636db9e..4ce0305c8 100644 --- a/boards/ST_STM32F4_DISCOVERY/board.h +++ b/boards/ST_STM32F4_DISCOVERY/board.h @@ -1,17 +1,21 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at + This file is part of ChibiOS/RT. - http://www.apache.org/licenses/LICENSE-2.0 + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ #ifndef _BOARD_H_ @@ -48,9 +52,9 @@ #define STM32_VDD 300 /* - * MCU type as defined in the ST header file stm32f4xx.h. + * MCU type as defined in the ST header. */ -#define STM32F4XX +#define STM32F40_41xxx /* * IO pins assignments. diff --git a/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg b/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg index e30de70e6..e60257f6e 100644 --- a/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg +++ b/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg @@ -10,6 +10,7 @@ STMicroelectronics STM32F4-Discovery ST_STM32F4_DISCOVERY + STM32F40_41xxx diff --git a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h index b2921f0fe..6701cf712 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h @@ -57,7 +57,7 @@ #define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SR_VALUE 5 -#define STM32_VOS STM32_VOS_HIGH +#define STM32_VOS STM32_VOS_SCALE1 #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE diff --git a/os/hal/platforms/STM32/stm32.h b/os/hal/platforms/STM32/stm32.h index 67dcd6eb2..d8abed37d 100644 --- a/os/hal/platforms/STM32/stm32.h +++ b/os/hal/platforms/STM32/stm32.h @@ -61,7 +61,8 @@ #elif defined(STM32F37X) #include "stm32f37x.h" -#elif defined(STM32F4XX) +#elif defined(STM32F401xx) || defined(STM32F40_41xxx) || \ + defined(STM32F427_437xx) || defined(STM32F429_439xx) #include "stm32f4xx.h" #elif defined(STM32L1XX_MD) diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c index ad3a32a0f..bbe45fe43 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.c +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -153,7 +153,7 @@ void stm32_clock_init(void) { /* PWR initialization.*/ #if defined(STM32F4XX) || defined(__DOXYGEN__) - PWR->CR = STM32_VOS; + PWR->CR = STM32_VOS & STM32_VOS_MASK; while ((PWR->CSR & PWR_CSR_VOSRDY) == 0) ; /* Waits until power regulator is stable. */ #else diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index f524ac900..5207401ad 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -20,13 +20,18 @@ * @pre This module requires the following macros to be defined in the * @p board.h file: * - STM32_LSECLK. + * - STM32_LSEDRV. + * - STM32_LSE_BYPASS (optionally). * - STM32_HSECLK. * - STM32_HSE_BYPASS (optionally). * - STM32_VDD (as hundredths of Volt). * . * One of the following macros must also be defined: * - STM32F2XX for High-performance STM32 F-2 devices. - * - STM32F4XX for High-performance STM32 F-4 devices. + * - STM32F401xx for High-performance STM32 F-4 devices. + * - STM32F40_41xxx for High-performance STM32 F-4 devices. + * - STM32F427_437xx for High-performance STM32 F-4 devices. + * - STM32F429_439xx for High-performance STM32 F-4 devices. * . * * @addtogroup HAL @@ -51,32 +56,60 @@ * @name Platform identification * @{ */ -#if defined(STM32F4XX) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F4xx High Performance" -#else /* !defined(STM32F4XX) */ +#if defined(STM32F429_439xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU" +#elif defined(STM32F427_437xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU" +#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU" +#elif defined(STM32F401) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU" +#elif defined(STM32F2XX) || defined(__DOXYGEN__) #define PLATFORM_NAME "STM32F2xx High Performance" -#endif /* !defined(STM32F4XX) */ +#else +#error "STM32F2xx/F4xx device not specified" +#endif /** @} */ /** * @name Absolute Maximum Ratings * @{ */ -#if defined(STM32F4XX) || defined(__DOXYGEN__) +/** + * @name Absolute Maximum Ratings + * @{ + */ +#if defined(STM32F429_439xx) || defined(STM32F429_439xx) || \ + defined(__DOXYGEN__) /** * @brief Maximum HSE clock frequency. */ #define STM32_HSECLK_MAX 26000000 +/** + * @brief Maximum HSE clock frequency using an external source. + */ +#define STM32_HSECLK_BYP_MAX 50000000 + /** * @brief Minimum HSE clock frequency. */ -#define STM32_HSECLK_MIN 1000000 +#define STM32_HSECLK_MIN 4000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_BYP_MIN 1000000 /** * @brief Maximum LSE clock frequency. */ -#define STM32_LSECLK_MAX 1000000 +#define STM32_LSECLK_MAX 32768 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_BYP_MAX 1000000 /** * @brief Minimum LSE clock frequency. @@ -86,7 +119,7 @@ /** * @brief Maximum PLLs input clock frequency. */ -#define STM32_PLLIN_MAX 2000000 +#define STM32_PLLIN_MAX 2100000 /** * @brief Minimum PLLs input clock frequency. @@ -106,7 +139,7 @@ /** * @brief Maximum PLL output clock frequency. */ -#define STM32_PLLOUT_MAX 168000000 +#define STM32_PLLOUT_MAX 180000000 /** * @brief Minimum PLL output clock frequency. @@ -116,23 +149,65 @@ /** * @brief Maximum APB1 clock frequency. */ -#define STM32_PCLK1_MAX 42000000 +#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4) /** * @brief Maximum APB2 clock frequency. */ -#define STM32_PCLK2_MAX 84000000 +#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2) /** * @brief Maximum SPI/I2S clock frequency. */ #define STM32_SPII2S_MAX 37500000 +#endif /* STM32F40_41xxx */ -#else /* !defined(STM32F4XX) */ +#if defined(STM32F40_41xxx) || defined(__DOXYGEN__) +#define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_BYP_MAX 50000000 +#define STM32_HSECLK_MIN 4000000 +#define STM32_HSECLK_BYP_MIN 1000000 +#define STM32_LSECLK_MAX 32768 +#define STM32_LSECLK_BYP_MAX 1000000 +#define STM32_LSECLK_MIN 32768 +#define STM32_PLLIN_MAX 2100000 +#define STM32_PLLIN_MIN 950000 +#define STM32_PLLVCO_MAX 432000000 +#define STM32_PLLVCO_MIN 192000000 +#define STM32_PLLOUT_MAX 168000000 +#define STM32_PLLOUT_MIN 24000000 +#define STM32_PCLK1_MAX 42000000 +#define STM32_PCLK2_MAX 84000000 +#define STM32_SPII2S_MAX 37500000 +#endif /* STM32F40_41xxx */ + +#if defined(STM32F401) || defined(__DOXYGEN__) +#define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_BYP_MAX 50000000 +#define STM32_HSECLK_MIN 4000000 +#define STM32_HSECLK_BYP_MIN 1000000 +#define STM32_LSECLK_MAX 32768 +#define STM32_LSECLK_BYP_MAX 1000000 +#define STM32_LSECLK_MIN 32768 +#define STM32_PLLIN_MAX 2100000 +#define STM32_PLLIN_MIN 950000 +#define STM32_PLLVCO_MAX 432000000 +#define STM32_PLLVCO_MIN 192000000 +#define STM32_PLLOUT_MAX 168000000 +#define STM32_PLLOUT_MIN 24000000 +#define STM32_PCLK1_MAX 42000000 +#define STM32_PCLK2_MAX 84000000 +#define STM32_SPII2S_MAX 37500000 +#endif /* STM32F40_41xxx */ + +#if defined(STM32F2XX) #define STM32_SYSCLK_MAX 120000000 #define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_BYP_MAX 26000000 #define STM32_HSECLK_MIN 1000000 -#define STM32_LSECLK_MAX 1000000 +#define STM32_HSECLK_BYP_MIN 1000000 +#define STM32_LSECLK_MAX 32768 +#define STM32_LSECLK_BYP_MAX 1000000 #define STM32_LSECLK_MIN 32768 #define STM32_PLLIN_MAX 2000000 #define STM32_PLLIN_MIN 950000 @@ -143,7 +218,7 @@ #define STM32_PCLK1_MAX 30000000 #define STM32_PCLK2_MAX 60000000 #define STM32_SPII2S_MAX 37500000 -#endif /* !defined(STM32F4XX) */ +#endif /* defined(STM32F2XX) */ /** @} */ /** @@ -163,6 +238,19 @@ #define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */ #define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */ #endif + +#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ + defined(STM32F401) || defined(__DOXYGEN__) +#define STM32_VOS_MASK (3 << 14) /**< Scale Mode mask. */ +#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__) +#define STM32_VOS_MASK (1 << 14) /**< Scale Mode mask. */ +#else +#endif + +#define STM32_VOS_SCALE3 (1 << 14) /**< Scale 3 mode. */ +#define STM32_VOS_SCALE2 (2 << 14) /**< Scale 2 mode. */ +#define STM32_VOS_SCALE1 (3 << 14) /**< Scale 2 mode. */ + #define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ #define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ #define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ @@ -859,6 +947,14 @@ /* Derived constants and error checks. */ /*===========================================================================*/ +/* + * Generic STM32F4XX identifier for backward compatibility. + */ +#if defined(STM32F401xx) || defined(STM32F40_41xxx) || \ + defined(STM32F427_437xx) || defined(STM32F429_439xx) +#define STM32F4XX +#endif + #if defined(STM32F4XX) || defined(__DOXYGEN__) /* * Configuration-related checks. @@ -871,7 +967,7 @@ * @brief Maximum SYSCLK. * @note It is a function of the core voltage setting. */ -#if (STM32_VOS == STM32_VOS_HIGH) || defined(__DOXYGEN__) +#if (STM32_VOS == STM32_VOS_SCALE1) || defined(__DOXYGEN__) #define STM32_SYSCLK_MAX 168000000 #else #define STM32_SYSCLK_MAX 144000000 diff --git a/os/hal/platforms/STM32F4xx/stm32f4xx.h b/os/hal/platforms/STM32F4xx/stm32f4xx.h index 52b9f24e2..1ddbeb36c 100644 --- a/os/hal/platforms/STM32F4xx/stm32f4xx.h +++ b/os/hal/platforms/STM32F4xx/stm32f4xx.h @@ -2,37 +2,43 @@ ****************************************************************************** * @file stm32f4xx.h * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 + * @version V1.2.1 + * @date 19-September-2013 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F4xx devices. + * definitions and memory mapping for STM32F4xx devices. * * The file is the unique include file that the application programmer * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_STDPERIPH_DRIVER" * - To change few application-specific parameters such as the HSE * crystal frequency * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral�s registers hardware + * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + *

© COPYRIGHT 2013 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * - *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ @@ -59,16 +65,39 @@ application */ -#if !defined (STM32F4XX) - #define STM32F4XX +#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) + /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, + STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, + STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + + /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, + STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ + + /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, + STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, + STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, + STM32F439IG and STM32F439II Devices */ + + /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + #endif +/* Old STM32F40XX definition, maintained for legacy purpose */ +#ifdef STM32F40XX + #define STM32F40_41xxx +#endif /* STM32F40XX */ + +/* Old STM32F427X definition, maintained for legacy purpose */ +#ifdef STM32F427X + #define STM32F427_437xx +#endif /* STM32F427X */ + /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ -#if !defined (STM32F4XX) - #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)" +#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #endif #if !defined (USE_STDPERIPH_DRIVER) @@ -77,7 +106,7 @@ In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ - /*#define USE_STDPERIPH_DRIVER*/ + /*#define USE_STDPERIPH_DRIVER */ #endif /* USE_STDPERIPH_DRIVER */ /** @@ -90,6 +119,7 @@ #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #endif /* HSE_VALUE */ /** @@ -97,7 +127,7 @@ Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ #endif /* HSE_STARTUP_TIMEOUT */ #if !defined (HSI_VALUE) @@ -105,10 +135,10 @@ #endif /* HSI_VALUE */ /** - * @brief STM32F4XX Standard Peripherals Library version number V1.0.0 + * @brief STM32F4XX Standard Peripherals Library version number V1.2.0 */ #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ @@ -168,6 +198,8 @@ typedef enum IRQn DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + +#if defined (STM32F40_41xxx) CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ @@ -220,7 +252,7 @@ typedef enum IRQn DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ @@ -229,8 +261,198 @@ typedef enum IRQn OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ FPU_IRQn = 81 /*!< FPU global interrupt */ +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +#endif /* STM32F427_437xx */ + +#if defined (STM32F429_439xx) + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ +#endif /* STM32F429_439xx */ + +#if defined (STM32F401xx) + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ +#endif /* STM32F401xx */ + } IRQn_Type; /** @@ -239,7 +461,7 @@ typedef enum IRQn #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ /* CHIBIOS FIX */ -/*#include "system_stm32f4xx.h"*/ +//#include "system_stm32f4xx.h" #include /** @addtogroup Exported_types @@ -481,6 +703,37 @@ typedef struct __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; /** * @brief Ethernet MAC @@ -576,14 +829,16 @@ typedef struct typedef struct { - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ } FLASH_TypeDef; +#if defined (STM32F40_41xxx) /** * @brief Flexible Static Memory Controller */ @@ -642,10 +897,86 @@ typedef struct __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ } FSMC_Bank4_TypeDef; +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FMC_Bank4_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; +#endif /* STM32F427_437xx || STM32F429_439xx */ /** * @brief General Purpose I/O */ + /* CHIBIOS FIX */ #if 0 typedef struct @@ -700,6 +1031,8 @@ typedef struct uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ + uint16_t RESERVED9; /*!< Reserved, 0x26 */ } I2C_TypeDef; /** @@ -714,6 +1047,54 @@ typedef struct __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ } IWDG_TypeDef; +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + /** * @brief Power Control */ @@ -760,6 +1141,9 @@ typedef struct uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + } RCC_TypeDef; /** @@ -810,6 +1194,28 @@ typedef struct __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ } RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + /** * @brief SD host Interface */ @@ -947,26 +1353,42 @@ typedef struct typedef struct { - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ } CRYP_TypeDef; /** @@ -975,18 +1397,27 @@ typedef struct typedef struct { - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ } HASH_TypeDef; /** - * @brief HASH + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG */ typedef struct @@ -1007,13 +1438,22 @@ typedef struct #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ + +#if defined (STM32F40_41xxx) #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ +#endif /* STM32F427_437xx || STM32F429_439xx */ #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ @@ -1056,6 +1496,8 @@ typedef struct #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) #define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) /*!< APB2 peripherals */ #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) @@ -1068,11 +1510,20 @@ typedef struct #define ADC_BASE (APB2PERIPH_BASE + 0x2300) #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) /*!< AHB1 peripherals */ #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) @@ -1084,6 +1535,8 @@ typedef struct #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) @@ -1110,19 +1563,33 @@ typedef struct #define ETH_MMC_BASE (ETH_BASE + 0x0100) #define ETH_PTP_BASE (ETH_BASE + 0x0700) #define ETH_DMA_BASE (ETH_BASE + 0x1000) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) /*!< AHB2 peripherals */ #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) #define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) +#if defined (STM32F40_41xxx) /*!< FSMC Bankx registers base address */ #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) +#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) +#endif /* STM32F427_437xx || STM32F429_439xx */ /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0xE0042000) @@ -1161,6 +1628,8 @@ typedef struct #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) @@ -1170,12 +1639,21 @@ typedef struct #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) @@ -1185,6 +1663,8 @@ typedef struct #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) @@ -1207,15 +1687,30 @@ typedef struct #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define CRYP ((CRYP_TypeDef *) CRYP_BASE) #define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) + +#if defined (STM32F40_41xxx) #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#endif /* STM32F40_41xxx */ + +#if defined (STM32F427_437xx) || defined (STM32F429_439xx) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#endif /* STM32F427_437xx || STM32F429_439xx */ + #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** @@ -1240,12 +1735,12 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!