git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5453 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -267,6 +267,21 @@
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#define ADC_ACR_RESSEL_8BITS (2U << 6)
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#define ADC_ACR_RESSEL_8BITS (2U << 6)
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/** @} */
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/** @} */
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/**
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* @name ADC PUDCRx registers definitions
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* @{
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*/
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#define ADC_PUDCR_NONE 0x0000
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#define ADC_PUDCR_UP_200K 0x1100
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#define ADC_PUDCR_UP_100K 0x1200
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#define ADC_PUDCR_UP_5K 0x1300
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#define ADC_PUDCR_DOWN_200K 0x2100
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#define ADC_PUDCR_DOWN_100K 0x2200
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#define ADC_PUDCR_DOWN_5K 0x2300
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#define ADC_PUDCR_UP_DOWN_200K 0x3100
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#define ADC_PUDCR_UP_DOWN_100K 0x3200
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/** @} */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -424,7 +439,14 @@
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* @brief Initialization value for PUDCRx registers.
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* @brief Initialization value for PUDCRx registers.
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*/
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*/
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#if !defined(SPC5_ADC_PUDCR) || defined(__DOXYGEN__)
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#if !defined(SPC5_ADC_PUDCR) || defined(__DOXYGEN__)
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#define SPC5_ADC_PUDCR {0, 0, 0, 0, 0, 0, 0, 0}
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#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE}
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#endif
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#endif
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/** @} */
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/** @} */
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@ -51,7 +51,27 @@
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#define SPC5_ADC_USE_ADC1_Q3 TRUE
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#define SPC5_ADC_USE_ADC1_Q3 TRUE
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#define SPC5_ADC_USE_ADC1_Q4 TRUE
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#define SPC5_ADC_USE_ADC1_Q4 TRUE
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#define SPC5_ADC_USE_ADC1_Q5 TRUE
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#define SPC5_ADC_USE_ADC1_Q5 TRUE
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#define SPC5_ADC_FIFO0_DMA_PRIO 12
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#define SPC5_ADC_FIFO1_DMA_PRIO 12
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#define SPC5_ADC_FIFO2_DMA_PRIO 12
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#define SPC5_ADC_FIFO3_DMA_PRIO 12
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#define SPC5_ADC_FIFO4_DMA_PRIO 12
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#define SPC5_ADC_FIFO5_DMA_PRIO 12
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#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12
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#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
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#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
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#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE}
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/*
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/*
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* SERIAL driver system settings.
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* SERIAL driver system settings.
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