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Fixed warnings. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14619 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-07-26 07:51:51 +00:00
parent fc407d0086
commit 5bbbe91ccb
3 changed files with 9 additions and 9 deletions
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6
os/hal/ports/STM32/STM32G0xx/hal_lld.c
View File

@ -195,7 +195,7 @@ static const system_limits_t vos_range2 = {
*
* @param[in] acr value for the ACR register
*/
static void flash_set_acr(uint32_t acr) {
__STATIC_INLINE void flash_set_acr(uint32_t acr) {
FLASH->ACR = acr;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) {
@ -207,7 +207,7 @@ static void flash_set_acr(uint32_t acr) {
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
*/
static void hal_lld_set_static_pwr(void) {
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
/* PWR clock enabled.*/
rccEnablePWRInterface(false);
@ -250,7 +250,7 @@ static void hal_lld_set_static_pwr(void) {
/**
* @brief Initializes static muxes and dividers.
*/
static void hal_lld_set_static_clocks(void) {
__STATIC_INLINE void hal_lld_set_static_clocks(void) {
/* Clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE | STM32_HPRE;

6
os/hal/ports/STM32/STM32G4xx/hal_lld.c
View File

@ -214,7 +214,7 @@ static const system_limits_t vos_range2 = {
*
* @param[in] acr value for the ACR register
*/
static void flash_set_acr(uint32_t acr) {
__STATIC_INLINE void flash_set_acr(uint32_t acr) {
FLASH->ACR = acr;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) {
@ -226,7 +226,7 @@ static void flash_set_acr(uint32_t acr) {
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
*/
static void hal_lld_set_static_pwr(void) {
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
/* PWR clock enabled.*/
rccEnablePWRInterface(false);
@ -269,7 +269,7 @@ static void hal_lld_set_static_pwr(void) {
/**
* @brief Initializes static muxes and dividers.
*/
static void hal_lld_set_static_clocks(void) {
__STATIC_INLINE void hal_lld_set_static_clocks(void) {
/* Clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE2 | STM32_PPRE1 |

6
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
View File

@ -241,7 +241,7 @@ static const system_limits_t vos_range2 = {
*
* @param[in] acr value for the ACR register
*/
static void flash_set_acr(uint32_t acr) {
__STATIC_INLINE void flash_set_acr(uint32_t acr) {
FLASH->ACR = acr;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) {
@ -253,7 +253,7 @@ static void flash_set_acr(uint32_t acr) {
* @brief Configures the PWR unit.
* @note CR1, CR2 and CR5 are not initialized inside this function.
*/
static void hal_lld_set_static_pwr(void) {
__STATIC_INLINE void hal_lld_set_static_pwr(void) {
/* PWR clock enabled.*/
rccEnablePWRInterface(false);
@ -296,7 +296,7 @@ static void hal_lld_set_static_pwr(void) {
/**
* @brief Initializes static muxes and dividers.
*/
static void hal_lld_set_static_clocks(void) {
__STATIC_INLINE void hal_lld_set_static_clocks(void) {
uint32_t ccipr;
/* Clock-related settings (dividers, MCO etc).*/