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STM32L driver tested and working. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3387 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2011-09-24 06:53:13 +00:00
parent 09d93604e7
commit 5bf43b6500
1 changed files with 10 additions and 10 deletions
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20
os/hal/platforms/STM32L1xx/adc_lld.c
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@ -188,23 +188,24 @@ void adc_lld_stop(ADCDriver *adcp) {
* @notapi * @notapi
*/ */
void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode, n; uint32_t mode, cr2;
const ADCConversionGroup *grpp = adcp->grpp; const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/ /* DMA setup.*/
mode = adcp->dmamode; mode = adcp->dmamode;
if (grpp->circular) cr2 = grpp->cr2;
if (grpp->circular) {
mode |= STM32_DMA_CR_CIRC; mode |= STM32_DMA_CR_CIRC;
cr2 |= ADC_CR2_CONT;
}
if (adcp->depth > 1) { if (adcp->depth > 1) {
/* If the buffer depth is greater than one then the half transfer interrupt /* If the buffer depth is greater than one then the half transfer interrupt
interrupt is enabled in order to allows streaming processing.*/ interrupt is enabled in order to allows streaming processing.*/
mode |= STM32_DMA_CR_HTIE; mode |= STM32_DMA_CR_HTIE;
n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth;
} }
else
n = (uint32_t)grpp->num_channels;
dmaStreamSetMemory0(adcp->dmastp, adcp->samples); dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
dmaStreamSetTransactionSize(adcp->dmastp, n); dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode); dmaStreamSetMode(adcp->dmastp, mode);
/* ADC setup.*/ /* ADC setup.*/
@ -213,8 +214,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */
adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->SMPR2 = grpp->smpr2;
adcp->adc->SMPR3 = grpp->smpr3; adcp->adc->SMPR3 = grpp->smpr3;
adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_CONT | adcp->adc->CR2 = cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
ADC_CR2_ADON;
adcp->adc->SQR1 = grpp->sqr1; adcp->adc->SQR1 = grpp->sqr1;
adcp->adc->SQR2 = grpp->sqr2; adcp->adc->SQR2 = grpp->sqr2;
adcp->adc->SQR3 = grpp->sqr3; adcp->adc->SQR3 = grpp->sqr3;
@ -225,8 +225,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
while ((adcp->adc->SR & ADC_SR_ADONS) == 0) while ((adcp->adc->SR & ADC_SR_ADONS) == 0)
; ;
/* ADC start by raising ADC_CR2_SWSTART.*/ /* ADC start by raising ADC_CR2_SWSTART.*/
adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | ADC_CR2_DDS | adcp->adc->CR2 = cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | ADC_CR2_DDS |
ADC_CR2_CONT | ADC_CR2_ADON; ADC_CR2_ADON;
} }
/** /**