git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9552 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -210,6 +210,16 @@ static const uint8_t evconf_value[1] = {0x4F};
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#endif
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static const uint8_t flash_status[1] = {(M25Q_READ_DUMMY_CYCLES << 4U) | 0x0FU};
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static const uint8_t flash_status_xip[1] = {(M25Q_READ_DUMMY_CYCLES << 4U) | 0x07U};
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static const uint8_t flash_reset_xip_pattern[50] = {
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0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
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0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
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0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
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0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
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0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
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0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
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0x11, 0x11
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};
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#endif /* M25Q_BUS_MODE != M25Q_BUS_MODE_SPI */
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@ -497,12 +507,31 @@ static void flash_cmd_addr_dummy_receive(M25QDriver *devp,
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QSPI_CFG_ADDR_SIZE_24 |
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QSPI_CFG_DUMMY_CYCLES(dummy) |
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QSPI_CFG_DATA_MODE_FOUR_LINES;
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#endif
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mode.addr = addr;
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mode.alt = 0U;
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qspiReceive(devp->config->qspip, &mode, n, p);
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}
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void flash_xip_reset(M25QDriver *devp) {
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qspi_command_t cmd;
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/* The only mode to generate an odd number of clock cycles is to write
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data on 4 lines in DDR mode.*/
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#if M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI1L
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cmd.cfg = QSPI_CFG_DUMMY_CYCLES(25);
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#elif M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI2L
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cmd.cfg = QSPI_CFG_DUMMY_CYCLES(13);
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#else
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cmd.cfg = QSPI_CFG_CMD(0x11) |
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QSPI_CFG_CMD_MODE_FOUR_LINES |
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QSPI_CFG_DUMMY_CYCLES(8) |
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QSPI_CFG_DATA_MODE_FOUR_LINES;
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#endif
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cmd.addr = 0U;
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cmd.alt = 0U;
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qspiSend(devp->config->qspip, &cmd, 2, flash_reset_xip_pattern);
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}
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#endif /* M25Q_BUS_MODE != M25Q_BUS_MODE_SPI */
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static flash_error_t flash_poll_status(M25QDriver *devp) {
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@ -882,17 +911,25 @@ void m25qStart(M25QDriver *devp, const M25QConfig *config) {
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/* QSPI initialization.*/
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qspiStart(devp->config->qspip, devp->config->qspicfg);
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/* Reading device ID and unique ID.*/
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/* Resetting XIP mode on entry.*/
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flash_xip_reset(devp);
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#if M25Q_SWITCH_WIDTH == TRUE
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/* Attempting a device reset with different bus widths, commands
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shorter than 8 bits are ignored.*/
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qspiCommand(devp->config->qspip, &cmd_reset_enable_1);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_1);
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qspiCommand(devp->config->qspip, &cmd_reset_enable_2);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_2);
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/* If the device is in one bit mode then the following commands are
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rejected because shorter than 8 bits. If the device is in multiple
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bits mode then the comands are accepted and the device is reset to
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one bit mode.*/
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#if M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI4L
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qspiCommand(devp->config->qspip, &cmd_reset_enable_4);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_4);
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#else
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qspiCommand(devp->config->qspip, &cmd_reset_enable_2);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_2);
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#endif
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/* Now the device should be in one bit mode for sure and we perform a
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device reset.*/
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qspiCommand(devp->config->qspip, &cmd_reset_enable_1);
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qspiCommand(devp->config->qspip, &cmd_reset_memory_1);
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#endif
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/* Reading device ID and unique ID.*/
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@ -992,29 +1029,33 @@ void m25qStop(M25QDriver *devp) {
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*
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* @api
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*/
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void m25qMemoryMap(M25QDriver *devp, uint8_t ** addrp) {
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void m25qMemoryMap(M25QDriver *devp, uint8_t **addrp) {
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qspi_command_t cmd;
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/* Activating XIP mode in the device.*/
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flash_cmd(devp, M25Q_CMD_WRITE_ENABLE);
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flash_cmd_send(devp, M25Q_CMD_WRITE_V_CONF_REGISTER,
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1, flash_status_xip);
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/* Putting the QSPI driver in memory mapped mode.*/
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cmd.cfg = QSPI_CFG_CMD(M25Q_CMD_FAST_READ) |
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QSPI_CFG_ADDR_SIZE_24 |
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#if M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI1L
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QSPI_CFG_CMD_MODE_ONE_LINE |
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QSPI_CFG_ADDR_MODE_ONE_LINE |
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QSPI_CFG_ALT_MODE_ONE_LINE |
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QSPI_CFG_DATA_MODE_ONE_LINE |
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#elif M25Q_BUS_MODE == M25Q_BUS_MODE_QSPI2L
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QSPI_CFG_CMD_MODE_TWO_LINES |
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QSPI_CFG_ADDR_MODE_TWO_LINES |
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QSPI_CFG_ALT_MODE_TWO_LINES |
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QSPI_CFG_DATA_MODE_TWO_LINES |
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#else
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QSPI_CFG_CMD_MODE_FOUR_LINES |
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QSPI_CFG_ADDR_MODE_FOUR_LINES |
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QSPI_CFG_ALT_MODE_FOUR_LINES |
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QSPI_CFG_DATA_MODE_FOUR_LINES |
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#endif
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QSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/
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QSPI_CFG_SIOO |
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QSPI_CFG_DUMMY_CYCLES(M25Q_READ_DUMMY_CYCLES);
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QSPI_CFG_DUMMY_CYCLES(M25Q_READ_DUMMY_CYCLES - 2);
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qspiMapFlash(devp->config->qspip, &cmd, addrp);
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}
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@ -1029,6 +1070,9 @@ void m25qMemoryMap(M25QDriver *devp, uint8_t ** addrp) {
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void m25qMemoryUnmap(M25QDriver *devp) {
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qspiUnmapFlash(devp->config->qspip);
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/* Resetting XIP mode.*/
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flash_xip_reset(devp);
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}
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#endif /* QSPI_SUPPORTS_MEMMAP == TRUE */
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#endif /* M25Q_BUS_MODE != M25Q_BUS_MODE_SPI */
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File diff suppressed because one or more lines are too long
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@ -79,6 +79,7 @@ static THD_FUNCTION(Thread1, arg) {
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*/
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int main(void) {
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flash_error_t err;
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uint8_t *addr;
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/*
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* System initializations.
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@ -127,6 +128,12 @@ int main(void) {
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if (err != FLASH_ERROR_VERIFY)
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chSysHalt("verify non-erase error");
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/* Memory mapping the device.*/
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m25qMemoryMap(&m25q, &addr);
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/* Unmapping the device.*/
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m25qMemoryUnmap(&m25q);
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/* Reading it back.*/
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err = flashRead(&m25q, 0, buffer, 128);
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if (err != FLASH_NO_ERROR)
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