git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1260 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -26,9 +26,8 @@
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#include <ch.h>
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#include <ch.h>
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#include <serial.h>
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#include <serial.h>
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#include <nvic.h>
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#include "nvic.h"
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#include <board.h>
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#include "board.h"
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#if USE_STM32_USART1 || defined(__DOXYGEN__)
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#if USE_STM32_USART1 || defined(__DOXYGEN__)
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/** @brief USART1 serial driver identifier.*/
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/** @brief USART1 serial driver identifier.*/
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@ -55,7 +55,9 @@ static void spi_stop(SPIDriver *spip, msg_t msg) {
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/* Stops SPI operations.*/
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/* Stops SPI operations.*/
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spip->spd_spi->CR1 &= ~SPI_CR1_SPE;
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spip->spd_spi->CR1 &= ~SPI_CR1_SPE;
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chSysLockFromIsr();
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chSchReadyI(spip->spd_thread)->p_msg = msg;
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chSchReadyI(spip->spd_thread)->p_msg = msg;
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chSysUnlockFromIsr();
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}
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}
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static void dma_start(SPIDriver *spip, size_t n, void *rxbuf, void *txbuf) {
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static void dma_start(SPIDriver *spip, size_t n, void *rxbuf, void *txbuf) {
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@ -75,6 +77,10 @@ static void dma_start(SPIDriver *spip, size_t n, void *rxbuf, void *txbuf) {
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spip->spd_dmatx->CMAR = (uint32_t)txbuf;
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spip->spd_dmatx->CMAR = (uint32_t)txbuf;
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spip->spd_dmatx->CNDTR = (uint32_t)n;
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spip->spd_dmatx->CNDTR = (uint32_t)n;
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spip->spd_dmatx->CCR |= ccr;
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spip->spd_dmatx->CCR |= ccr;
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/* DMAs start.*/
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spip->spd_dmarx->CCR |= DMA_CCR1_EN;
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spip->spd_dmatx->CCR |= DMA_CCR1_EN;
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}
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}
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static msg_t spi_start_wait(SPIDriver *spip) {
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static msg_t spi_start_wait(SPIDriver *spip) {
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@ -177,7 +183,7 @@ void spi_lld_init(void) {
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SPID1.spd_spi = SPI1;
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SPID1.spd_spi = SPI1;
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SPID1.spd_dmarx = DMA1_Channel2;
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SPID1.spd_dmarx = DMA1_Channel2;
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SPID1.spd_dmatx = DMA1_Channel3;
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SPID1.spd_dmatx = DMA1_Channel3;
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SPID1.spd_dmaprio = SPI1_DMA_PRIORITY << 12;
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SPID1.spd_dmaprio = STM32_SPI1_DMA_PRIORITY << 12;
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GPIOA->CRH = (GPIOA->CRH & 0x000FFFFF) | 0xB4B00000;
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GPIOA->CRH = (GPIOA->CRH & 0x000FFFFF) | 0xB4B00000;
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#endif
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#endif
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@ -187,7 +193,7 @@ void spi_lld_init(void) {
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SPID2.spd_spi = SPI2;
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SPID2.spd_spi = SPI2;
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SPID2.spd_dmarx = DMA1_Channel4;
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SPID2.spd_dmarx = DMA1_Channel4;
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SPID2.spd_dmatx = DMA1_Channel5;
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SPID2.spd_dmatx = DMA1_Channel5;
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SPID2.spd_dmaprio = SPI2_DMA_PRIORITY << 12;
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SPID2.spd_dmaprio = STM32_SPI2_DMA_PRIORITY << 12;
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GPIOB->CRL = (GPIOB->CRL & 0x000FFFFF) | 0xB4B00000;
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GPIOB->CRL = (GPIOB->CRL & 0x000FFFFF) | 0xB4B00000;
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#endif
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#endif
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}
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}
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@ -203,12 +209,16 @@ void spi_lld_start(SPIDriver *spip) {
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if (spip->spd_state == SPI_STOP) {
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if (spip->spd_state == SPI_STOP) {
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#if USE_STM32_SPI1
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#if USE_STM32_SPI1
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if (&SPID1 == spip) {
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if (&SPID1 == spip) {
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NVICEnableVector(DMA1_Channel2_IRQn, STM32_SPI1_IRQ_PRIORITY);
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NVICEnableVector(DMA1_Channel3_IRQn, STM32_SPI1_IRQ_PRIORITY);
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dmaEnable(DMA1_ID);
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dmaEnable(DMA1_ID);
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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}
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}
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#endif
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#endif
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#if USE_STM32_SPI2
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#if USE_STM32_SPI2
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if (&SPID2 == spip) {
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if (&SPID2 == spip) {
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NVICEnableVector(DMA1_Channel4_IRQn, STM32_SPI2_IRQ_PRIORITY);
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NVICEnableVector(DMA1_Channel5_IRQn, STM32_SPI2_IRQ_PRIORITY);
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dmaEnable(DMA1_ID);
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dmaEnable(DMA1_ID);
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RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
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RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
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}
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}
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@ -220,18 +230,16 @@ void spi_lld_start(SPIDriver *spip) {
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spip->spd_spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
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spip->spd_spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
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/* DMA setup.*/
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/* DMA setup.*/
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spip->spd_dmarx->CPAR = (uint32_t)&spip->spd_spi->DR;
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spip->spd_dmarx->CPAR = (uint32_t)&spip->spd_spi->DR;
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spip->spd_dmatx->CPAR = (uint32_t)&spip->spd_spi->DR;
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spip->spd_dmatx->CPAR = (uint32_t)&spip->spd_spi->DR;
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/*
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/*
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* If specified in the configuration then emits a pulses train on
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* If specified in the configuration then emits a pulses train on
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* the SPI clock line without asserting any slave.
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* the SPI clock line without asserting any slave.
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*/
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*/
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if (spip->spd_config->spc_initcnt > 0) {
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if (spip->spd_config->spc_initcnt > 0) {
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spip->spd_dmarx->CCR = DMA_CCR1_TCIE |
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spip->spd_dmarx->CCR = DMA_CCR1_TCIE | DMA_CCR1_TEIE;
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DMA_CCR1_TEIE | DMA_CCR1_EN;
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spip->spd_dmatx->CCR = DMA_CCR1_DIR | DMA_CCR1_TEIE;
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spip->spd_dmatx->CCR = DMA_CCR1_DIR |
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DMA_CCR1_TEIE | DMA_CCR1_EN;
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dma_start(spip, (size_t)spip->spd_config->spc_initcnt,
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dma_start(spip, (size_t)spip->spd_config->spc_initcnt,
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&dummyrx, &dummytx);
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&dummyrx, &dummytx);
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(void) spi_start_wait(spip);
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(void) spi_start_wait(spip);
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@ -249,12 +257,16 @@ void spi_lld_stop(SPIDriver *spip) {
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if (spip->spd_state == SPI_READY) {
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if (spip->spd_state == SPI_READY) {
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#if USE_STM32_SPI1
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#if USE_STM32_SPI1
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if (&SPID1 == spip) {
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if (&SPID1 == spip) {
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NVICDisableVector(DMA1_Channel2_IRQn);
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NVICDisableVector(DMA1_Channel3_IRQn);
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dmaDisable(DMA1_ID);
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dmaDisable(DMA1_ID);
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RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
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RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
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}
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}
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#endif
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#endif
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#if USE_STM32_SPI2
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#if USE_STM32_SPI2
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if (&SPID2 == spip) {
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if (&SPID2 == spip) {
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NVICDisableVector(DMA1_Channel4_IRQn);
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NVICDisableVector(DMA1_Channel5_IRQn);
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dmaDisable(DMA1_ID);
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dmaDisable(DMA1_ID);
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RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;
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RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;
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}
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}
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* over the TX channel.
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* over the TX channel.
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*/
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*/
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#if !defined(SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#if !defined(SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define SPI1_DMA_PRIORITY 2
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#define STM32_SPI1_DMA_PRIORITY 2
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#endif
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#endif
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/**
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/**
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* over the TX channel.
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* over the TX channel.
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*/
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*/
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#if !defined(SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#if !defined(SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define SPI2_DMA_PRIORITY 2
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#define STM32_SPI2_DMA_PRIORITY 2
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#endif
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/**
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* @brief SPI1 interrupt priority level setting.
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* @note @p BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
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*/
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#if !defined(STM32_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI1_IRQ_PRIORITY 0xB0
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#endif
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/**
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* @brief SPI2 interrupt priority level setting.
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* @note @p BASEPRI_KERNEL >= @p STM32_SPI2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
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*/
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#if !defined(STM32_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI2_IRQ_PRIORITY 0xB0
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#endif
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#endif
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/*===========================================================================*/
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/*===========================================================================*/
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