I2C. Workaround allowing to read single byte on STM32 platforms except F1x.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.4.x@4554 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -290,31 +290,6 @@ static void i2c_lld_set_opmode(I2CDriver *i2cp) {
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dp->CR1 = regCR1;
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}
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/**
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* @brief Return the last event value from I2C status registers.
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* @details Important but implicit destination of this function is
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* clearing interrupts flags.
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* @note Internal use only.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static uint32_t i2c_get_event(I2CDriver *i2cp) {
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I2C_TypeDef *dp = i2cp->i2c;
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uint16_t regSR1 = dp->SR1;
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uint16_t regSR2 = dp->SR2;
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#if CH_DBG_ENABLE_ASSERTS
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dbgSR1 = regSR1;
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dbgSR2 = regSR2;
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dbgCR1 = dp->CR1;
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dbgCR2 = dp->CR2;
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#endif /* CH_DBG_ENABLE_ASSERTS */
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return (I2C_EV_MASK & (regSR1 | (regSR2 << 16)));
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}
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/**
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* @brief I2C shared ISR code.
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*
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@ -324,11 +299,13 @@ static uint32_t i2c_get_event(I2CDriver *i2cp) {
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*/
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static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
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I2C_TypeDef *dp = i2cp->i2c;
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uint32_t regSR = dp->SR2;
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uint32_t event = dp->SR1;
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/* Interrupts are disabled just before dmaStreamEnable() because there
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is no need of interrupts until next transaction begin. All the work is
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done by the DMA.*/
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switch (i2c_get_event(i2cp)) {
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switch (I2C_EV_MASK & (event | (regSR << 16))) {
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case I2C_EV5_MASTER_MODE_SELECT:
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dp->DR = i2cp->addr;
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break;
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@ -336,6 +313,8 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
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dp->CR2 &= ~I2C_CR2_ITEVTEN;
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dmaStreamEnable(i2cp->dmarx);
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dp->CR2 |= I2C_CR2_LAST; /* Needed in receiver mode. */
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if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2)
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dp->CR1 &= ~I2C_CR1_ACK;
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break;
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case I2C_EV6_MASTER_TRA_MODE_SELECTED:
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dp->CR2 &= ~I2C_CR2_ITEVTEN;
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@ -356,6 +335,9 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
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default:
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break;
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}
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/* Clear ADDR flag. */
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if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10))
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(void)dp->SR2;
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}
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/**
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@ -786,7 +768,9 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
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I2C_TypeDef *dp = i2cp->i2c;
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VirtualTimer vt;
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#if defined(STM32F1XX)
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chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout");
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#endif
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/* Global timeout for the whole operation.*/
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if (timeout != TIME_INFINITE)
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@ -865,8 +849,10 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
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I2C_TypeDef *dp = i2cp->i2c;
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VirtualTimer vt;
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#if defined(STM32F1XX)
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chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))),
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"i2c_lld_master_transmit_timeout");
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#endif
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/* Global timeout for the whole operation.*/
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if (timeout != TIME_INFINITE)
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@ -101,6 +101,8 @@
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- NEW: Validated CAN driver on STM32F2/F4.
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- Small fixes to the STM32F4 board files.
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- Various documentation fixes and improvements.
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- NEW: I2C workaround allowing to read single byte on STM32 platforms
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except F1x.
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*** 2.4.1 ***
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- FIX: Fixed inconsistent LPCxxx Internal RC oscillator names (bug 3524138).
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