From 5e3c3d0dcbbfa6b4c901c59c085397f6cde772da Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Mon, 17 May 2021 12:44:07 +0000 Subject: [PATCH] STM32 USARTv2, USARTv3 updated for dynamic clocking. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14387 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../ports/STM32/LLD/USARTv2/hal_serial_lld.c | 34 ++++++++------ .../ports/STM32/LLD/USARTv2/hal_serial_lld.h | 2 - os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c | 32 +++++++------ os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.h | 4 +- os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c | 46 +++++++++++-------- os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h | 4 -- os/hal/ports/STM32/LLD/USARTv3/driver.mk | 4 +- os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c | 33 ++++++------- os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h | 6 +-- readme.txt | 1 + 10 files changed, 86 insertions(+), 80 deletions(-) diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c index 7c89ecf87..849a3ba89 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c @@ -228,26 +228,29 @@ static uint8_t sd_out_buflp1[STM32_SERIAL_LPUART1_OUT_BUF_SIZE]; * * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration + * @param[in] clock base clock for the USART */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config) { +static void usart_init(SerialDriver *sdp, + const SerialConfig *config, + uint32_t clock) { uint32_t brr; USART_TypeDef *u = sdp->usart; /* Baud rate setting.*/ #if STM32_SERIAL_USE_LPUART1 if (sdp == &LPSD1) { - osalDbgAssert((sdp->clock >= config->speed * 3U) && - (sdp->clock <= config->speed * 4096U), + osalDbgAssert((clock >= config->speed * 3U) && + (clock <= config->speed * 4096U), "invalid baud rate vs input clock"); - brr = (uint32_t)(((uint64_t)sdp->clock * 256) / config->speed); + brr = (uint32_t)(((uint64_t)clock * 256) / config->speed); osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value"); } else #endif { - brr = (uint32_t)(sdp->clock / config->speed); + brr = (uint32_t)(clock / config->speed); /* Correcting BRR value when oversampling by 8 instead of 16. Fraction is still 4 bits wide, but only lower 3 bits used. @@ -602,7 +605,6 @@ void sd_lld_init(void) { iqObjectInit(&SD1.iqueue, sd_in_buf1, sizeof sd_in_buf1, NULL, &SD1); oqObjectInit(&SD1.oqueue, sd_out_buf1, sizeof sd_out_buf1, notify1, &SD1); SD1.usart = USART1; - SD1.clock = STM32_USART1CLK; #if !defined(STM32_USART1_SUPPRESS_ISR) && defined(STM32_USART1_NUMBER) nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY); #endif @@ -613,7 +615,6 @@ void sd_lld_init(void) { iqObjectInit(&SD2.iqueue, sd_in_buf2, sizeof sd_in_buf2, NULL, &SD2); oqObjectInit(&SD2.oqueue, sd_out_buf2, sizeof sd_out_buf2, notify2, &SD2); SD2.usart = USART2; - SD2.clock = STM32_USART2CLK; #if !defined(STM32_USART2_SUPPRESS_ISR) && defined(STM32_USART2_NUMBER) nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY); #endif @@ -624,7 +625,6 @@ void sd_lld_init(void) { iqObjectInit(&SD3.iqueue, sd_in_buf3, sizeof sd_in_buf3, NULL, &SD3); oqObjectInit(&SD3.oqueue, sd_out_buf3, sizeof sd_out_buf3, notify3, &SD3); SD3.usart = USART3; - SD3.clock = STM32_USART3CLK; #if !defined(STM32_USART3_SUPPRESS_ISR) && defined(STM32_USART3_NUMBER) nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY); #endif @@ -635,7 +635,6 @@ void sd_lld_init(void) { iqObjectInit(&SD4.iqueue, sd_in_buf4, sizeof sd_in_buf4, NULL, &SD4); oqObjectInit(&SD4.oqueue, sd_out_buf4, sizeof sd_out_buf4, notify4, &SD4); SD4.usart = UART4; - SD4.clock = STM32_UART4CLK; #if !defined(STM32_UART4_SUPPRESS_ISR) && defined(STM32_UART4_NUMBER) nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY); #endif @@ -646,7 +645,6 @@ void sd_lld_init(void) { iqObjectInit(&SD5.iqueue, sd_in_buf5, sizeof sd_in_buf5, NULL, &SD5); oqObjectInit(&SD5.oqueue, sd_out_buf5, sizeof sd_out_buf5, notify5, &SD5); SD5.usart = UART5; - SD5.clock = STM32_UART5CLK; #if !defined(STM32_UART5_SUPPRESS_ISR) && defined(STM32_UART5_NUMBER) nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY); #endif @@ -657,7 +655,6 @@ void sd_lld_init(void) { iqObjectInit(&SD6.iqueue, sd_in_buf6, sizeof sd_in_buf6, NULL, &SD6); oqObjectInit(&SD6.oqueue, sd_out_buf6, sizeof sd_out_buf6, notify6, &SD6); SD6.usart = USART6; - SD6.clock = STM32_USART6CLK; #if !defined(STM32_USART6_SUPPRESS_ISR) && defined(STM32_USART6_NUMBER) nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY); #endif @@ -668,7 +665,6 @@ void sd_lld_init(void) { iqObjectInit(&SD7.iqueue, sd_in_buf7, sizeof sd_in_buf7, NULL, &SD7); oqObjectInit(&SD7.oqueue, sd_out_buf7, sizeof sd_out_buf7, notify7, &SD7); SD7.usart = UART7; - SD7.clock = STM32_UART7CLK; #if !defined(STM32_UART7_SUPPRESS_ISR) && defined(STM32_UART7_NUMBER) nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY); #endif @@ -679,7 +675,6 @@ void sd_lld_init(void) { iqObjectInit(&SD8.iqueue, sd_in_buf8, sizeof sd_in_buf8, NULL, &SD8); oqObjectInit(&SD8.oqueue, sd_out_buf8, sizeof sd_out_buf8, notify8, &SD8); SD8.usart = UART8; - SD8.clock = STM32_UART8CLK; #if !defined(STM32_UART8_SUPPRESS_ISR) && defined(STM32_UART8_NUMBER) nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY); #endif @@ -690,7 +685,6 @@ void sd_lld_init(void) { iqObjectInit(&LPSD1.iqueue, sd_in_buflp1, sizeof sd_in_buflp1, NULL, &LPSD1); oqObjectInit(&LPSD1.oqueue, sd_out_buflp1, sizeof sd_out_buflp1, notifylp1, &LPSD1); LPSD1.usart = LPUART1; - LPSD1.clock = STM32_LPUART1CLK; #if !defined(STM32_LPUART1_SUPPRESS_ISR) && defined(STM32_LPUART1_NUMBER) nvicEnableVector(STM32_LPUART1_NUMBER, STM32_SERIAL_LPUART1_PRIORITY); #endif @@ -708,6 +702,7 @@ void sd_lld_init(void) { * @notapi */ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + uint32_t clock = 0U; if (config == NULL) config = &default_config; @@ -715,51 +710,60 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { if (sdp->state == SD_STOP) { #if STM32_SERIAL_USE_USART1 if (&SD1 == sdp) { + clock = STM32_USART1CLK; rccEnableUSART1(true); } #endif #if STM32_SERIAL_USE_USART2 if (&SD2 == sdp) { + clock = STM32_USART2CLK; rccEnableUSART2(true); } #endif #if STM32_SERIAL_USE_USART3 if (&SD3 == sdp) { + clock = STM32_USART3CLK; rccEnableUSART3(true); } #endif #if STM32_SERIAL_USE_UART4 if (&SD4 == sdp) { + clock = STM32_UART4CLK; rccEnableUART4(true); } #endif #if STM32_SERIAL_USE_UART5 if (&SD5 == sdp) { + clock = STM32_UART5CLK; rccEnableUART5(true); } #endif #if STM32_SERIAL_USE_USART6 if (&SD6 == sdp) { + clock = STM32_USART6CLK; rccEnableUSART6(true); } #endif #if STM32_SERIAL_USE_UART7 if (&SD7 == sdp) { + clock = STM32_UART7CLK; rccEnableUART7(true); } #endif #if STM32_SERIAL_USE_UART8 if (&SD8 == sdp) { + clock = STM32_UART8CLK; rccEnableUART8(true); } #endif #if STM32_SERIAL_USE_LPUART1 if (&LPSD1 == sdp) { + clock = STM32_LPUART1CLK; rccEnableLPUART1(true); } #endif } - usart_init(sdp, config); + usart_init(sdp, config, clock); } /** diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h index 44ab99899..7ec2572d4 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h @@ -542,8 +542,6 @@ typedef struct { /* End of the mandatory fields.*/ \ /* Pointer to the USART registers block.*/ \ USART_TypeDef *usart; \ - /* Clock frequency for the associated USART/UART.*/ \ - uint32_t clock; \ /* Mask to be applied on received frames.*/ \ uint8_t rxmask; diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c index 25c99536f..3189df2ba 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c @@ -185,8 +185,9 @@ __STATIC_INLINE void usart_enable_tx_end_irq(SIODriver *siop) { * @details This function must be invoked with interrupts disabled. * * @param[in] siop pointer to a @p SIODriver object + * @param[in] clock base clock for the USART */ -__STATIC_INLINE void usart_init(SIODriver *siop) { +__STATIC_INLINE void usart_init(SIODriver *siop, uint32_t clock) { USART_TypeDef *u = siop->usart; uint32_t presc, brr; @@ -197,18 +198,18 @@ __STATIC_INLINE void usart_init(SIODriver *siop) { /* Baud rate setting.*/ #if STM32_SIO_USE_LPUART1 if (siop == &LPSIOD1) { - osalDbgAssert((siop->clock >= siop->config->baud * 3U) && - (siop->clock <= siop->config->baud * 4096U), + osalDbgAssert((clock >= siop->config->baud * 3U) && + (clock <= siop->config->baud * 4096U), "invalid baud rate vs input clock"); - brr = (uint32_t)(((uint64_t)(siop->clock / presc) * (uint64_t)256) / siop->config->baud); + brr = (uint32_t)(((uint64_t)(clock / presc) * (uint64_t)256) / siop->config->baud); osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value"); } else #endif { - brr = (uint32_t)((siop->clock / presc) / siop->config->baud); + brr = (uint32_t)((clock / presc) / siop->config->baud); /* Correcting BRR value when oversampling by 8 instead of 16. Fraction is still 4 bits wide, but only lower 3 bits used. @@ -246,47 +247,38 @@ void sio_lld_init(void) { #if STM32_SIO_USE_USART1 == TRUE sioObjectInit(&SIOD1); SIOD1.usart = USART1; - SIOD1.clock = STM32_USART1CLK; #endif #if STM32_SIO_USE_USART2 == TRUE sioObjectInit(&SIOD2); SIOD2.usart = USART2; - SIOD2.clock = STM32_USART2CLK; #endif #if STM32_SIO_USE_USART3 == TRUE sioObjectInit(&SIOD3); SIOD3.usart = USART3; - SIOD3.clock = STM32_USART3CLK; #endif #if STM32_SIO_USE_UART4 == TRUE sioObjectInit(&SIOD4); SIOD4.usart = UART4; - SIOD4.clock = STM32_UART4CLK; #endif #if STM32_SIO_USE_UART5 == TRUE sioObjectInit(&SIOD5); SIOD5.usart = UART5; - SIOD5.clock = STM32_UART5CLK; #endif #if STM32_SIO_USE_USART6 == TRUE sioObjectInit(&SIOD6); SIOD6.usart = USART6; - SIOD6.clock = STM32_USART6CLK; #endif #if STM32_SIO_USE_UART7 == TRUE sioObjectInit(&SIOD7); SIOD7.usart = UART7; - SIOD7.clock = STM32_UART7CLK; #endif #if STM32_SIO_USE_UART8 == TRUE sioObjectInit(&SIOD8); SIOD8.usart = UART8; - SIOD8.clock = STM32_UART8CLK; #endif #if STM32_SIO_USE_LPUART1 == TRUE sioObjectInit(&LPSIOD1); LPSIOD1.usart = LPUART1; - LPSIOD1.clock = STM32_LPUART1CLK; #endif } @@ -302,6 +294,7 @@ void sio_lld_init(void) { * @notapi */ bool sio_lld_start(SIODriver *siop) { + uint32_t clock = 0U; /* Using the default configuration if the application passed a NULL pointer.*/ @@ -316,54 +309,63 @@ bool sio_lld_start(SIODriver *siop) { } #if STM32_SIO_USE_USART1 == TRUE else if (&SIOD1 == siop) { + clock = STM32_USART1CLK; rccResetUSART1(); rccEnableUSART1(true); } #endif #if STM32_SIO_USE_USART2 == TRUE else if (&SIOD2 == siop) { + clock = STM32_USART2CLK; rccResetUSART2(); rccEnableUSART2(true); } #endif #if STM32_SIO_USE_USART3 == TRUE else if (&SIOD3 == siop) { + clock = STM32_USART3CLK; rccResetUSART3(); rccEnableUSART3(true); } #endif #if STM32_SIO_USE_UART4 == TRUE else if (&SIOD4 == siop) { + clock = STM32_UART4CLK; rccResetUART4(); rccEnableUART4(true); } #endif #if STM32_SIO_USE_UART5 == TRUE else if (&SIOD5 == siop) { + clock = STM32_UART5CLK; rccResetUART5(); rccEnableUART5(true); } #endif #if STM32_SIO_USE_USART6 == TRUE else if (&SIOD6 == siop) { + clock = STM32_USART6CLK; rccResetUSART6(); rccEnableUSART6(true); } #endif #if STM32_SIO_USE_UART7 == TRUE else if (&SIOD7 == siop) { + clock = STM32_UART7CLK; rccResetUART7(); rccEnableUART7(true); } #endif #if STM32_SIO_USE_UART8 == TRUE else if (&SIOD8 == siop) { + clock = STM32_UART8CLK; rccResetUART8(); rccEnableUART8(true); } #endif #if STM32_SIO_USE_LPUART1 == TRUE else if (&LPSIOD1 == siop) { + clock = STM32_LPUART1CLK; rccResetLPUART1(); rccEnableLPUART1(true); } @@ -382,7 +384,7 @@ bool sio_lld_start(SIODriver *siop) { } /* Configures the peripheral.*/ - usart_init(siop); + usart_init(siop, clock); return false; } diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.h b/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.h index d42437f19..2d2b2dd88 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.h @@ -262,9 +262,7 @@ typedef uint32_t sio_events_mask_t; */ #define sio_lld_driver_fields \ /* Pointer to the USARTx registers block.*/ \ - USART_TypeDef *usart; \ - /* USART clock frequency.*/ \ - uint32_t clock + USART_TypeDef *usart /** * @brief Low level fields of the SIO configuration structure. diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c index 37877168a..0effbd132 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c @@ -250,8 +250,9 @@ static void usart_stop(UARTDriver *uartp) { * @details This function must be invoked with interrupts disabled. * * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] clock base clock for the USART */ -static void usart_start(UARTDriver *uartp) { +static void usart_start(UARTDriver *uartp, uint32_t clock) { uint32_t fck; uint32_t cr1; const uint32_t tmo = uartp->config->timeout; @@ -261,7 +262,7 @@ static void usart_start(UARTDriver *uartp) { usart_stop(uartp); /* Baud rate setting.*/ - fck = (uint32_t)(uartp->clock / uartp->config->speed); + fck = (uint32_t)(clock / uartp->config->speed); /* Correcting USARTDIV when oversampling by 8 instead of 16. Fraction is still 4 bits wide, but only lower 3 bits used. @@ -534,7 +535,6 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART1 uartObjectInit(&UARTD1); UARTD1.usart = USART1; - UARTD1.clock = STM32_USART1CLK; UARTD1.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD1.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD1.dmarx = NULL; @@ -547,7 +547,6 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART2 uartObjectInit(&UARTD2); UARTD2.usart = USART2; - UARTD2.clock = STM32_USART2CLK; UARTD2.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD2.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD2.dmarx = NULL; @@ -560,7 +559,6 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART3 uartObjectInit(&UARTD3); UARTD3.usart = USART3; - UARTD3.clock = STM32_USART3CLK; UARTD3.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD3.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD3.dmarx = NULL; @@ -573,7 +571,6 @@ void uart_lld_init(void) { #if STM32_UART_USE_UART4 uartObjectInit(&UARTD4); UARTD4.usart = UART4; - UARTD4.clock = STM32_UART4CLK; UARTD4.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD4.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD4.dmarx = NULL; @@ -586,7 +583,6 @@ void uart_lld_init(void) { #if STM32_UART_USE_UART5 uartObjectInit(&UARTD5); UARTD5.usart = UART5; - UARTD5.clock = STM32_UART5CLK; UARTD5.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD5.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD5.dmarx = NULL; @@ -599,7 +595,6 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART6 uartObjectInit(&UARTD6); UARTD6.usart = USART6; - UARTD6.clock = STM32_USART6CLK; UARTD6.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD6.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD6.dmarx = NULL; @@ -612,7 +607,6 @@ void uart_lld_init(void) { #if STM32_UART_USE_UART7 uartObjectInit(&UARTD7); UARTD7.usart = UART7; - UARTD7.clock = STM32_UART7CLK; UARTD7.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD7.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD7.dmarx = NULL; @@ -625,7 +619,6 @@ void uart_lld_init(void) { #if STM32_UART_USE_UART8 uartObjectInit(&UARTD8); UARTD8.usart = UART8; - UARTD8.clock = STM32_UART8CLK; UARTD8.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD8.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD8.dmarx = NULL; @@ -644,10 +637,15 @@ void uart_lld_init(void) { * @notapi */ void uart_lld_start(UARTDriver *uartp) { + uint32_t clock = 0U; if (uartp->state == UART_STOP) { + + if (false) { + } #if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { + else if (&UARTD1 == uartp) { + clock = STM32_USART1CLK; uartp->dmarx = dmaStreamAllocI(STM32_UART_USART1_RX_DMA_STREAM, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, @@ -672,7 +670,8 @@ void uart_lld_start(UARTDriver *uartp) { #endif #if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { + else if (&UARTD2 == uartp) { + clock = STM32_USART2CLK; uartp->dmarx = dmaStreamAllocI(STM32_UART_USART2_RX_DMA_STREAM, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, @@ -697,7 +696,8 @@ void uart_lld_start(UARTDriver *uartp) { #endif #if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { + else if (&UARTD3 == uartp) { + clock = STM32_USART3CLK; uartp->dmarx = dmaStreamAllocI(STM32_UART_USART3_RX_DMA_STREAM, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, @@ -722,7 +722,8 @@ void uart_lld_start(UARTDriver *uartp) { #endif #if STM32_UART_USE_UART4 - if (&UARTD4 == uartp) { + else if (&UARTD4 == uartp) { + clock = STM32_UART4CLK; uartp->dmarx = dmaStreamAllocI(STM32_UART_UART4_RX_DMA_STREAM, STM32_UART_UART4_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, @@ -747,7 +748,8 @@ void uart_lld_start(UARTDriver *uartp) { #endif #if STM32_UART_USE_UART5 - if (&UARTD5 == uartp) { + else if (&UARTD5 == uartp) { + clock = STM32_UART5CLK; uartp->dmarx = dmaStreamAllocI(STM32_UART_UART5_RX_DMA_STREAM, STM32_UART_UART5_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, @@ -772,7 +774,8 @@ void uart_lld_start(UARTDriver *uartp) { #endif #if STM32_UART_USE_USART6 - if (&UARTD6 == uartp) { + else if (&UARTD6 == uartp) { + clock = STM32_USART6CLK; uartp->dmarx = dmaStreamAllocI(STM32_UART_USART6_RX_DMA_STREAM, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, @@ -797,7 +800,8 @@ void uart_lld_start(UARTDriver *uartp) { #endif #if STM32_UART_USE_UART7 - if (&UARTD7 == uartp) { + else if (&UARTD7 == uartp) { + clock = STM32_UART7CLK; uartp->dmarx = dmaStreamAllocI(STM32_UART_UART7_RX_DMA_STREAM, STM32_UART_UART7_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, @@ -822,7 +826,8 @@ void uart_lld_start(UARTDriver *uartp) { #endif #if STM32_UART_USE_UART8 - if (&UARTD8 == uartp) { + else if (&UARTD8 == uartp) { + clock = STM32_UART8CLK; uartp->dmarx = dmaStreamAllocI(STM32_UART_UART8_RX_DMA_STREAM, STM32_UART_UART8_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, @@ -845,6 +850,9 @@ void uart_lld_start(UARTDriver *uartp) { #endif } #endif + else { + osalDbgAssert(false, "invalid USART instance"); + } /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ @@ -859,7 +867,7 @@ void uart_lld_start(UARTDriver *uartp) { uartp->rxstate = UART_RX_IDLE; uartp->txstate = UART_TX_IDLE; - usart_start(uartp); + usart_start(uartp, clock); } /** diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h index b7cac43d7..aa83b0dac 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h @@ -819,10 +819,6 @@ struct UARTDriver { * @brief Pointer to the USART registers block. */ USART_TypeDef *usart; - /** - * @brief Clock frequency for the associated USART/UART. - */ - uint32_t clock; /** * @brief Receive DMA mode bit mask. */ diff --git a/os/hal/ports/STM32/LLD/USARTv3/driver.mk b/os/hal/ports/STM32/LLD/USARTv3/driver.mk index c647e7455..133818d86 100644 --- a/os/hal/ports/STM32/LLD/USARTv3/driver.mk +++ b/os/hal/ports/STM32/LLD/USARTv3/driver.mk @@ -15,5 +15,5 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c endif PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USART \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2 \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3 + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv3 \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2 diff --git a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c index e42c5317a..601f42b49 100644 --- a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c @@ -193,8 +193,9 @@ __STATIC_INLINE void usart_enable_tx_end_irq(SIODriver *siop) { * @details This function must be invoked with interrupts disabled. * * @param[in] siop pointer to a @p SIODriver object + * @param[in] clock base clock for the USART */ -__STATIC_INLINE void usart_init(SIODriver *siop) { +__STATIC_INLINE void usart_init(SIODriver *siop, uint32_t clock) { USART_TypeDef *u = siop->usart; uint32_t presc, brr; @@ -205,18 +206,18 @@ __STATIC_INLINE void usart_init(SIODriver *siop) { /* Baud rate setting.*/ #if STM32_SIO_USE_LPUART1 if (siop == &LPSIOD1) { - osalDbgAssert((siop->clock >= siop->config->baud * 3U) && - (siop->clock <= siop->config->baud * 4096U), + osalDbgAssert((clock >= siop->config->baud * 3U) && + (clock <= siop->config->baud * 4096U), "invalid baud rate vs input clock"); - brr = (uint32_t)(((uint64_t)(siop->clock / presc) * (uint64_t)256) / siop->config->baud); + brr = (uint32_t)(((uint64_t)(clock / presc) * (uint64_t)256) / siop->config->baud); osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value"); } else #endif { - brr = (uint32_t)((siop->clock / presc) / siop->config->baud); + brr = (uint32_t)((clock / presc) / siop->config->baud); /* Correcting BRR value when oversampling by 8 instead of 16. Fraction is still 4 bits wide, but only lower 3 bits used. @@ -255,49 +256,39 @@ void sio_lld_init(void) { #if STM32_SIO_USE_USART1 == TRUE sioObjectInit(&SIOD1); SIOD1.usart = USART1; - SIOD1.clock = STM32_USART1CLK; #endif #if STM32_SIO_USE_USART2 == TRUE sioObjectInit(&SIOD2); SIOD2.usart = USART2; - SIOD2.clock = STM32_USART2CLK; #endif #if STM32_SIO_USE_USART3 == TRUE sioObjectInit(&SIOD3); SIOD3.usart = USART3; - SIOD3.clock = STM32_USART3CLK; #endif #if STM32_SIO_USE_UART4 == TRUE sioObjectInit(&SIOD4); SIOD4.usart = UART4; - SIOD4.clock = STM32_UART4CLK; #endif #if STM32_SIO_USE_UART5 == TRUE sioObjectInit(&SIOD5); SIOD5.usart = UART5; - SIOD5.clock = STM32_UART5CLK; #endif #if STM32_SIO_USE_USART6 == TRUE sioObjectInit(&SIOD6); SIOD6.usart = USART6; - SIOD6.clock = STM32_USART6CLK; #endif #if STM32_SIO_USE_UART7 == TRUE sioObjectInit(&SIOD7); SIOD7.usart = UART7; - SIOD7.clock = STM32_UART7CLK; #endif #if STM32_SIO_USE_UART8 == TRUE sioObjectInit(&SIOD8); SIOD8.usart = UART8; - SIOD8.clock = STM32_UART8CLK; #endif #if STM32_SIO_USE_LPUART1 == TRUE sioObjectInit(&LPSIOD1); LPSIOD1.usart = LPUART1; - LPSIOD1.clock = STM32_LPUART1CLK; #endif - } /** @@ -311,6 +302,7 @@ void sio_lld_init(void) { * @notapi */ bool sio_lld_start(SIODriver *siop) { + uint32_t clock = 0U; /* Using the default configuration if the application passed a NULL pointer.*/ @@ -325,54 +317,63 @@ bool sio_lld_start(SIODriver *siop) { } #if STM32_SIO_USE_USART1 == TRUE else if (&SIOD1 == siop) { + clock = STM32_USART1CLK; rccResetUSART1(); rccEnableUSART1(true); } #endif #if STM32_SIO_USE_USART2 == TRUE else if (&SIOD2 == siop) { + clock = STM32_USART2CLK; rccResetUSART2(); rccEnableUSART2(true); } #endif #if STM32_SIO_USE_USART3 == TRUE else if (&SIOD3 == siop) { + clock = STM32_USART3CLK; rccResetUSART3(); rccEnableUSART3(true); } #endif #if STM32_SIO_USE_UART4 == TRUE else if (&SIOD4 == siop) { + clock = STM32_UART4CLK; rccResetUART4(); rccEnableUART4(true); } #endif #if STM32_SIO_USE_UART5 == TRUE else if (&SIOD5 == siop) { + clock = STM32_UART5CLK; rccResetUART5(); rccEnableUART5(true); } #endif #if STM32_SIO_USE_USART6 == TRUE else if (&SIOD6 == siop) { + clock = STM32_USART6CLK; rccResetUSART6(); rccEnableUSART6(true); } #endif #if STM32_SIO_USE_UART7 == TRUE else if (&SIOD7 == siop) { + clock = STM32_UART7CLK; rccResetUART7(); rccEnableUART7(true); } #endif #if STM32_SIO_USE_UART8 == TRUE else if (&SIOD8 == siop) { + clock = STM32_UART8CLK; rccResetUART8(); rccEnableUART8(true); } #endif #if STM32_SIO_USE_LPUART1 == TRUE else if (&LPSIOD1 == siop) { + clock = STM32_LPUART1CLK; rccResetLPUART1(); rccEnableLPUART1(true); } @@ -391,7 +392,7 @@ bool sio_lld_start(SIODriver *siop) { } /* Configures the peripheral.*/ - usart_init(siop); + usart_init(siop, clock); return false; } diff --git a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h index 138048253..c039b1f81 100644 --- a/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h @@ -38,7 +38,7 @@ /*===========================================================================*/ /** - * @name PLATFORM configuration options + * @name STM32 configuration options * @{ */ /** @@ -266,9 +266,7 @@ typedef uint32_t sio_events_mask_t; */ #define sio_lld_driver_fields \ /* Pointer to the USARTx registers block.*/ \ - USART_TypeDef *usart; \ - /* USART clock frequency.*/ \ - uint32_t clock + USART_TypeDef *usart /** * @brief Low level fields of the SIO configuration structure. diff --git a/readme.txt b/readme.txt index 3b0efd61e..41be3bcec 100644 --- a/readme.txt +++ b/readme.txt @@ -74,6 +74,7 @@ ***************************************************************************** *** Next *** +- NEW: USARTv2, USARTv3 updated for dynamic clocking. - NEW: Dynamic support implemented for STM32G4xx. - NEW: Dynamic clocks support in HAL. - NEW: Reload feature added to RT virtual timers.