diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 59021971d..c236ddeb8 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -235,7 +235,6 @@ void stm32_clock_init(void) {
 #if STM32_ACTIVATE_PLLSAI
   /* PLLSAI activation.*/
   RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ;
-  RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
   RCC->CR |= RCC_CR_PLLSAION;
 
   /* Waiting for PLL lock.*/
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
index 9d82755b0..a4ba20721 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -246,7 +246,7 @@ void stm32_clock_init(void) {
   /* PLLSAI activation.*/
   RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIQ | STM32_PLLSAIP |
                     STM32_PLLSAIN;
- RCC->CR |= RCC_CR_PLLSAION;
+  RCC->CR |= RCC_CR_PLLSAION;
 
   /* Waiting for PLL lock.*/
   while (!(RCC->CR & RCC_CR_PLLSAIRDY))
diff --git a/readme.txt b/readme.txt
index 587209cbd..3e2c8b605 100644
--- a/readme.txt
+++ b/readme.txt
@@ -73,6 +73,7 @@
 *****************************************************************************
 
 *** 16.1.8 ***
+- HAL: Fixed invalid constant in STM32F4 PLLSAI initialization code (bug #834).
 - HAL: Fixed STM32 OTGv1 number of endpoints (bug #833).
 - HAL: Fixed transaction end problem with STM32 OTGv1 driver (bug #832).
 - HAL: Fixed wrong comment in STM32F7 mcuconf (bug #830).