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More G4 code. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13010 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-09-21 09:33:00 +00:00
parent 884dc81754
commit 5f615f69ce
4 changed files with 2099 additions and 1 deletions
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2
os/hal/ports/STM32/STM32G4xx/hal_lld.h
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@ -1777,7 +1777,7 @@
#include "nvic.h" #include "nvic.h"
#include "stm32_isr.h" #include "stm32_isr.h"
//#include "stm32_dma.h" //#include "stm32_dma.h"
//#include "stm32_exti.h" #include "stm32_exti.h"
#include "stm32_rcc.h" #include "stm32_rcc.h"
#ifdef __cplusplus #ifdef __cplusplus

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os/hal/ports/STM32/STM32G4xx/stm32_isr.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32G4xx/stm32_isr.h
* @brief STM32G4xx ISR handler header.
*
* @addtogroup STM32G4xx_ISR
* @{
*/
#ifndef STM32_ISR_H
#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISRs suppressed in standard drivers
* @{
*/
#define STM32_TIM1_SUPPRESS_ISR
#define STM32_TIM2_SUPPRESS_ISR
#define STM32_TIM3_SUPPRESS_ISR
#define STM32_TIM4_SUPPRESS_ISR
#define STM32_TIM5_SUPPRESS_ISR
#define STM32_TIM6_SUPPRESS_ISR
#define STM32_TIM7_SUPPRESS_ISR
#define STM32_TIM8_SUPPRESS_ISR
#define STM32_TIM15_SUPPRESS_ISR
#define STM32_TIM16_SUPPRESS_ISR
#define STM32_TIM17_SUPPRESS_ISR
#define STM32_TIM20_SUPPRESS_ISR
#define STM32_USART1_SUPPRESS_ISR
#define STM32_USART2_SUPPRESS_ISR
#define STM32_USART3_SUPPRESS_ISR
#define STM32_UART4_SUPPRESS_ISR
#define STM32_UART5_SUPPRESS_ISR
#define STM32_LPUART1_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers remapping
* @{
*/
/*
* ADC unit.
*/
#define STM32_ADC1_HANDLER Vector88
#define STM32_ADC2_HANDLER Vector88
#define STM32_ADC3_HANDLER VectorFC
#define STM32_ADC4_HANDLER Vector134
#define STM32_ADC5_HANDLER Vector138
#define STM32_ADC1_NUMBER 18
#define STM32_ADC2_NUMBER 18
#define STM32_ADC3_NUMBER 47
#define STM32_ADC4_NUMBER 61
#define STM32_ADC5_NUMBER 62
/*
* DMA unit.
*/
#define STM32_DMA1_CH1_HANDLER Vector6C
#define STM32_DMA1_CH2_HANDLER Vector70
#define STM32_DMA1_CH3_HANDLER Vector74
#define STM32_DMA1_CH4_HANDLER Vector78
#define STM32_DMA1_CH5_HANDLER Vector7C
#define STM32_DMA1_CH6_HANDLER Vector80
#define STM32_DMA1_CH7_HANDLER Vector84
#define STM32_DMA1_CH8_HANDLER Vector1B0
#define STM32_DMA2_CH1_HANDLER Vector120
#define STM32_DMA2_CH2_HANDLER Vector124
#define STM32_DMA2_CH3_HANDLER Vector128
#define STM32_DMA2_CH4_HANDLER Vector12C
#define STM32_DMA2_CH5_HANDLER Vector130
#define STM32_DMA2_CH6_HANDLER Vector1B4
#define STM32_DMA2_CH7_HANDLER Vector1B8
#define STM32_DMA2_CH8_HANDLER Vector1BC
#define STM32_DMA1_CH1_NUMBER 11
#define STM32_DMA1_CH2_NUMBER 12
#define STM32_DMA1_CH3_NUMBER 13
#define STM32_DMA1_CH4_NUMBER 14
#define STM32_DMA1_CH5_NUMBER 15
#define STM32_DMA1_CH6_NUMBER 16
#define STM32_DMA1_CH7_NUMBER 17
#define STM32_DMA1_CH8_NUMBER 96
#define STM32_DMA2_CH1_NUMBER 56
#define STM32_DMA2_CH2_NUMBER 57
#define STM32_DMA2_CH3_NUMBER 58
#define STM32_DMA2_CH4_NUMBER 59
#define STM32_DMA2_CH5_NUMBER 60
#define STM32_DMA2_CH6_NUMBER 97
#define STM32_DMA2_CH7_NUMBER 98
#define STM32_DMA2_CH7_NUMBER 99
/*
* EXTI unit.
*/
#define STM32_EXTI_LINE0_HANDLER Vector58
#define STM32_EXTI_LINE1_HANDLER Vector5C
#define STM32_EXTI_LINE2_HANDLER Vector60
#define STM32_EXTI_LINE3_HANDLER Vector64
#define STM32_EXTI_LINE4_HANDLER Vector68
#define STM32_EXTI_LINE5_9_HANDLER Vector9C
#define STM32_EXTI_LINE10_15_HANDLER VectorE0
#define STM32_EXTI_LINE164041HANDLER Vector44
#define STM32_EXTI_LINE17_HANDLER VectorE4
#define STM32_EXTI_LINE19_HANDLER Vector48
#define STM32_EXTI_LINE20_HANDLER Vector4C
#define STM32_EXTI_LINE212229_HANDLER Vector140
#define STM32_EXTI_LINE303132_HANDLER Vector144
#define STM32_EXTI_LINE33_HANDLER Vector148
#define STM32_EXTI_LINE0_NUMBER 6
#define STM32_EXTI_LINE1_NUMBER 7
#define STM32_EXTI_LINE2_NUMBER 8
#define STM32_EXTI_LINE3_NUMBER 9
#define STM32_EXTI_LINE4_NUMBER 10
#define STM32_EXTI_LINE5_9_NUMBER 23
#define STM32_EXTI_LINE10_15_NUMBER 40
#define STM32_EXTI_LINE164041_NUMBER 1
#define STM32_EXTI_LINE17_NUMBER 41
#define STM32_EXTI_LINE19_NUMBER 2
#define STM32_EXTI_LINE20_NUMBER 3
#define STM32_EXTI_LINE212229_NUMBER 64
#define STM32_EXTI_LINE303132_NUMBER 65
#define STM32_EXTI_LINE33_NUMBER 66
/*
* I2C units.
*/
#define STM32_I2C1_EVENT_HANDLER VectorBC
#define STM32_I2C1_ERROR_HANDLER VectorC0
#define STM32_I2C2_EVENT_HANDLER VectorC4
#define STM32_I2C2_ERROR_HANDLER VectorC8
#define STM32_I2C3_EVENT_HANDLER Vector1A0
#define STM32_I2C3_ERROR_HANDLER Vector1A4
#define STM32_I2C4_EVENT_HANDLER Vector188
#define STM32_I2C4_ERROR_HANDLER Vector18C
#define STM32_I2C1_EVENT_NUMBER 31
#define STM32_I2C1_ERROR_NUMBER 32
#define STM32_I2C2_EVENT_NUMBER 33
#define STM32_I2C2_ERROR_NUMBER 34
#define STM32_I2C3_EVENT_NUMBER 92
#define STM32_I2C3_ERROR_NUMBER 93
#define STM32_I2C4_EVENT_NUMBER 82
#define STM32_I2C4_ERROR_NUMBER 83
/*
* TIM units.
*/
#define STM32_TIM1_BRK_TIM15_HANDLER VectorA0
#define STM32_TIM1_UP_TIM16_HANDLER VectorA4
#define STM32_TIM1_TRGCO_TIM17_HANDLER VectorA8
#define STM32_TIM1_CC_HANDLER VectorAC
#define STM32_TIM2_HANDLER VectorB0
#define STM32_TIM3_HANDLER VectorB4
#define STM32_TIM4_HANDLER VectorB8
#define STM32_TIM5_HANDLER Vector108
#define STM32_TIM6_HANDLER Vector118
#define STM32_TIM7_HANDLER Vector11C
#define STM32_TIM8_BRK_HANDLER VectorEC
#define STM32_TIM8_UP_HANDLER VectorF0
#define STM32_TIM8_TRGCO_HANDLER VectorF4
#define STM32_TIM8_CC_HANDLER VectorF8
#define STM32_TIM20_BRK_HANDLER Vector174
#define STM32_TIM20_UP_HANDLER Vector178
#define STM32_TIM20_TRGCO_HANDLER Vector17C
#define STM32_TIM20_CC_HANDLER Vector180
#define STM32_TIM1_BRK_TIM15_NUMBER 24
#define STM32_TIM1_UP_TIM16_NUMBER 25
#define STM32_TIM1_TRGCO_TIM17_NUMBER 26
#define STM32_TIM1_CC_NUMBER 27
#define STM32_TIM2_NUMBER 28
#define STM32_TIM3_NUMBER 29
#define STM32_TIM4_NUMBER 30
#define STM32_TIM5_NUMBER 50
#define STM32_TIM6_NUMBER 54
#define STM32_TIM7_NUMBER 55
#define STM32_TIM8_BRK_NUMBER 43
#define STM32_TIM8_UP_NUMBER 44
#define STM32_TIM8_TRGCO_NUMBER 45
#define STM32_TIM8_CC_NUMBER 46
#define STM32_TIM20_BRK_NUMBER 77
#define STM32_TIM20_UP_NUMBER 78
#define STM32_TIM20_TRGCO_NUMBER 79
#define STM32_TIM20_CC_NUMBER 80
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER VectorD4
#define STM32_USART2_HANDLER VectorD8
#define STM32_USART3_HANDLER VectorDC
#define STM32_UART4_HANDLER Vector110
#define STM32_UART5_HANDLER Vector114
#define STM32_LPUART1_HANDLER Vector19C
#define STM32_USART1_NUMBER 37
#define STM32_USART2_NUMBER 38
#define STM32_USART3_NUMBER 39
#define STM32_UART4_NUMBER 52
#define STM32_UART5_NUMBER 53
#define STM32_LPUART1_NUMBER 91
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0..1 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI0_1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI0_1_PRIORITY 3
#endif
/**
* @brief EXTI2..3 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI2_3_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI2_3_PRIORITY 3
#endif
/**
* @brief EXTI4..15 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI4_15_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI4_15_PRIORITY 3
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI16_40_41_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI16_40_41_PRIORITY 3
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI17_PRIORITY 3
#endif
/**
* @brief EXTI19 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI19_PRIORITY 3
#endif
/**
* @brief EXTI20 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI20_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI20_PRIORITY 3
#endif
/**
* @brief EXTI21, 22, 29 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI21_22_29_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI21_22_29_PRIORITY 3
#endif
/**
* @brief EXTI30, 31, 32 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI30_31_32_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI30_31_32_PRIORITY 3
#endif
/**
* @brief TIM1-BRK, TIM15 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
#endif
/**
* @brief TIM1-UP, TIM16 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_TIM1_UP_TIM16_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
#endif
/**
* @brief TIM1-TRG-COM, TIM17 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
#endif
/**
* @brief TIM1-CC interrupt priority level setting.
*/
#if !defined(STM32_IRQ_TIM1_CC_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#endif
/**
* @brief USART1 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_USART1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_USART1_PRIORITY 3
#endif
/**
* @brief USART2 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_USART2_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_USART2_PRIORITY 3
#endif
/**
* @brief USART3 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_USART3_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_USART3_PRIORITY 3
#endif
/**
* @brief UART4 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_UART4_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_UART4_PRIORITY 3
#endif
/**
* @brief UART5 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_UART5_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_UART5_PRIORITY 3
#endif
/**
* @brief LPUART1 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_LPUART1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_LPUART1_PRIORITY 3
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* IRQ priority checks.*/
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_1_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_3_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_3_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_15_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_15_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_40_41_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_40_41_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI19_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI19_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI20_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI20_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_22_29_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_22_29_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_40_41_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_40_41_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_USART1_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART2_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_USART2_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_USART3_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_USART3_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_UART4_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_UART4_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_UART5_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_UART5_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_LPUART1_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_LPUART1_PRIORITY"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void irqInit(void);
void irqDeinit(void);
#ifdef __cplusplus
}
#endif
#endif /* STM32_ISR_H */
/** @} */

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os/hal/ports/STM32/STM32G4xx/stm32_rcc.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32L4xx+/stm32_registry.h
* @brief STM32L4xx+ capabilities registry.
*
* @addtogroup HAL
* @{
*/
#ifndef STM32_REGISTRY_H
#define STM32_REGISTRY_H
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
* @name STM32L4xx+ capabilities
* @{
*/
/*===========================================================================*/
/* Common. */
/*===========================================================================*/
/* RNG attributes.*/
#define STM32_HAS_RNG1 TRUE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_STORAGE_SIZE 128
#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
#define STM32_RTC_WKUP_HANDLER Vector4C
#define STM32_RTC_ALARM_HANDLER VectorE4
#define STM32_RTC_TAMP_STAMP_NUMBER 2
#define STM32_RTC_WKUP_NUMBER 3
#define STM32_RTC_ALARM_NUMBER 41
#define STM32_RTC_ALARM_EXTI 18
#define STM32_RTC_TAMP_STAMP_EXTI 19
#define STM32_RTC_WKUP_EXTI 20
#define STM32_RTC_IRQ_ENABLE() do { \
nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
} while (false)
#if defined(STM32G441xx) || defined(STM32G483xx) || defined(STM32G484xx) || \
defined(__DOXYGEN__)
#define STM32_HAS_HASH1 TRUE
#define STM32_HAS_CRYP1 TRUE
#else
#define STM32_HAS_HASH1 FALSE
#define STM32_HAS_CRYP1 FALSE
#endif
/*===========================================================================*/
/* STM32G474xx, STM32G484xx. */
/*===========================================================================*/
#if defined(STM32G474xx) || defined(STM32G484xx) || \
defined(__DOXYGEN__)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
#define STM32_HAS_ADC3 TRUE
#define STM32_HAS_ADC4 TRUE
#define STM32_HAS_ADC5 TRUE
/* CAN attributes.*/
#define STM32_HAS_CAN1 FALSE
#define STM32_HAS_CAN2 FALSE
#define STM32_HAS_CAN3 FALSE
/* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 TRUE
#define STM32_HAS_DAC1_CH2 TRUE
#define STM32_HAS_DAC2_CH1 TRUE
#define STM32_HAS_DAC2_CH2 TRUE
#define STM32_HAS_DAC3_CH1 TRUE
#define STM32_HAS_DAC3_CH2 TRUE
#define STM32_HAS_DAC4_CH1 TRUE
#define STM32_HAS_DAC4_CH2 TRUE
/* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_DMAMUX TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 8
#define STM32_DMA2_NUM_CHANNELS 8
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 41
#define STM32_EXTI_IMR1_MASK 0x1F840000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFCF3U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 2
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE
#define STM32_HAS_GPIOD TRUE
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_GPIOI FALSE
#define STM32_HAS_GPIOJ FALSE
#define STM32_HAS_GPIOK FALSE
#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
RCC_AHB2ENR_GPIOBEN | \
RCC_AHB2ENR_GPIOCEN | \
RCC_AHB2ENR_GPIODEN | \
RCC_AHB2ENR_GPIOEEN | \
RCC_AHB2ENR_GPIOFEN | \
RCC_AHB2ENR_GPIOGEN)
/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
#define STM32_HAS_I2C3 TRUE
#define STM32_HAS_I2C4 TRUE
/* OCTOSPI attributes.*/
#define STM32_HAS_OCTOSPI1 FALSE
#define STM32_HAS_OCTOSPI2 FALSE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 FALSE
#define STM32_HAS_SDMMC2 FALSE
/* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_HAS_SPI4 TRUE
#define STM32_SPI4_SUPPORTS_I2S FALSE
#define STM32_HAS_SPI5 FALSE
#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 6
#define STM32_HAS_TIM1 TRUE
#define STM32_TIM1_IS_32BITS FALSE
#define STM32_TIM1_CHANNELS 6
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS TRUE
#define STM32_TIM2_CHANNELS 4
#define STM32_HAS_TIM3 TRUE
#define STM32_TIM3_IS_32BITS FALSE
#define STM32_TIM3_CHANNELS 4
#define STM32_HAS_TIM4 TRUE
#define STM32_TIM4_IS_32BITS FALSE
#define STM32_TIM4_CHANNELS 4
#define STM32_HAS_TIM5 TRUE
#define STM32_TIM5_IS_32BITS TRUE
#define STM32_TIM5_CHANNELS 4
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
#define STM32_HAS_TIM7 TRUE
#define STM32_TIM7_IS_32BITS FALSE
#define STM32_TIM7_CHANNELS 0
#define STM32_HAS_TIM8 TRUE
#define STM32_TIM8_IS_32BITS FALSE
#define STM32_TIM8_CHANNELS 6
#define STM32_HAS_TIM15 TRUE
#define STM32_TIM15_IS_32BITS FALSE
#define STM32_TIM15_CHANNELS 2
#define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM20 TRUE
#define STM32_TIM20_IS_32BITS FALSE
#define STM32_TIM20_CHANNELS 6
#define STM32_HAS_TIM9 FALSE
#define STM32_HAS_TIM10 FALSE
#define STM32_HAS_TIM11 FALSE
#define STM32_HAS_TIM12 FALSE
#define STM32_HAS_TIM13 FALSE
#define STM32_HAS_TIM14 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
#define STM32_HAS_TIM21 FALSE
#define STM32_HAS_TIM22 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_HAS_USART2 TRUE
#define STM32_HAS_USART3 TRUE
#define STM32_HAS_UART4 TRUE
#define STM32_HAS_UART5 TRUE
#define STM32_HAS_LPUART1 TRUE
#define STM32_HAS_USART6 FALSE
#define STM32_HAS_UART7 FALSE
#define STM32_HAS_UART8 FALSE
/* OTG/USB attributes.*/
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
#define STM32_HAS_USB TRUE
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
#define STM32_USB_PMA_SIZE 1024
#define STM32_USB_HAS_BCDR TRUE
/* IWDG attributes.*/
#define STM32_HAS_IWDG TRUE
#define STM32_IWDG_IS_WINDOWED TRUE
/* LTDC attributes.*/
#define STM32_HAS_LTDC FALSE
/* DMA2D attributes.*/
#define STM32_HAS_DMA2D FALSE
/* FSMC attributes.*/
#define STM32_HAS_FSMC FALSE
/* CRC attributes.*/
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE
/* DCMI attributes.*/
#define STM32_HAS_DCMI FALSE
#endif /* defined(STM32G474xx) || defined(STM32G484xx) */
/** @} */
#endif /* STM32_REGISTRY_H */
/** @} */