andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1813 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-03-30 15:22:13 +00:00
parent 8a9ecf55f7
commit 5fa5b9ef56
2 changed files with 41 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
os/ports/GCC/ARMCMx/chcore.c
View File

@ -104,7 +104,7 @@ void _port_switch_from_irq(void) {
"pop {pc}"); "pop {pc}");
} }
#if CORTEX_MODEL == CORTEX_M0 #if defined(CH_ARCHITECTURE_ARM_v6M)
#define PUSH_CONTEXT(sp) { \ #define PUSH_CONTEXT(sp) { \
asm volatile ("push {r4, r5, r6, r7, lr} \n\t" \ asm volatile ("push {r4, r5, r6, r7, lr} \n\t" \
"mov r4, r8 \n\t" \ "mov r4, r8 \n\t" \
@ -122,8 +122,17 @@ void _port_switch_from_irq(void) {
"mov r11, r7 \n\t" \ "mov r11, r7 \n\t" \
"pop {r4, r5, r6, r7, pc}" : : "r" (sp)); \ "pop {r4, r5, r6, r7, pc}" : : "r" (sp)); \
} }
#else /* CORTEX_MODEL != CORTEX_M0 */ #elif defined(CH_ARCHITECTURE_ARM_v7M)
#endif /* CORTEX_MODEL != CORTEX_M0 */ #define PUSH_CONTEXT(sp) { \
asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr} \n\t"); \
}
#define POP_CONTEXT(sp) { \
asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} \n\t" \
: : "r" (sp)); \
}
#else
#endif
/** /**
* @brief Performs a context switch between two threads. * @brief Performs a context switch between two threads.

40
os/ports/GCC/ARMCMx/chcore.h
View File

@ -129,32 +129,36 @@
/* Port exported info. */ /* Port exported info. */
/*===========================================================================*/ /*===========================================================================*/
#if defined(__DOXYGEN__)
/**
* @brief Macro defining the ARM architecture.
*/
#define CH_ARCHITECTURE_ARM_vxm
/** /**
* @brief Name of the implemented architecture. * @brief Name of the implemented architecture.
*/ */
#define CH_ARCHITECTURE_NAME "ARM" #define CH_ARCHITECTURE_NAME "ARMvx-M"
#if defined(__DOXYGEN__)
/**
* @brief Macro defining the ARM Cortex-M3 architecture.
*/
#define CH_ARCHITECTURE_ARMCMx
/** /**
* @brief Name of the architecture variant (optional). * @brief Name of the architecture variant (optional).
*/ */
#define CH_CORE_VARIANT_NAME "Cortex-Mx" #define CH_CORE_VARIANT_NAME "Cortex-Mx"
#elif CORTEX_MODEL == CORTEX_M4 #elif CORTEX_MODEL == CORTEX_M4
#define CH_ARCHITECTURE_ARMCM4 #define CH_ARCHITECTURE_ARM_v7M
#define CH_ARCHITECTURE_NAME "ARMv7-M"
#define CH_CORE_VARIANT_NAME "Cortex-M4" #define CH_CORE_VARIANT_NAME "Cortex-M4"
#elif CORTEX_MODEL == CORTEX_M3 #elif CORTEX_MODEL == CORTEX_M3
#define CH_ARCHITECTURE_ARMCM3 #define CH_ARCHITECTURE_ARM_v7M
#define CH_ARCHITECTURE_NAME "ARMv7-M"
#define CH_CORE_VARIANT_NAME "Cortex-M3" #define CH_CORE_VARIANT_NAME "Cortex-M3"
#elif CORTEX_MODEL == CORTEX_M1 #elif CORTEX_MODEL == CORTEX_M1
#define CH_ARCHITECTURE_ARMCM1 #define CH_ARCHITECTURE_ARM_v6M
#define CH_ARCHITECTURE_NAME "ARMv6-M"
#define CH_CORE_VARIANT_NAME "Cortex-M1" #define CH_CORE_VARIANT_NAME "Cortex-M1"
#elif CORTEX_MODEL == CORTEX_M0 #elif CORTEX_MODEL == CORTEX_M0
#define CH_ARCHITECTURE_ARMCM0 #define CH_ARCHITECTURE_ARM_v6M
#define CH_ARCHITECTURE_NAME "ARMv6-M"
#define CH_CORE_VARIANT_NAME "Cortex-M0" #define CH_CORE_VARIANT_NAME "Cortex-M0"
#endif #endif
@ -210,6 +214,7 @@ struct extctx {
* @details This structure represents the inner stack frame during a context * @details This structure represents the inner stack frame during a context
* switching. * switching.
*/ */
#if defined(CH_ARCHITECTURE_ARM_v6M)
struct intctx { struct intctx {
regarm_t r8; regarm_t r8;
regarm_t r9; regarm_t r9;
@ -221,6 +226,19 @@ struct intctx {
regarm_t r7; regarm_t r7;
regarm_t lr; regarm_t lr;
}; };
#elif defined(CH_ARCHITECTURE_ARM_v7M)
struct intctx {
regarm_t r4;
regarm_t r5;
regarm_t r6;
regarm_t r7;
regarm_t r8;
regarm_t r9;
regarm_t r10;
regarm_t r11;
regarm_t lr;
};
#endif
#endif #endif
#if !defined(__DOXYGEN__) #if !defined(__DOXYGEN__)