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Safer ADC start for STM32F4 and STM32L1. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7677 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2015-02-10 14:57:35 +00:00
parent 6eb46acf16
commit 607e3a4c20
4 changed files with 86 additions and 16 deletions
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23
os/hal/ports/STM32/STM32F4xx/adc_lld.c
View File

@ -317,6 +317,7 @@ void adc_lld_stop(ADCDriver *adcp) {
*/ */
void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode; uint32_t mode;
uint32_t cr2;
const ADCConversionGroup *grpp = adcp->grpp; const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/ /* DMA setup.*/
@ -343,15 +344,23 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adc->SQR2 = grpp->sqr2; adcp->adc->SQR2 = grpp->sqr2;
adcp->adc->SQR3 = grpp->sqr3; adcp->adc->SQR3 = grpp->sqr3;
/* ADC configuration and start, the start is performed using the method /* ADC configuration and start.*/
specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | /* Enforcing the mandatory bits in CR2.*/
ADC_CR2_DDS | ADC_CR2_ADON; cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
/* The start method is different dependign if HW or SW triggered, the
start is performed using the method specified in the CR2 configuration.*/
if ((cr2 & ADC_CR2_SWSTART) != 0) {
/* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
/* Finally enabling ADC_CR2_SWSTART.*/
adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
}
else else
adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | adcp->adc->CR2 = cr2;
ADC_CR2_DDS | ADC_CR2_ADON;
} }
/** /**

23
os/hal/ports/STM32/STM32L1xx/adc_lld.c
View File

@ -200,6 +200,7 @@ void adc_lld_stop(ADCDriver *adcp) {
*/ */
void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode; uint32_t mode;
uint32_t cr2;
const ADCConversionGroup *grpp = adcp->grpp; const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/ /* DMA setup.*/
@ -229,15 +230,23 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
adcp->adc->SQR4 = grpp->sqr4; adcp->adc->SQR4 = grpp->sqr4;
adcp->adc->SQR5 = grpp->sqr5; adcp->adc->SQR5 = grpp->sqr5;
/* ADC configuration and start, the start is performed using the method /* ADC configuration and start.*/
specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | /* Enforcing the mandatory bits in CR2.*/
ADC_CR2_DDS | ADC_CR2_ADON; cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
/* The start method is different dependign if HW or SW triggered, the
start is performed using the method specified in the CR2 configuration.*/
if ((cr2 & ADC_CR2_SWSTART) != 0) {
/* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
/* Finally enabling ADC_CR2_SWSTART.*/
adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
}
else else
adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | adcp->adc->CR2 = cr2;
ADC_CR2_DDS | ADC_CR2_ADON;
} }
/** /**

4
testhal/STM32/STM32F4xx/ADC/debug/STM32F4xx-ADC (OpenOCD, Flash and Run).launch
View File

@ -33,13 +33,13 @@
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<listEntry value="/STM32F4xx-ADC"/> <listEntry value="/STM32F4xx-ADC"/>
</listAttribute> </listAttribute>

52
testhal/STM32/STM32L1xx/ADC/debug/STM32L1xx-ADC (OpenOCD, Flash and Run).launch Normal file
View File

@ -0,0 +1,52 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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