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Updated I2C testhal for STM32F1x. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9174 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Uladzimir Pylinski 2016-03-28 10:32:44 +00:00
parent b11ee36528
commit 60d04bd486
3 changed files with 46 additions and 11 deletions
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2
testhal/STM32/STM32F1xx/I2C/.project
View File

@ -27,7 +27,7 @@
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
<locationURI>CHIBIOS</locationURI>
</link>
</linkedResources>
</projectDescription>

2
testhal/STM32/STM32F1xx/I2C/Makefile
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@ -92,7 +92,7 @@ include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.m
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/platform.mk
include $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_103STK/board.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk

53
testhal/STM32/STM32F1xx/I2C/lis3.c
View File

@ -22,14 +22,20 @@
*/
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include "ch.h"
#include "hal.h"
#include "lis3.h"
/* device I2C address */
#define addr 0b0011101
/* enable single byte read checks. Note: it does not work on STM32F1x */
#define TEST_SINGLE_BYTE_READ TRUE
/* autoincrement bit position. This bit needs to perform reading of
* multiple bytes at one request */
#define AUTO_INCREMENT_BIT (1<<7)
@ -59,7 +65,7 @@ void lis3Start(void){
/* sending */
i2cAcquireBus(&I2CD1);
status = i2cMasterTransmitTimeout(&I2CD1, addr,
accel_tx_data, 4, accel_rx_data, 0, tmo);
accel_tx_data, 4, NULL, 0, tmo);
i2cReleaseBus(&I2CD1);
osalDbgCheck(MSG_OK == status);
@ -68,25 +74,54 @@ void lis3Start(void){
/*
*
*/
#include <math.h>
static void raw2g(uint8_t *raw, float *g) {
int16_t tmp;
for (size_t i=0; i<3; i++){
tmp = raw[i*2] | (raw[i*2+1] << 8);
g[i] = (float)tmp / 16384.0; /* convert raw value to G */
}
}
/*
*
*/
void lis3GetAcc(float *result) {
msg_t status = MSG_OK;
systime_t tmo = MS2ST(4);
size_t i = 0;
int16_t tmp;
/* read in burst mode */
memset(accel_rx_data, 0x55, sizeof(accel_rx_data));
accel_tx_data[0] = ACCEL_OUT_DATA | AUTO_INCREMENT_BIT;
i2cAcquireBus(&I2CD1);
status = i2cMasterTransmitTimeout(&I2CD1, addr,
accel_tx_data, 1, accel_rx_data, 6, tmo);
i2cReleaseBus(&I2CD1);
osalDbgCheck(MSG_OK == status);
raw2g(accel_rx_data, result);
for (i=0; i<3; i++){
tmp = accel_rx_data[i*2] + (accel_rx_data[i*2+1] << 8);
result[i] = tmp;
result[i] /= 16384; /* convert raw value to G */
#if TEST_SINGLE_BYTE_READ
float accel_single_byte_check[3];
const float check_threshold = 0.1;
/* read data byte at a time */
memset(accel_rx_data, 0x55, sizeof(accel_rx_data));
accel_tx_data[0] = ACCEL_OUT_DATA;
i2cAcquireBus(&I2CD1);
for (size_t i=0; i<6; i++) {
status = i2cMasterTransmitTimeout(&I2CD1, addr,
accel_tx_data, 1, &accel_rx_data[i], 1, tmo);
osalDbgCheck(MSG_OK == status);
accel_tx_data[0]++;
}
i2cReleaseBus(&I2CD1);
raw2g(accel_rx_data, accel_single_byte_check);
/* check results */
for (size_t i=0; i<3; i++) {
osalDbgCheck(fabsf(result[i] - accel_single_byte_check[i]) < check_threshold);
}
#endif /* TEST_SINGLE_BYTE_READ */
}