From 62d5bc81ae3fec995ebd43b37be75537abcabfbd Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Mon, 20 Sep 2021 17:10:03 +0000 Subject: [PATCH] More work on MP1 clock tree. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14812 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- demos/STM32/RT-STM32MP157A-DK1/.project | 5 + os/hal/ports/STM32/LLD/RCCv2/driver.mk | 7 + os/hal/ports/STM32/LLD/RCCv2/stm32_pll3.inc | 397 ++++++++++++++++++ os/hal/ports/STM32/STM32MP1xx/hal_lld.h | 115 ++--- os/hal/ports/STM32/STM32MP1xx/platform.mk | 1 + .../ports/STM32/STM32MP1xx/stm32_registry.h | 6 + 6 files changed, 480 insertions(+), 51 deletions(-) create mode 100644 os/hal/ports/STM32/LLD/RCCv2/driver.mk create mode 100644 os/hal/ports/STM32/LLD/RCCv2/stm32_pll3.inc diff --git a/demos/STM32/RT-STM32MP157A-DK1/.project b/demos/STM32/RT-STM32MP157A-DK1/.project index b3a64b0f7..5455a5e6b 100644 --- a/demos/STM32/RT-STM32MP157A-DK1/.project +++ b/demos/STM32/RT-STM32MP157A-DK1/.project @@ -24,6 +24,11 @@ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + board + 2 + CHIBIOS/os/hal/boards/ST_STM32MP157A_DK1 + os 2 diff --git a/os/hal/ports/STM32/LLD/RCCv2/driver.mk b/os/hal/ports/STM32/LLD/RCCv2/driver.mk new file mode 100644 index 000000000..4c988a3fd --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv2/driver.mk @@ -0,0 +1,7 @@ +ifeq ($(USE_SMART_BUILD),yes) +PLATFORMSRC += +else +PLATFORMSRC += +endif + +PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv2 diff --git a/os/hal/ports/STM32/LLD/RCCv2/stm32_pll3.inc b/os/hal/ports/STM32/LLD/RCCv2/stm32_pll3.inc new file mode 100644 index 000000000..1cf7d1ae4 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv2/stm32_pll3.inc @@ -0,0 +1,397 @@ +/* + ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv2/stm32_pll3.inc + * @brief Shared PLL3 handler. + * + * @addtogroup STM32_PLL3_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ +#if !defined(STM32_RCC_HAS_PLL3) +#define STM32_RCC_HAS_PLL3 FALSE +#endif + +#if STM32_RCC_HAS_PLL3 + +/* More checks on registry.*/ +#if !defined(STM32_RCC_PLL3_HAS_P) +#error "STM32_RCC_PLL3_HAS_P not defined in registry" +#endif + +#if !defined(STM32_RCC_PLL3_HAS_Q) +#error "STM32_RCC_PLL3_HAS_Q not defined in registry" +#endif + +#if !defined(STM32_RCC_PLL3_HAS_R) +#error "STM32_RCC_PLL3_HAS_R not defined in registry" +#endif + +/* Checks on configurations.*/ +#if !defined(STM32_PLL3SRC) +#error "STM32_PLL3SRC not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL3DIVM_VALUE) +#error "STM32_PLL3DIVM_VALUE not defined in mcuconf.h" +#endif + +#if !defined(STM32_PLL3DIVN_VALUE) +#error "STM32_PLL3DIVN_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3DIVP_VALUE) +#error "STM32_PLL3DIVP_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL3_HAS_Q && !defined(STM32_PLL3DIVQ_VALUE) +#error "STM32_PLL3DIVQ_VALUE not defined in mcuconf.h" +#endif + +#if STM32_RCC_PLL3_HAS_R && !defined(STM32_PLL3DIVR_VALUE) +#error "STM32_PLL3DIVR_VALUE not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_PLL3INCLK_MAX) +#error "STM32_PLL3INCLK_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3INCLK_MIN) +#error "STM32_PLL3INCLK_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3VCOCLK_MAX) +#error "STM32_PLL3VCOCLK_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3VCOCLK_MIN) +#error "STM32_PLL3VCOCLK_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3PCLK_MAX) +#error "STM32_PLL3PCLK_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3PCLK_MIN) +#error "STM32_PLL3PCLK_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_Q && !defined(STM32_PLL3QCLK_MAX) +#error "STM32_PLL3QCLK_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_Q && !defined(STM32_PLL3QCLK_MIN) +#error "STM32_PLL3QCLK_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_R && !defined(STM32_PLL3RCLK_MAX) +#error "STM32_PLL3RCLK_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_R && !defined(STM32_PLL3RCLK_MIN) +#error "STM32_PLL3RCLK_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3DIVM_MAX) +#error "STM32_PLL3DIVM_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3DIVM_MIN) +#error "STM32_PLL3DIVM_MIN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3DIVN_MAX) +#error "STM32_PLL3DIVN_MAX not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3DIVN_MIN) +#error "STM32_PLL3DIVN_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3DIVP_MAX) +#error "STM32_PLL3DIVP_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3DIVP_MIN) +#error "STM32_PLL3DIVP_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_Q && !defined(STM32_PLL3DIVQ_MAX) +#error "STM32_PLL3DIVQ_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_Q && !defined(STM32_PLL3DIVQ_MIN) +#error "STM32_PLL3DIVQ_MIN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_R && !defined(STM32_PLL3DIVR_MAX) +#error "STM32_PLL3DIVR_MAX not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_R && !defined(STM32_PLL3DIVR_MIN) +#error "STM32_PLL3DIVR_MIN not defined in hal_lld.h" +#endif + +/* Input checks.*/ +#if !defined(STM32_ACTIVATE_PLL3) +#error "STM32_ACTIVATE_PLL3 not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_P && !defined(STM32_PLL3DIVPEN) +#error "STM32_PLL3DIVPEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_Q && !defined(STM32_PLL3DIVQEN) +#error "STM32_PLL3DIVQEN not defined in hal_lld.h" +#endif + +#if STM32_RCC_PLL3_HAS_R && !defined(STM32_PLL3DIVREN) +#error "STM32_PLL3DIVREN not defined in hal_lld.h" +#endif + +#if !defined(STM32_PLL3MCLK) +#error "STM32_PLL3MCLK not defined in hal_lld.h" +#endif + +#if STM32_ACTIVATE_PLL3 && (STM32_PLL3MCLK == 0) +#error "PLL3 activation required but no PLL3 clock selected" +#endif + +/** + * @brief STM32_PLL3DIVM field. + */ +#if ((STM32_PLL3DIVM_VALUE >= STM32_PLL3DIVM_MIN) && \ + (STM32_PLL3DIVM_VALUE <= STM32_PLL3DIVM_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3DIVM ((STM32_PLL3DIVM_VALUE - 1U) << RCC_PLLCFGR_PLL3DIVM_Pos) + +#else +#error "invalid STM32_PLL3DIVM_VALUE value specified" +#endif + +/** + * @brief Clock at the M divider input. + */ +#define STM32_PLL3INCLK (STM32_PLL3MCLK / STM32_PLL3DIVM_VALUE) + +#if (STM32_PLL3INCLK != 0) && \ + ((STM32_PLL3INCLK < STM32_PLL3INCLK_MIN) || (STM32_PLL3INCLK > STM32_PLL3INCLK_MAX)) +#error "STM32_PLL3INCLK outside acceptable range (STM32_PLL3INCLK_MIN...STM32_PLL3INCLK_MAX)" +#endif + +/** + * @brief STM32_PLL3DIVN field. + */ +#if ((STM32_PLL3DIVN_VALUE >= STM32_PLL3DIVN_MIN) && \ + (STM32_PLL3DIVN_VALUE <= STM32_PLL3DIVN_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3DIVN ((STM32_PLL3DIVN_VALUE - 1U) << RCC_PLLCFGR_PLL3DIVN_Pos) + +#else +#error "invalid STM32_PLL3DIVN_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLL3VCOCLK (STM32_PLL3INCLK * STM32_PLL3DIVN_VALUE) + +/* + * PLL VCO frequency range check. + */ +#if STM32_ACTIVATE_PLL3 && \ + ((STM32_PLL3VCOCLK < STM32_PLL3VCOCLK_MIN) || (STM32_PLL3VCOCLK > STM32_PLL3VCOCLK_MAX)) +#error "STM32_PLL3VCOCLK outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/*---------------------------------------------------------------------------*/ +/* P output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL3_HAS_P || defined(__DOXYGEN__) +/** + * @brief STM32_PLL3DIVP field. + */ +#if ((STM32_PLL3DIVP_VALUE >= STM32_PLL3DIVP_MIN) && \ + (STM32_PLL3DIVP_VALUE <= STM32_PLL3DIVP_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3DIVP ((STM32_PLL3DIVP_VALUE - 1) << RCC_PLL3CFGR2_DIVP_Pos) +#else +#error "invalid STM32_PLL3DIVP_VALUE value specified" +#endif + +/** + * @brief PLL3 P output clock frequency. + */ +#define STM32_PLL3_P_CLKOUT (STM32_PLL3VCOCLK / STM32_PLL3DIVP_VALUE) + +/* + * PLL3 P output frequency range check. + */ +#if STM32_ACTIVATE_PLL3 && \ + ((STM32_PLL3_P_CLKOUT < STM32_PLL3PCLK_MIN) || \ + (STM32_PLL3_P_CLKOUT > STM32_PLL3PCLK_MAX)) +#error "STM32_PLL3_P_CLKOUT outside acceptable range (STM32_PLL3PCLK_MIN...STM32_PLL3PCLK_MAX)" +#endif + +#else /* !STM32_RCC_PLL_HAS_P */ +#define STM32_PLL3DIVP 0 +#endif /* !STM32_RCC_PLL_HAS_P */ + +/*---------------------------------------------------------------------------*/ +/* Q output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL3_HAS_Q || defined(__DOXYGEN__) +/** + * @brief STM32_PLL3DIVQ field. + */ +#if ((STM32_PLL3DIVQ_VALUE >= STM32_PLL3DIVQ_MIN) && \ + (STM32_PLL3DIVQ_VALUE <= STM32_PLL3DIVQ_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3DIVQ ((STM32_PLL3DIVQ_VALUE - 1) << RCC_PLL3CFGR2_DIVQ_Pos) +#else +#error "invalid STM32_PLL3DIVQ_VALUE value specified" +#endif + +/** + * @brief PLL3 Q output clock frequency. + */ +#define STM32_PLL3_Q_CLKOUT (STM32_PLL3VCOCLK / STM32_PLL3DIVQ_VALUE) + +/* + * PLL3 Q output frequency range check. + */ +#if STM32_ACTIVATE_PLL3 && \ + ((STM32_PLL3_Q_CLKOUT < STM32_PLL3QCLK_MIN) || \ + (STM32_PLL3_Q_CLKOUT > STM32_PLL3QCLK_MAX)) +#error "STM32_PLL3_Q_CLKOUT outside acceptable range (STM32_PLL3QCLK_MIN...STM32_PLL3QCLK_MAX)" +#endif + +#else /* !STM32_RCC_PLL_HAS_Q */ +#define STM32_PLL3DIVQ 0 +#endif /* !STM32_RCC_PLL_HAS_Q */ + +/*---------------------------------------------------------------------------*/ +/* R output, if present. */ +/*---------------------------------------------------------------------------*/ +#if STM32_RCC_PLL3_HAS_R || defined(__DOXYGEN__) +/** + * @brief STM32_PLL3DIVQ field. + */ +#if ((STM32_PLL3DIVR_VALUE >= STM32_PLL3DIVR_MIN) && \ + (STM32_PLL3DIVR_VALUE <= STM32_PLL3DIVR_MAX)) || \ + defined(__DOXYGEN__) +#define STM32_PLL3DIVR ((STM32_PLL3DIVR_VALUE - 1) << RCC_PLL3CFGR2_DIVR_Pos) +#else +#error "invalid STM32_PLL3DIVR_VALUE value specified" +#endif + +/** + * @brief PLL3 R output clock frequency. + */ +#define STM32_PLL3_R_CLKOUT (STM32_PLL3VCOCLK / STM32_PLL3DIVR_VALUE) + +/* + * PLL3 R output frequency range check. + */ +#if STM32_ACTIVATE_PLL3 && \ + ((STM32_PLL3_R_CLKOUT < STM32_PLL3RCLK_MIN) || \ + (STM32_PLL3_R_CLKOUT > STM32_PLL3RCLK_MAX)) +#error "STM32_PLL3_R_CLKOUT outside acceptable range (STM32_PLL3RCLK_MIN...STM32_PLL3RCLK_MAX)" +#endif + +#else /* !STM32_RCC_PLL_HAS_R */ +#define STM32_PLL3DIVR 0 +#endif /* !STM32_RCC_PLL_HAS_R */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if 0 +__STATIC_INLINE bool pll_not_locked(void) { + + return (bool)((RCC->CR & RCC_CR_PLLRDY) == 0U); +} + +__STATIC_INLINE void pll_wait_lock(void) { + + while (pll_not_locked()) { + /* Waiting for PLL lock.*/ + } +} +#endif + +#endif /* STM32_RCC_HAS_PLL */ + +__STATIC_INLINE void pll_init(void) { + +#if STM32_RCC_HAS_PLL3 +#if STM32_ACTIVATE_PLL3 + /* PLL activation.*/ +#if 0 + RCC->PLLCFGR = STM32_PLLPDIV | STM32_PLLR | + STM32_PLLREN | STM32_PLLQ | + STM32_PLLQEN | STM32_PLLP | + STM32_PLLPEN | STM32_PLLN | + STM32_PLLM | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + + pll_wait_lock(); +#endif +#endif +#endif +} + +__STATIC_INLINE void pll_deinit(void) { + +#if STM32_RCC_HAS_PLL3 +#if STM32_ACTIVATE_PLL3 + /* PLL de-activation.*/ +#if 0 + RCC->PLLCFGR &= ~RCC_CR_PLLON; +#endif +#endif +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32MP1xx/hal_lld.h b/os/hal/ports/STM32/STM32MP1xx/hal_lld.h index a91b0751f..5b17410ce 100644 --- a/os/hal/ports/STM32/STM32MP1xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32MP1xx/hal_lld.h @@ -176,14 +176,14 @@ * @brief PWR MCUCR register initialization value. */ #if !defined(STM32_PWR_MCUCR) || defined(__DOXYGEN__) -#define STM32_PWR_MCUCR XXXXXXXXXXXXXXX +#define STM32_PWR_MCUCR 2222222222 #endif /** * @brief PWR MCUWKUPENR register initialization value. */ #if !defined(STM32_PWR_MCUWKUPENR) || defined(__DOXYGEN__) -#define STM32_PWR_MCUWKUPENR XXXXXXXXXXXXXXX +#define STM32_PWR_MCUWKUPENR 2222222222 #endif /** @@ -214,8 +214,8 @@ * @note The allowed values are 1..64. * @note This initialization is performed only if TZEN=0 or MCKPROT=0. */ -#if !defined(STM32_PLL3M_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL3M_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL3DIVM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL3DIVM_VALUE 3 #endif /** @@ -223,8 +223,8 @@ * @note The allowed values are 25..200. * @note This initialization is performed only if TZEN=0 or MCKPROT=0. */ -#if !defined(STM32_PLL3N_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL3N_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL3DIVN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL3DIVN_VALUE 50 #endif /** @@ -232,8 +232,8 @@ * @note The allowed values are 1..128. * @note This initialization is performed only if TZEN=0 or MCKPROT=0. */ -#if !defined(STM32_PLL3P_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL3P_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL3DIVP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL3DIVP_VALUE 2 #endif /** @@ -241,8 +241,8 @@ * @note The allowed values are 1..128. * @note This initialization is performed only if TZEN=0 or MCKPROT=0. */ -#if !defined(STM32_PLL3Q_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL3Q_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL3DIVQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL3DIVQ_VALUE 4 #endif /** @@ -250,8 +250,8 @@ * @note The allowed values are 1..128. * @note This initialization is performed only if TZEN=0 or MCKPROT=0. */ -#if !defined(STM32_PLL3R_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL3R_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL3DIVR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL3DIVR_VALUE 4 #endif /** @@ -265,40 +265,40 @@ * @brief PLL4 M divider value. * @note The allowed values are 1..64. */ -#if !defined(STM32_PLL4M_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL4M_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL4DIVM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL4DIVM_VALUE 2222222222 #endif /** * @brief PLL4 N multiplier value. * @note The allowed values are 25..200. */ -#if !defined(STM32_PLL4N_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL4N_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL4DIVN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL4DIVN_VALUE 2222222222 #endif /** * @brief PLL4 P divider value or zero if disabled. * @note The allowed values are 1..128. */ -#if !defined(STM32_PLL4P_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL4P_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL4DIVP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL4DIVP_VALUE 2222222222 #endif /** * @brief PLL4 Q divider value. * @note The allowed values are 1..128. */ -#if !defined(STM32_PLL4Q_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL4Q_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL4DIVQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL4DIVQ_VALUE 2222222222 #endif /** * @brief PLL4 R divider value. * @note The allowed values are 1..128. */ -#if !defined(STM32_PLL4R_VALUE) || defined(__DOXYGEN__) -#define STM32_PLL4R_VALUE XXXXXXXXXXXXXXX +#if !defined(STM32_PLL4DIVR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLL4DIVR_VALUE 2222222222 #endif /** @@ -306,7 +306,7 @@ * @note This initialization is performed only if TZEN=0 or MCKPROT=0. */ #if !defined(STM32_MCUDIV) || defined(__DOXYGEN__) -#define STM32_MCUDIV XXXXXXXXXXXXXXX +#define STM32_MCUDIV 2222222222 #endif /** @@ -314,28 +314,28 @@ * @note This initialization is performed only if TZEN=0 or MCKPROT=0. */ #if !defined(STM32_MCUSSRC) || defined(__DOXYGEN__) -#define STM32_MCUSSRC XXXXXXXXXXXXXX +#define STM32_MCUSSRC 2222222222 #endif /** * @brief APB1DIV prescaler setting. */ #if !defined(STM32_APB1DIV) || defined(__DOXYGEN__) -#define STM32_APB1DIV XXXXXXXXXXXXXXX +#define STM32_APB1DIV 2222222222 #endif /** * @brief APB2DIV prescaler setting. */ #if !defined(STM32_APB2DIV) || defined(__DOXYGEN__) -#define STM32_APB2DIV XXXXXXXXXXXXXXX +#define STM32_APB2DIV 2222222222 #endif /** * @brief APB3DIV prescaler setting. */ #if !defined(STM32_APB3DIV) || defined(__DOXYGEN__) -#define STM32_APB3DIV XXXXXXXXXXXXXXX +#define STM32_APB3DIV 2222222222 #endif /** @@ -405,22 +405,32 @@ * @{ */ #define STM32_MCUSS_CK_MAX 209000000 -#define STM32_PLLIN_MAX 16000000 -#define STM32_PLLIN_MIN 4000000 -#define STM32_PLLIN_SD_THRESHOLD 8000000 -#define STM32_BOOST_PLLVCO_MAX 800000000 -#define STM32_BOOST_PLLVCO_MIN 400000000 -#define STM32_BOOST_PLLP_MAX 800000000 -#define STM32_BOOST_PLLP_MIN 3125000 -#define STM32_BOOST_PLLQ_MAX 800000000 -#define STM32_BOOST_PLLQ_MIN 3125000 -#define STM32_BOOST_PLLR_MAX 800000000 -#define STM32_BOOST_PLLR_MIN 3125000 -#define STM32_BOOST_PCLK1_MAX 104500000 -#define STM32_BOOST_PCLK2_MAX 104500000 -#define STM32_BOOST_PCLK3_MAX 104500000 -#define STM32_BOOST_ADCCLK_BOOST_MAX 36000000 -#define STM32_BOOST_ADCCLK_NOBOOST_MAX 20000000 +#define STM32_PLL3INCLK_MAX 16000000 +#define STM32_PLL3INCLK_MIN 4000000 +#define STM32_PLL3INCLK_SD_MIN 8000000 +#define STM32_PLL3VCOCLK_MAX 800000000 +#define STM32_PLL3VCOCLK_MIN 400000000 +#define STM32_PLL3PCLK_MAX 800000000 +#define STM32_PLL3PCLK_MIN 3125000 +#define STM32_PLL3QCLK_MAX 800000000 +#define STM32_PLL3QCLK_MIN 3125000 +#define STM32_PLL3RCLK_MAX 800000000 +#define STM32_PLL3RCLK_MIN 3125000 +#define STM32_PLL3DIVM_MAX 64 +#define STM32_PLL3DIVM_MIN 1 +#define STM32_PLL3DIVN_MAX 200 +#define STM32_PLL3DIVN_MIN 25 +#define STM32_PLL3DIVP_MAX 128 +#define STM32_PLL3DIVP_MIN 1 +#define STM32_PLL3DIVQ_MAX 128 +#define STM32_PLL3DIVQ_MIN 1 +#define STM32_PLL3DIVR_MAX 128 +#define STM32_PLL3DIVR_MIN 1 +#define STM32_PCLK1_MAX 104500000 +#define STM32_PCLK2_MAX 104500000 +#define STM32_PCLK3_MAX 104500000 +#define STM32_ADCCLK_BOOST_MAX 36000000 +#define STM32_ADCCLK_NOBOOST_MAX 20000000 /** @} */ /* External oscillator settings check.*/ @@ -459,16 +469,16 @@ * @brief PLL3 input clock frequency. */ #if (STM32_PLL3SRC == STM32_PLL3SRC_HSI) || defined(__DOXYGEN__) - #define STM32_PLL3CLKIN (STM32_HSICLK / STM32_PLL3M_VALUE) + #define STM32_PLL3MCLK STM32_HSICLK #elif STM32_PLL3SRC == STM32_PLL3SRC_HSE - #define STM32_PLL3CLKIN (STM32_HSECLK / STM32_PLL3M_VALUE) + #define STM32_PLL3MCLK STM32_HSECLK #elif STM32_PLL3SRC == STM32_PLL3SRC_CSI - #define STM32_PLL3CLKIN (STM32_CSICLK / STM32_PLL3M_VALUE) + #define STM32_PLL3MCLK STM32_CSICLK #elif STM32_PLL3SRC == STM32_PLL3SRC_NOCLOCK - #define STM32_PLL3CLKIN 0 + #define STM32_PLL3MCLK 0 #else #error "invalid STM32_PLL3SRC value specified" @@ -529,19 +539,19 @@ * @brief PLL4 input clock frequency. */ #if (STM32_PLL4SRC == STM32_PLL4SRC_HSI) || defined(__DOXYGEN__) - #define STM32_PLL4CLKIN (STM32_HSICLK / STM32_PLL4M_VALUE) + #define STM32_PLL4MCLK STM32_HSICLK #elif STM32_PLL4SRC == STM32_PLL4SRC_HSE - #define STM32_PLL4CLKIN (STM32_HSECLK / STM32_PLL4M_VALUE) + #define STM32_PLL4MCLK STM32_HSECLK #elif STM32_PLL4SRC == STM32_PLL4SRC_CSI - #define STM32_PLL4CLKIN (STM32_CSICLK / STM32_PLL4M_VALUE) + #define STM32_PLL4MCLK STM32_CSICLK #elif STM32_PLL4SRC == STM32_PLL4SRC_I2S_CKIN #if STM32_I2S_CKIN_VALUE <= 0 #error "STM32_I2S_CKIN_VALUE is zero but it is selected as PLL4 input" #endif - #define STM32_PLL4CLKIN (STM32_I2S_CKIN_VALUE / STM32_PLL4M_VALUE) + #define STM32_PLL4MCLK STM32_I2S_CKIN_VALUE #else #error "invalid STM32_PLL4SRC value specified" @@ -598,6 +608,9 @@ #define STM32_PLL4DIVREN (0 << 6) #endif +/* Inclusion of PLL-related checks and calculations.*/ +#include + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32MP1xx/platform.mk b/os/hal/ports/STM32/STM32MP1xx/platform.mk index c617f4ad3..d69fa29de 100644 --- a/os/hal/ports/STM32/STM32MP1xx/platform.mk +++ b/os/hal/ports/STM32/STM32MP1xx/platform.mk @@ -26,6 +26,7 @@ endif # Drivers compatible with the platform. include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk diff --git a/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h b/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h index b5f7a5b45..c13b2d2c7 100644 --- a/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h @@ -52,6 +52,12 @@ defined(STM32MP151Dxx) || defined(STM32MP151Fxx) || \ defined(__DOXYGEN__) +/* RCC attributes.*/ +#define STM32_RCC_HAS_PLL3 TRUE +#define STM32_RCC_PLL3_HAS_P TRUE +#define STM32_RCC_PLL3_HAS_Q TRUE +#define STM32_RCC_PLL3_HAS_R TRUE + /* ADC attributes.*/ /* CAN attributes.*/