git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1376 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
parent
2f505cf183
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@ -21,53 +21,11 @@
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#define _BOARD_H_
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/*
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* Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
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*/
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//#define SYSCLK_48
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/*
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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* Board frequencies.
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*/
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#define LSECLK 32768
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#define HSECLK 8000000
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#define HSICLK 8000000
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#define PLLPRE 1
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#ifdef SYSCLK_48
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#define PLLMUL 6
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#else
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#define PLLMUL 9
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#endif
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#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
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#define SYSCLK PLLCLK
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#define APB1CLK (SYSCLK / 2)
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#define APB2CLK (SYSCLK / 2)
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#define AHB1CLK (SYSCLK / 1)
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/*
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* Values derived from the clock settings.
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*/
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#define PLLPREBITS ((PLLPRE - 1) << 17)
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#define PLLMULBITS ((PLLMUL - 2) << 18)
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#ifdef SYSCLK_48
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#define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS
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#define FLASHBITS 0x00000011
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#else
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#define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS
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#define FLASHBITS 0x00000012
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#endif
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/*
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* Extra definitions for RCC_CR register (missing from the ST header file).
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*/
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#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3)
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/*
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* Extra definitions for RCC_CFGR register (missing from the ST header file).
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*/
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#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16)
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#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16)
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#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22)
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#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22)
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/*
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* IO pins assignments.
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@ -21,53 +21,11 @@
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#define _BOARD_H_
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/*
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* Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
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*/
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//#define SYSCLK_48
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/*
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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* Board frequencies.
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*/
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#define LSECLK 32768
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#define HSECLK 8000000
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#define HSICLK 8000000
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#define PLLPRE 1
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#ifdef SYSCLK_48
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#define PLLMUL 6
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#else
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#define PLLMUL 9
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#endif
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#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
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#define SYSCLK PLLCLK
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#define APB1CLK (SYSCLK / 2)
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#define APB2CLK (SYSCLK / 2)
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#define AHB1CLK (SYSCLK / 1)
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/*
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* Values derived from the clock settings.
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*/
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#define PLLPREBITS ((PLLPRE - 1) << 17)
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#define PLLMULBITS ((PLLMUL - 2) << 18)
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#ifdef SYSCLK_48
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#define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS
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#define FLASHBITS 0x00000011
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#else
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#define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS
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#define FLASHBITS 0x00000012
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#endif
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/*
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* Extra definitions for RCC_CR register (missing from the ST header file).
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*/
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#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3)
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/*
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* Extra definitions for RCC_CFGR register (missing from the ST header file).
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*/
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#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16)
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#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16)
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#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22)
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#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22)
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/*
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* IO pins assignments.
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@ -5,9 +5,9 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states)
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*** ChibiOS/RT test suite
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***
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*** Kernel: 1.3.3unstable
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*** Kernel: 1.3.5unstable
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*** Architecture: ARM Cortex-M3
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*** GCC Version: 4.4.1
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*** GCC Version: 4.4.2
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----------------------------------------------------------------------------
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--- Test Case 1.1 (Threads, enqueuing test #1)
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@ -51,6 +51,10 @@
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#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*
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* Calculating the derived clock constants.
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*/
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@ -95,7 +95,7 @@ void hal_lld_init(void) {
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void stm32_clock_init(void) {
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/* HSI setup.*/
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RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION;
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RCC->CR = 0x00000083; /* Reset value, HSI ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Waits until HSI stable. */
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/* HSE setup.*/
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@ -103,7 +103,7 @@ void stm32_clock_init(void) {
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while (!(RCC->CR & RCC_CR_HSERDY))
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; /* Waits until HSE stable. */
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/* PLL setup.*/
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RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;
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RCC->CFGR = RCC_CFGR_PLLSRC | PLLPREBITS | PLLMULBITS;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL stable. */
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@ -41,13 +41,55 @@
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#include "stm32_dma.h"
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver constants. */
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief System clock setting.
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* @note Only 48MHz and 72MHz are currently supported.
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*/
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#if !defined(STM32_SYSCLK) || defined(__DOXYGEN__)
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#define STM32_SYSCLK 72
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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*/
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#define PLLPRE 1
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#if STM32_SYSCLK == 48
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#define PLLMUL 6
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#elif STM32_SYSCLK == 72
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#define PLLMUL 9
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#else
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#error "unsupported STM32_SYSCLK setting"
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#endif
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#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
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#define SYSCLK PLLCLK
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#define APB1CLK (SYSCLK / 2)
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#define APB2CLK (SYSCLK / 2)
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#define AHB1CLK (SYSCLK / 1)
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/*
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* Values derived from the clock settings.
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*/
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#define PLLPREBITS ((PLLPRE - 1) << 17)
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#define PLLMULBITS ((PLLMUL - 2) << 18)
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#if STM32_SYSCLK == 48
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#define USBPREBITS RCC_CFGR_USBPRE
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#define FLASHBITS 0x00000011
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#elif STM32_SYSCLK == 72
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#define USBPREBITS 0
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#define FLASHBITS 0x00000012
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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