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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1376 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2009-12-05 14:59:37 +00:00
parent 2f505cf183
commit 646d8a2376
7 changed files with 58 additions and 92 deletions
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44
demos/ARMCM3-STM32F103-FATFS-GCC/board.h
View File

@ -21,53 +21,11 @@
#define _BOARD_H_ #define _BOARD_H_
/* /*
* Uncomment this if you want a 48MHz system clock, else it will be 72MHz. * Board frequencies.
*/
//#define SYSCLK_48
/*
* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
*/ */
#define LSECLK 32768 #define LSECLK 32768
#define HSECLK 8000000 #define HSECLK 8000000
#define HSICLK 8000000 #define HSICLK 8000000
#define PLLPRE 1
#ifdef SYSCLK_48
#define PLLMUL 6
#else
#define PLLMUL 9
#endif
#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
#define SYSCLK PLLCLK
#define APB1CLK (SYSCLK / 2)
#define APB2CLK (SYSCLK / 2)
#define AHB1CLK (SYSCLK / 1)
/*
* Values derived from the clock settings.
*/
#define PLLPREBITS ((PLLPRE - 1) << 17)
#define PLLMULBITS ((PLLMUL - 2) << 18)
#ifdef SYSCLK_48
#define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS
#define FLASHBITS 0x00000011
#else
#define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS
#define FLASHBITS 0x00000012
#endif
/*
* Extra definitions for RCC_CR register (missing from the ST header file).
*/
#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3)
/*
* Extra definitions for RCC_CFGR register (missing from the ST header file).
*/
#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16)
#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16)
#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22)
#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22)
/* /*
* IO pins assignments. * IO pins assignments.

44
demos/ARMCM3-STM32F103-GCC/board.h
View File

@ -21,53 +21,11 @@
#define _BOARD_H_ #define _BOARD_H_
/* /*
* Uncomment this if you want a 48MHz system clock, else it will be 72MHz. * Board frequencies.
*/
//#define SYSCLK_48
/*
* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
*/ */
#define LSECLK 32768 #define LSECLK 32768
#define HSECLK 8000000 #define HSECLK 8000000
#define HSICLK 8000000 #define HSICLK 8000000
#define PLLPRE 1
#ifdef SYSCLK_48
#define PLLMUL 6
#else
#define PLLMUL 9
#endif
#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
#define SYSCLK PLLCLK
#define APB1CLK (SYSCLK / 2)
#define APB2CLK (SYSCLK / 2)
#define AHB1CLK (SYSCLK / 1)
/*
* Values derived from the clock settings.
*/
#define PLLPREBITS ((PLLPRE - 1) << 17)
#define PLLMULBITS ((PLLMUL - 2) << 18)
#ifdef SYSCLK_48
#define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS
#define FLASHBITS 0x00000011
#else
#define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS
#define FLASHBITS 0x00000012
#endif
/*
* Extra definitions for RCC_CR register (missing from the ST header file).
*/
#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3)
/*
* Extra definitions for RCC_CFGR register (missing from the ST header file).
*/
#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16)
#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16)
#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22)
#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22)
/* /*
* IO pins assignments. * IO pins assignments.

4
docs/reports/STM32F103-72.txt
View File

@ -5,9 +5,9 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states)
*** ChibiOS/RT test suite *** ChibiOS/RT test suite
*** ***
*** Kernel: 1.3.3unstable *** Kernel: 1.3.5unstable
*** Architecture: ARM Cortex-M3 *** Architecture: ARM Cortex-M3
*** GCC Version: 4.4.1 *** GCC Version: 4.4.2
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
--- Test Case 1.1 (Threads, enqueuing test #1) --- Test Case 1.1 (Threads, enqueuing test #1)

4
os/hal/platforms/MSP430/hal_lld.h
View File

@ -51,6 +51,10 @@
#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK #define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK
#endif #endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* /*
* Calculating the derived clock constants. * Calculating the derived clock constants.
*/ */

4
os/hal/platforms/STM32/hal_lld.c
View File

@ -95,7 +95,7 @@ void hal_lld_init(void) {
void stm32_clock_init(void) { void stm32_clock_init(void) {
/* HSI setup.*/ /* HSI setup.*/
RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION; RCC->CR = 0x00000083; /* Reset value, HSI ON. */
while (!(RCC->CR & RCC_CR_HSIRDY)) while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Waits until HSI stable. */ ; /* Waits until HSI stable. */
/* HSE setup.*/ /* HSE setup.*/
@ -103,7 +103,7 @@ void stm32_clock_init(void) {
while (!(RCC->CR & RCC_CR_HSERDY)) while (!(RCC->CR & RCC_CR_HSERDY))
; /* Waits until HSE stable. */ ; /* Waits until HSE stable. */
/* PLL setup.*/ /* PLL setup.*/
RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; RCC->CFGR = RCC_CFGR_PLLSRC | PLLPREBITS | PLLMULBITS;
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL stable. */ ; /* Waits until PLL stable. */

46
os/hal/platforms/STM32/hal_lld.h
View File

@ -41,13 +41,55 @@
#include "stm32_dma.h" #include "stm32_dma.h"
/*===========================================================================*/ /*===========================================================================*/
/* Driver pre-compile time settings. */ /* Driver constants. */
/*===========================================================================*/ /*===========================================================================*/
/*===========================================================================*/ /*===========================================================================*/
/* Driver constants. */ /* Driver pre-compile time settings. */
/*===========================================================================*/ /*===========================================================================*/
/**
* @brief System clock setting.
* @note Only 48MHz and 72MHz are currently supported.
*/
#if !defined(STM32_SYSCLK) || defined(__DOXYGEN__)
#define STM32_SYSCLK 72
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*
* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
*/
#define PLLPRE 1
#if STM32_SYSCLK == 48
#define PLLMUL 6
#elif STM32_SYSCLK == 72
#define PLLMUL 9
#else
#error "unsupported STM32_SYSCLK setting"
#endif
#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
#define SYSCLK PLLCLK
#define APB1CLK (SYSCLK / 2)
#define APB2CLK (SYSCLK / 2)
#define AHB1CLK (SYSCLK / 1)
/*
* Values derived from the clock settings.
*/
#define PLLPREBITS ((PLLPRE - 1) << 17)
#define PLLMULBITS ((PLLMUL - 2) << 18)
#if STM32_SYSCLK == 48
#define USBPREBITS RCC_CFGR_USBPRE
#define FLASHBITS 0x00000011
#elif STM32_SYSCLK == 72
#define USBPREBITS 0
#define FLASHBITS 0x00000012
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver data structures and types. */ /* Driver data structures and types. */
/*===========================================================================*/ /*===========================================================================*/

4
os/hal/templates/hal_lld.h
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@ -35,6 +35,10 @@
/* Driver constants. */ /* Driver constants. */
/*===========================================================================*/ /*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/ /*===========================================================================*/
/* Driver data structures and types. */ /* Driver data structures and types. */
/*===========================================================================*/ /*===========================================================================*/