Updated mcuconf.h according to last PLLI2S enhancements.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9544 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -55,11 +55,14 @@
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#define STM32_RTCPRE_VALUE 8
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#define STM32_RTCPRE_VALUE 8
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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#define STM32_PLLI2SM_VALUE 4
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SP_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_RTCPRE_VALUE 8
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#define STM32_RTCPRE_VALUE 8
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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#define STM32_PLLI2SM_VALUE 4
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SP_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_RTCPRE_VALUE 8
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#define STM32_RTCPRE_VALUE 8
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2SEL STM32_MCO2SEL_PLLI2S
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV1
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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#define STM32_PLLI2SR_VALUE 4
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#define STM32_PLLI2SQ_VALUE 4
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_BKPRAM_ENABLE FALSE
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*****************************************************************************
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*****************************************************************************
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*** Next ***
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*** Next ***
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- HAL: Extended PLLI2S for STM32F4xx subfamily.
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- HAL: Added QSPI driver implementation for STM32.
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- HAL: Added QSPI driver implementation for STM32.
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- HAL: Added QSPI driver model.
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- HAL: Added QSPI driver model.
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- VAR: Cortex-M VTOR initialization is now performed in startup files and
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- VAR: Cortex-M VTOR initialization is now performed in startup files and
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