RP WDGv1 WIP

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14192 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
cinsights 2021-04-15 13:30:03 +00:00
parent 726aa34df0
commit 6548dd4a56
3 changed files with 17 additions and 10 deletions

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@ -63,6 +63,9 @@ void wdg_lld_init(void) {
WDGD1.state = WDG_STOP; WDGD1.state = WDG_STOP;
WDGD1.wdg = WATCHDOG; WDGD1.wdg = WATCHDOG;
#if WDG_HAS_STORAGE
WDGD1.scratch = SCRATCH;
#endif
WDGD1.wdg->CRTL &= ~WATCHDOG_CTRL_ENABLE; WDGD1.wdg->CRTL &= ~WATCHDOG_CTRL_ENABLE;
} }
@ -77,21 +80,15 @@ void wdg_lld_start(WDGDriver *wdgp) {
/* Set the time. */ /* Set the time. */
uint32_t time = wdgp->wdg->config.rlr; uint32_t time = wdgp->wdg->config.rlr;
if (time == 0U) {
time = 50;
}
/* Due to a silicon bug (see errata RP2040-E1) WDG counts down on each edge. */ /* Due to a silicon bug (see errata RP2040-E1) WDG counts down at each edge. */
time = (time == 0U) ? (50 * 2 * 1000) : (time * 2 * 1000); time = ((time == 0U) ? 50 : time) * 2 * 1000;
/* Set ceiling if greater than count capability. */ /* Set ceiling if greater than count capability. */
if (time > WATCHDOG_CTRL_TIME) { if (time > WATCHDOG_CTRL_TIME) {
time = WATCHDOG_CTRL_TIME; time = WATCHDOG_CTRL_TIME;
} }
/* Save the reload count. */
wdgp->wdg->rlr = time;
/* Set the initial interval, state, control bits and enable WDG. */ /* Set the initial interval, state, control bits and enable WDG. */
wdgp->wdg->LOAD = time; wdgp->wdg->LOAD = time;
wdgp->state = WDG_READY; wdgp->state = WDG_READY;
@ -122,7 +119,7 @@ void wdg_lld_stop(WDGDriver *wdgp) {
*/ */
void wdg_lld_reset(WDGDriver * wdgp) { void wdg_lld_reset(WDGDriver * wdgp) {
wdgp->wdg->LOAD = wdgp->rlr; wdgp->wdg->LOAD = wdgp->wdg->config.rlr;
} }
#endif /* HAL_USE_WDG */ #endif /* HAL_USE_WDG */

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@ -95,6 +95,12 @@ struct WDGDriver {
* @brief Pointer to the WATCHDOG registers block. * @brief Pointer to the WATCHDOG registers block.
*/ */
WATCHDOG_TypeDef *wdg; WATCHDOG_TypeDef *wdg;
/**
* @brief Pointer to the WATCHDOG scratch storage.
*/
#if WDG_HAS_STORAGE
uint8_t *scratch;
#endif
}; };
/*===========================================================================*/ /*===========================================================================*/

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@ -52,6 +52,10 @@
/* RTC attributes.*/ /* RTC attributes.*/
#define RP_HAS_RTC TRUE #define RP_HAS_RTC TRUE
/* WDG attributes.*/
#define RP_HAS_WDG TRUE
#define RP_WDG_STORAGE_SIZE 32U
/** @} */ /** @} */
#endif /* RP_REGISTRY_H */ #endif /* RP_REGISTRY_H */