git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9968 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
b70eb4b288
commit
65b57a9e9e
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@ -80,7 +80,7 @@
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<link>
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<name>board</name>
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<type>2</type>
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<locationURI>CHIBIOS/os/hal/boards/OLIMEX_STM32_E407</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/OLIMEX_STM32_P107</locationURI>
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</link>
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<link>
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<name>fatfs</name>
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@ -88,24 +88,21 @@ PROJECT = ch
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# Imported source files and paths
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CHIBIOS = ../../..
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# Startup files.
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include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
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include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk
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# HAL-OSAL files (optional).
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk
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include $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_E407/board.mk
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include $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk
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include $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_P107/board.mk
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include $(CHIBIOS)/os/hal/osal/rt/osal.mk
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# RTOS files (optional).
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include $(CHIBIOS)/os/rt/rt.mk
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include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
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# Other files (optional).
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include $(CHIBIOS)/test/rt/test.mk
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include $(CHIBIOS)/os/hal/lib/streams/streams.mk
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include $(CHIBIOS)/os/various/shell/shell.mk
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include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk
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include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk
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# Define linker script file here
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LDSCRIPT= $(STARTUPLD)/STM32F407xG.ld
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LDSCRIPT= $(STARTUPLD)/STM32F107xC.ld
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# C sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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@ -118,11 +115,7 @@ CSRC = $(STARTUPSRC) \
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$(BOARDSRC) \
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$(TESTSRC) \
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$(LWSRC) \
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$(FATFSSRC) \
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$(STREAMSSRC) \
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$(SHELLSRC) \
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$(CHIBIOS)/os/various/evtimer.c \
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web/web.c usbcfg.c main.c
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web/web.c main.c
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# C++ sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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@ -155,7 +148,7 @@ ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
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INCDIR = $(CHIBIOS)/os/license \
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$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
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$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
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$(STREAMSINC) $(SHELLINC) $(LWINC) $(FATFSINC) \
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$(LWINC) \
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$(CHIBIOS)/os/various
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#
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@ -166,7 +159,7 @@ INCDIR = $(CHIBIOS)/os/license \
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# Compiler settings
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#
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MCU = cortex-m4
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MCU = cortex-m3
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#TRGT = arm-elf-
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TRGT = arm-none-eabi-
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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ChibiOSch_ - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -14,247 +14,27 @@
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limitations under the License.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "ch.h"
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#include "hal.h"
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#include "ch_test.h"
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#include "chprintf.h"
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#include "shell.h"
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#include "lwipthread.h"
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#include "web/web.h"
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#include "ff.h"
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#include "usbcfg.h"
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/*===========================================================================*/
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/* Card insertion monitor. */
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/*===========================================================================*/
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#define POLLING_INTERVAL 10
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#define POLLING_DELAY 10
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/**
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* @brief Card monitor timer.
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*/
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static virtual_timer_t tmr;
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/**
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* @brief Debounce counter.
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*/
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static unsigned cnt;
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/**
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* @brief Card event sources.
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*/
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static event_source_t inserted_event, removed_event;
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/**
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* @brief Insertion monitor timer callback function.
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*
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* @param[in] p pointer to the @p BaseBlockDevice object
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*
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* @notapi
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*/
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static void tmrfunc(void *p) {
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BaseBlockDevice *bbdp = p;
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chSysLockFromISR();
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if (cnt > 0) {
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if (blkIsInserted(bbdp)) {
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if (--cnt == 0) {
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chEvtBroadcastI(&inserted_event);
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}
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}
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else
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cnt = POLLING_INTERVAL;
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}
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else {
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if (!blkIsInserted(bbdp)) {
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cnt = POLLING_INTERVAL;
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chEvtBroadcastI(&removed_event);
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}
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}
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chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, bbdp);
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chSysUnlockFromISR();
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}
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/**
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* @brief Polling monitor start.
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*
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* @param[in] p pointer to an object implementing @p BaseBlockDevice
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*
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* @notapi
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*/
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static void tmr_init(void *p) {
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chEvtObjectInit(&inserted_event);
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chEvtObjectInit(&removed_event);
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chSysLock();
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cnt = POLLING_INTERVAL;
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chVTSetI(&tmr, MS2ST(POLLING_DELAY), tmrfunc, p);
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chSysUnlock();
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}
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/*===========================================================================*/
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/* FatFs related. */
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/*===========================================================================*/
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/**
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* @brief FS object.
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*/
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static FATFS SDC_FS;
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/* FS mounted and ready.*/
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static bool fs_ready = FALSE;
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/* Generic large buffer.*/
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static uint8_t fbuff[1024];
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static FRESULT scan_files(BaseSequentialStream *chp, char *path) {
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FRESULT res;
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FILINFO fno;
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DIR dir;
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int i;
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char *fn;
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#if _USE_LFN
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fno.lfname = 0;
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fno.lfsize = 0;
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#endif
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res = f_opendir(&dir, path);
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if (res == FR_OK) {
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i = strlen(path);
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for (;;) {
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res = f_readdir(&dir, &fno);
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if (res != FR_OK || fno.fname[0] == 0)
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break;
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if (fno.fname[0] == '.')
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continue;
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fn = fno.fname;
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if (fno.fattrib & AM_DIR) {
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path[i++] = '/';
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strcpy(&path[i], fn);
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res = scan_files(chp, path);
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if (res != FR_OK)
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break;
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path[--i] = 0;
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}
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else {
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chprintf(chp, "%s/%s\r\n", path, fn);
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}
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}
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}
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return res;
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}
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/*===========================================================================*/
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/* Command line related. */
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/*===========================================================================*/
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#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
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static void cmd_tree(BaseSequentialStream *chp, int argc, char *argv[]) {
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FRESULT err;
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uint32_t clusters;
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FATFS *fsp;
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(void)argv;
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if (argc > 0) {
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chprintf(chp, "Usage: tree\r\n");
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return;
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}
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if (!fs_ready) {
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chprintf(chp, "File System not mounted\r\n");
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return;
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}
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err = f_getfree("/", &clusters, &fsp);
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if (err != FR_OK) {
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chprintf(chp, "FS: f_getfree() failed\r\n");
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return;
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}
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chprintf(chp,
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"FS: %lu free clusters, %lu sectors per cluster, %lu bytes free\r\n",
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clusters, (uint32_t)SDC_FS.csize,
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clusters * (uint32_t)SDC_FS.csize * (uint32_t)MMCSD_BLOCK_SIZE);
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fbuff[0] = 0;
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scan_files(chp, (char *)fbuff);
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}
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static const ShellCommand commands[] = {
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{"tree", cmd_tree},
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{NULL, NULL}
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};
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static const ShellConfig shell_cfg1 = {
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(BaseSequentialStream *)&SDU1,
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commands
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};
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/*===========================================================================*/
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/* Main and generic code. */
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/*===========================================================================*/
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static thread_t *shelltp = NULL;
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/*
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* Card insertion event.
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*/
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static void InsertHandler(eventid_t id) {
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FRESULT err;
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(void)id;
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/*
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* On insertion SDC initialization and FS mount.
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*/
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if (sdcConnect(&SDCD1))
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return;
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err = f_mount(&SDC_FS, "/", 1);
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if (err != FR_OK) {
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sdcDisconnect(&SDCD1);
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return;
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}
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fs_ready = TRUE;
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}
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/*
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* Card removal event.
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*/
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static void RemoveHandler(eventid_t id) {
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(void)id;
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sdcDisconnect(&SDCD1);
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fs_ready = FALSE;
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}
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/*
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* Shell exit event.
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*/
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static void ShellHandler(eventid_t id) {
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(void)id;
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if (chThdTerminatedX(shelltp)) {
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chThdWait(shelltp); /* Returning memory to heap. */
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shelltp = NULL;
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}
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}
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/*
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* Green LED blinker thread, times are in milliseconds.
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*/
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static THD_WORKING_AREA(waThread1, 128);
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static THD_FUNCTION(Thread1, arg) {
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static WORKING_AREA(waThread1, 128);
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static msg_t Thread1(void *arg) {
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(void)arg;
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chRegSetThreadName("blinker");
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while (true) {
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palTogglePad(GPIOC, GPIOC_LED);
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chThdSleepMilliseconds(fs_ready ? 125 : 500);
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while (TRUE) {
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palClearPad(GPIOC, GPIOC_LED_STATUS1);
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chThdSleepMilliseconds(500);
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palSetPad(GPIOC, GPIOC_LED_STATUS1);
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chThdSleepMilliseconds(500);
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}
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}
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@ -262,12 +42,6 @@ static THD_FUNCTION(Thread1, arg) {
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* Application entry point.
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*/
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int main(void) {
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static const evhandler_t evhndl[] = {
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InsertHandler,
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RemoveHandler,
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ShellHandler
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};
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event_listener_t el0, el1, el2;
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/*
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* System initializations.
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@ -275,44 +49,15 @@ int main(void) {
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* and performs the board-specific initializations.
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* - Kernel initialization, the main() function becomes a thread and the
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* RTOS is active.
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* - lwIP subsystem initialization using the default configuration.
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*/
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halInit();
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chSysInit();
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lwipInit(NULL);
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/*
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* Initializes a serial-over-USB CDC driver.
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* Activates the serial driver 3 using the driver default configuration.
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*/
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sduObjectInit(&SDU1);
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sduStart(&SDU1, &serusbcfg);
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/*
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* Activates the USB driver and then the USB bus pull-up on D+.
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* Note, a delay is inserted in order to not have to disconnect the cable
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* after a reset.
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*/
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usbDisconnectBus(serusbcfg.usbp);
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chThdSleepMilliseconds(1500);
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usbStart(serusbcfg.usbp, &usbcfg);
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usbConnectBus(serusbcfg.usbp);
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/*
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* Shell manager initialization.
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*/
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shellInit();
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/*
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* Activates the serial driver 6 and SDC driver 1 using default
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* configuration.
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*/
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sdStart(&SD6, NULL);
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sdcStart(&SDCD1, NULL);
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/*
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* Activates the card insertion monitor.
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*/
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tmr_init(&SDCD1);
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sdStart(&SD3, NULL);
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/*
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* Creates the blinker thread.
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@ -326,18 +71,12 @@ int main(void) {
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http_server, NULL);
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/*
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* Normal main() thread activity, handling SD card events and shell
|
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* start/exit.
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* Normal main() thread activity, in this demo it does nothing except
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* sleeping in a loop and check the button state.
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*/
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chEvtRegister(&inserted_event, &el0, 0);
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chEvtRegister(&removed_event, &el1, 1);
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chEvtRegister(&shell_terminated, &el2, 2);
|
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while (true) {
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if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE)) {
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shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE,
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"shell", NORMALPRIO + 1,
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shellThread, (void *)&shell_cfg1);
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}
|
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chEvtDispatch(evhndl, chEvtWaitOneTimeout(ALL_EVENTS, MS2ST(500)));
|
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if (palReadPad(GPIOC, GPIOC_SWITCH_TAMPER) == 0)
|
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TestThread(&SD3);
|
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chThdSleepMilliseconds(500);
|
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}
|
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}
|
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|
|
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|
|
@ -17,8 +17,10 @@
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#ifndef MCUCONF_H
|
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#define MCUCONF_H
|
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|
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#define STM32F103_MCUCONF
|
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|
||||
/*
|
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* STM32F4xx drivers configuration.
|
||||
* STM32F103 drivers configuration.
|
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* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
|
|
@ -31,77 +33,41 @@
|
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* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F4xx_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT FALSE
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_LSI_ENABLED FALSE
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#define STM32_CLOCK48_REQUIRED TRUE
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_PLLM_VALUE 12
|
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#define STM32_PLLN_VALUE 336
|
||||
#define STM32_PLLP_VALUE 2
|
||||
#define STM32_PLLQ_VALUE 7
|
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV4
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#define STM32_RTCPRE_VALUE 8
|
||||
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
|
||||
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
|
||||
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
|
||||
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
|
||||
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
||||
#define STM32_PLLI2SN_VALUE 192
|
||||
#define STM32_PLLI2SR_VALUE 5
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_USB_CLOCK_REQUIRED TRUE
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_RTCSEL STM32_RTCSEL_HSEDIV
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_BKPRAM_ENABLE FALSE
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_USE_ADC2 FALSE
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||||
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#define STM32_ADC_IRQ_PRIORITY 6
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
|
||||
#define STM32_ADC_ADC1_IRQ_PRIORITY 6
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 FALSE
|
||||
#define STM32_CAN_USE_CAN2 FALSE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH1 FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH2 FALSE
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
|
|
@ -114,12 +80,9 @@
|
|||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
|
||||
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
|
|
@ -129,62 +92,26 @@
|
|||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM5 FALSE
|
||||
#define STM32_GPT_USE_TIM6 FALSE
|
||||
#define STM32_GPT_USE_TIM7 FALSE
|
||||
#define STM32_GPT_USE_TIM8 FALSE
|
||||
#define STM32_GPT_USE_TIM9 FALSE
|
||||
#define STM32_GPT_USE_TIM11 FALSE
|
||||
#define STM32_GPT_USE_TIM12 FALSE
|
||||
#define STM32_GPT_USE_TIM14 FALSE
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 FALSE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_USE_I2C3 FALSE
|
||||
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY 3
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI2 FALSE
|
||||
#define STM32_I2S_USE_SPI3 FALSE
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
|
|
@ -194,25 +121,12 @@
|
|||
#define STM32_ICU_USE_TIM4 FALSE
|
||||
#define STM32_ICU_USE_TIM5 FALSE
|
||||
#define STM32_ICU_USE_TIM8 FALSE
|
||||
#define STM32_ICU_USE_TIM9 FALSE
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define STM32_MAC_TRANSMIT_BUFFERS 2
|
||||
#define STM32_MAC_RECEIVE_BUFFERS 4
|
||||
#define STM32_MAC_BUFFERS_SIZE 1522
|
||||
#define STM32_MAC_PHY_TIMEOUT 100
|
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
|
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
|
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
|
|
@ -224,25 +138,17 @@
|
|||
#define STM32_PWM_USE_TIM4 FALSE
|
||||
#define STM32_PWM_USE_TIM5 FALSE
|
||||
#define STM32_PWM_USE_TIM8 FALSE
|
||||
#define STM32_PWM_USE_TIM9 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_SDIO_DMA_PRIORITY 3
|
||||
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
|
||||
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
|
||||
#define STM32_SDC_READ_TIMEOUT_MS 1000
|
||||
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
|
||||
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
|
||||
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_RTC_IRQ_PRIORITY 15
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
|
|
@ -252,13 +158,11 @@
|
|||
#define STM32_SERIAL_USE_USART3 FALSE
|
||||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USE_USART6 TRUE
|
||||
#define STM32_SERIAL_USART1_PRIORITY 12
|
||||
#define STM32_SERIAL_USART2_PRIORITY 12
|
||||
#define STM32_SERIAL_USART3_PRIORITY 12
|
||||
#define STM32_SERIAL_UART4_PRIORITY 12
|
||||
#define STM32_SERIAL_UART5_PRIORITY 12
|
||||
#define STM32_SERIAL_USART6_PRIORITY 12
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
|
|
@ -266,12 +170,6 @@
|
|||
#define STM32_SPI_USE_SPI1 FALSE
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
|
|
@ -292,47 +190,21 @@
|
|||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART3 FALSE
|
||||
#define STM32_UART_USE_UART4 FALSE
|
||||
#define STM32_UART_USE_UART5 FALSE
|
||||
#define STM32_UART_USE_USART6 FALSE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||||
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 TRUE
|
||||
#define STM32_USB_USE_OTG2 FALSE
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
|
||||
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
|
||||
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
|
||||
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
|
||||
#define STM32_USB_USE_USB1 TRUE
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
|
|
|
|||
Loading…
Reference in New Issue